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| * | am335x_evm: Enable CONFIG_NAND_OMAP_GPMC_PREFETCHTom Rini2015-01-29-0/+1
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * | ARM: OMAP5: DRA7xx: Add support for power rail groupingLubomir Popov2015-01-29-28/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC core rails. This concept of using one SMPS to supply multiple core domains (in various, although limited combinations, per primary device use case) has now become common and is used by many customer J6/J6Eco designs; it is supported by a number of corresponding PMIC OTP versions. This patch implements correct operation of the core voltages scaling routine by ensuring that each SMPS that is supplying more than one domain shall be written only once, and with the highest voltage of those fused in the SoC (or of those defined in the corresponding header if fuse read is disabled or fails) for the power rails belonging to the group. The patch also replaces some PMIC-related magic numbers with the appropriate definitions. The default OPP_NOM voltages for the DRA7xx SoCs are updated as well, per the latest DMs. Signed-off-by: Lubomir Popov <l-popov@ti.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-blackfinTom Rini2015-02-02-3/+3
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| * | | bfin: make env offset sector aligned for bct-brettl2 and ibf-dsp561 boardsSonic Zhang2015-01-16-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | | bfin: enlarge the monitor size for ip04 board to avoid oversize link errorSonic Zhang2015-01-16-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2015-02-02-331/+490
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| * | | | sunxi: mmc: Add 'sunxi_' prefix to the static functionsSiarhei Siamashka2015-02-02-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This results in a much more readable callgraph, because now they can't be confused with the function having exactly the same name in the generic mmc code. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: dram: Support more sun[457]i dram parameters in KconfigSiarhei Siamashka2015-02-02-3/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows to configure all the important DRAM parameters in Kconfig. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: dram: Optionally use standard JEDEC timings for sun[457]iSiarhei Siamashka2015-02-02-4/+249
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to the current Android magic settings, allow to optionally use DDR3 timing parameters, which are tailored for different clock frequencies and JEDEC speed bins. This should improve reliability and performance. Adding '+S:CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H=y' to the board defconfig allows to use timings, which are calculated for the DDR3-1066F speed bin. A lot of DDR3 chips, which are used in real Allwinner based devices, support DDR3-1066F speed bin timings. And adding '+S:CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y' should work with any DDR3 chips, because this targets the slowest JEDEC speed bins. The vendor magic values are still used by default for DRAM, but board maintainers now have more flexibility in DRAM timings selection. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: video: Force h/vsync active high when using ext. vga dac on some boardsHans de Goede2015-02-02-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On both my A13-OLinuxIno and my A13-OLinuxIno-Micro, the vga output gives an unstable image when active low v or hsync is used. The problem seems to be specific to the OLinuxIno A13 (normal & micro) boards. I've just looked up the schematics and they use an opendrain driver for the vga sync lines, and with sync pulses it is the logical high->low edge of the pulse which counts for the timing, which with an active low sync is being driven by the pull-up, and that simply seems to not drive it hard enough to get a stable image. So force v and hsync active high on these boards. independent of what the modeline says. This fixes the unstable image. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | sunxi: Add Inet 86VS supportMichal Suchanek2015-02-02-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Michal Suchanek <hramrach@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: TZX-Q8-713B7 supportPaul Kocialkowski2015-02-02-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: Add Linksprite_pcDuino3_Nano board / defconfigAdam Sampson2015-02-02-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a low-cost Allwinner A20 board with Arduino-style GPIO headers; it features 1G RAM, 4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro USB socket for OTG and another for power in, HDMI, SATA, 5V power for SATA devices, gigabit Ethernet, an IR receiver, 3.5mm audio out and a MIPI camera connector. Like the BananaPi, this board needs GMAC_TX_DELAY set to 3 in order for GMAC to work reliably at gigabit speeds. For more details, see: http://linux-sunxi.org/LinkSprite_pcDuino3_Nano Signed-off-by: Adam Sampson <ats@offog.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: MAINTAINERS: sort entries alphabeticallyHans de Goede2015-02-02-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keep all entries except for the monster entry at the top alphabetically sorted. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: rsb: Move rsb_set_device_mode() call to rsb_init()Hans de Goede2015-02-02-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that the device_mode_data is rsb specific, rather then slave specific, so integrate the rsb_set_device_mode() call into rsb_init(). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | sunxi: rsb: Add sun9i (A80 support)Hans de Goede2015-02-02-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the A80 to the rsb code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | sunxi: Remove CONFIG_TARGET_FOO for sun5i and sun7i boardsHans de Goede2015-02-02-101/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_TARGET_FOO was only used in board/sunxi/Makefile to select the dram config for sun5i and sun7i boards and in board/sunxi/gmac.c for some special handling of the bananapi/bananapro (both sun7i), all sun5i and sun7i boards have been moved over to using a single dram_sun5i_autoconfig file, and the tx clk delay handling for the Banana boards now has its own Kconfig. IOW nothing is using CONFIG_TARGET_FOO anymore, so remove it. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | sunxi: Add a GMAC Transmit Clock Delay Chain Kconfig optionHans de Goede2015-02-02-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | And use this to set the GMAC Transmit Clock Delay Chain value on Banana boards, rather then keying of CONFIG_TARGET_FOO. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | sunxi: Convert sun5i boards to use auto dram configurationHans de Goede2015-02-02-169/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we've separate detailed dram settings for all sun5i boards, this moves them over to using auto dram configuration so that we can get rid of all the per board dram_foo.c files. This has been tested on a A10s-Olinuxino, A13-Olinuxino, A13-OlinuxinoM, mk802-a10s and r7-tv-dongle board. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | sunxi: Hyundai_A7HD_defconfig fix USB vbus pin configHans de Goede2015-02-02-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB1_VBUS is not used, and USB2_VBUS uses the pin normally used to control USB1_VBUS. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: Only enable i2c support in the SPL when neededHans de Goede2015-02-02-0/+3
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We do not need i2c support in the SPL when there is no PMIC (some sun4i boards), or when the PMIC is not using i2c such as on sun6i and sun8i. This reduces the SPL size from (e.g.) 21812 to 19260 bytes. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | | Merge branch 'patman' of git://git.denx.de/u-boot-x86Tom Rini2015-01-31-26/+45
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| * | | | patman: Explain how to make doc/git-mailrc workSimon Glass2015-01-30-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an explanation for how to set up git so that patman can find the alias file. Fix up the get_maintainers message too. Reported-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | sandbox: Fix README to indicate that vendor name is unsetSimon Glass2015-01-30-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This brings in a additional small fix which was missed in a recent update to the README. Suggested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | | patman: Check commit_match before stripping leading whitespaceScott Wood2015-01-30-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | True commit lines start at column zero. Anything that is indented is part of the commit message instead. I noticed this by trying to run buildman with commit e3a4facdfc07179ebe017a07b8de6224a935a9f3 as master, which contained a reference to a Linux commit inside the commit message. ProcessLine saw that as a genuite commit line, and thus buildman tried to build it, and died with an exception because that SHA is not present in the U-Boot tree. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | patman: Make dry-run output match real functionalityPeter Tyser2015-01-30-14/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When run with the --dry-run argument patman prints out information showing what it would do. This information currently doesn't line up with what patman/git send-email really do. Some basic examples: - If an email address is addressed via "Series-cc" and "Patch-cc" patman shows that email address would be CC-ed two times. - If an email address is addressed via "Series-to" and "Patch-cc" patman shows that email address would be sent TO and CC-ed. - If an email address is addressed from a combination of tag aliases, get_maintainer.pl output, "Series-cc", "Patch-cc", etc patman shows that the email address would be CC-ed multiple times. Patman currently does try to send duplicate emails like the --dry-run output shows, but "git send-email" intelligently removes duplicate addresses so this patch shouldn't change the non-dry-run functionality. Change patman's output and email addressing to line up with the "git send-email" logic. This trims down patman's dry-run output and prevents confusion about what patman will do when emails are actually sent. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * | | | sandbox: Add a -D option to use a default device treeSimon Glass2015-01-30-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is painful to specify the full path to the device tree with the -d option. It is normally kept in the same directory as U-Boot, so provide an option to use this by default. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | sandbox: Correct cros-ec keyboard definitionSimon Glass2015-01-30-4/+2
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | The other boards got updated to the standard binding. Update sandbox as well. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2015-01-31-2/+93
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| * | | | net/designware: add error message on DMA reset timeoutAlexey Brodkin2015-01-30-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If for some reason DMA module fails to reset user oserves only this: --->--- # dhcp Trying dwmac.e0018000 FAIL --->--- This message makes not much sense. With proposed change error message will be more helpful: --->--- # dhcp Trying dwmac.e0018000 DMA reset timeout FAIL --->--- For example user may do power toggle to recover board functionality. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | | net: phy: micrel: add support for KSZ8895 switch in SMI modePhilippe De Muyter2015-01-30-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a phy driver for the Micrel KSZ8895 switch. As the SoC MAC is directly connected to the switch MAC the link to the switch is always up. But the KSZ8895 switch can be hardwired in three configuration modes : - not configurable with eventually an eeprom-stored configuration - configurable by the mdio/mdc connection (SMI protocol) - configurable by a SPI connection. In not configurable mode, the switch starts automatically, but in the other modes, it must be started programmatically, by writing 1 in configuration register 1. We only support the not configurable and mdio/mdc (aka SMI) modes here. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | | Add MS7206SE ethernet supportYoshinori Sato2015-01-30-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | | net: tsec: Fix NULL access in case init_phy() failsClaudiu Manoil2015-01-30-0/+2
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the PHY is not recognized don't access phydev (NULL) and return 0 to signal failure. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2015-01-30-912/+303
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| * | | | MIPS: unify CPU code in arch/mips/cpu/Daniel Schwierzeck2015-01-30-389/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unify and move code in arch/mips/cpu/mips[32|64]/ to arch/mips/cpu/. The CPU specific config.mk files need to remain until CONFIG_STANDALONE_LOAD_ADDR is converted to a global Kconfig symbol. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | MIPS: move au1x00 SoC code to arch/mips/mach-au1x00Daniel Schwierzeck2015-01-30-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move all au1x00 code out of arch/mips/cpu/mips32 to allow unification of CPU code in a later patch. The reorganization of the SoC specific header files will be done in a later patch series. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
| * | | | MIPS: handle mips64 ST0_KX bit in mips32 start.SPaul Burton2015-01-30-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for sharing a single copy of start.S between mips32 & mips64, handle setting the KX bit of the cop0 Status register when the mips32 start.S is built for mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | MIPS: handle mips64 relocs in mips32 start.SPaul Burton2015-01-30-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for sharing a single copy of start.S between mips32 & mips64, handle mips64 relocations in the mips32 start.S when built for mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | MIPS: use asm.h macros in mips32 start.SPaul Burton2015-01-30-55/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Where the mips32 & mips64 implementations of start.S differ in terms of access sizes & offsets, use the appropriate macros from asm.h to abstract those differences away. This is in preparation for sharing a single copy of start.S between mips32 & mips64. The exception to this is loads of immediates to be written to the cop0 Config register, which is a 32bit register on mips64 and therefore constants written to it can be loaded as such. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | malta: enable ELF loadingPaul Burton2015-01-29-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ability to load ELF files is sometimes useful on Malta boards, particularly for use with small embedded applications. Enable the loadelf command in the malta config. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | malta: enable HUSH parserPaul Burton2015-01-29-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The malta board is used for development and thus the shell is interacted with often. Enable HUSH to make the experience a little more pleasant. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | malta: delay after resetPaul Burton2015-01-29-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reset isn't instant, so delay to give it a chance. Otherwise we go on to print a failure message before resetting anyway. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | malta: IDE supportPaul Burton2015-01-29-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds IDE support to the MIPS Malta board. The IDE controller is enabled after probing the PCI bus and otherwise just makes use of U-boot generic IDE support. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | MIPS: clear TagLo select 2 during cache initPaul Burton2015-01-29-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current MIPS cores from Imagination Technologies use TagLo select 2 for the data cache. The architecture requires that it is safe for software to write to this register even if it isn't present, so take the trivial option of clearing both selects 0 & 2. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | MIPS: allow systems to skip loads during cache initPaul Burton2015-01-29-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current MIPS systems do not require that loads be performed to force the parity of cache lines, a simple invalidate by clearing the tag for each line will suffice. Thus this patch makes the loads & subsequent second invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD option, and defines that for existing mips32 targets. Exceptions are malta where this is known to be unnecessary, and qemu-mips where caches are not implemented. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | MIPS: inline mips_init_[id]cache functionsPaul Burton2015-01-29-58/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mips_init_[id]cache functions are small & only called once from a single callsite. Inlining them allows mips_cache_reset to avoid having to bother moving arguments around & leaves it a leaf function which is thus able to simply keep the return address live in the ra register throughout, simplifying the code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | MIPS: refactor cache loops to a macroPaul Burton2015-01-29-17/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reduce duplication by performing loops through cache tags using an assembler macro. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | MIPS: refactor L1 cache config reads to a macroPaul Burton2015-01-29-56/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reduce duplication between reading the configuration of the L1 dcache & icache by performing both using a macro which calculates the appropriate line & cache sizes from the coprocessor 0 Config1 register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | MIPS: unify cache initialization codePaul Burton2015-01-29-224/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mips32 & mips64 cache initialization code differs only in that the mips32 code supports reading the cache size from coprocessor 0 registers at runtime. Move the more developed mips32 version to a common arch/mips/lib/cache_init.S & remove the now-redundant mips64 version in order to reduce duplication. The temporary registers used are shuffled slightly in order to work for both mips32 & mips64 builds. The RA register is defined differently to suit mips32 & mips64, but will be removed by a later commit in the series after further cleanup. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | MIPS: unify cache maintenance functionsPaul Burton2015-01-29-167/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the more developed mips32 version of the cache maintenance functions to a common arch/mips/lib/cache.c, in order to reduce duplication between mips32 & mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
generated by cgit v1.1 at 2024-08-23 00:33:24 +0000