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* mmc: fsl_esdhc: Add support for DDR modeVolodymyr Riazantsev2015-02-24-2/+9
| | | | | | | | Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only. Signed-off-by: Volodymyr Riazantsev <volodymyr.riazantsev@globallogic.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls1021x: Add support for initializing CAAM's stream idAlison Wang2015-02-24-0/+115
| | | | | | | | | There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id for using the same SMMU3 on LS1021A. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls102xa: workaround for cache coherency problemchenhui zhao2015-02-24-0/+28
| | | | | | | | | | The RCPM FSM may not be reset after power-on, for example, in the cases of cold boot and wakeup from deep sleep. It causes cache coherency problem and may block deep sleep. Therefore, reset them if they are not be reset. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/pci: add Layerscape PCIe driverMinghuan Lian2015-02-24-5/+466
| | | | | | | | The patch adds Freescale Layerscape PCIe driver and provides up to 4 controllers support. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm/ls1021a: add PCIe settingsMinghuan Lian2015-02-24-0/+48
| | | | | | | | The patch enables and adds PCIe settings for boards LS1021AQDS and LS1021ATWR. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm/ls102xa: use a array to define pexmscportsrMinghuan Lian2015-02-24-2/+1
| | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm/ls102xa: create TLB to map PCIe regionMinghuan Lian2015-02-24-10/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins 0x48_00000000. In order to access PCIe device, we must create TLB to map the 40bit physical address to 32bit virtual address. This patch will enable MMU after DDR is available and creates MMU table in DRAM to map all 4G space; then, re-use the reserved space to map PCIe region. The following the mapping layout. VA mapping: ------- <---- 0GB | | | | |-------| <---- 0x24000000 |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000 |-------| <---- 0x300000000 | | |-------| <---- 0x34000000 |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000 |-------| <---- 0x40000000 | | |-------| <---- 0x80000000 DDR0 space start |\\\\\\\| |\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space |\\\\\\\| ------- <---- 4GB DDR0 space end Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls102xa: Define default values for some CCSR macrosAlison Wang2015-02-24-0/+37
| | | | | | | | This patch is to define default values for some CCSR macros to make header files cleaner. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers/mc: Migrated MC Flibs to 0.5.2J. German Rivera2015-02-24-52/+592
| | | | | | | | | | | Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree from "fsl,dprcr" to "fsl-mc". Print MC version info when appropriate. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls2085a_emu: Enable sync of refreshYork Sun2015-02-24-0/+1
| | | | | | | Enable sync of DDR refresh for LS2085a platform. GPP DDR controllers stay in sync. DP-DDR has only one controller so it does no harm. Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Enable erratum workround for A008514York Sun2015-02-24-0/+1
| | | | | | Erratum A008514 appleis to ls2085a. Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Enable workaround for A008336York Sun2015-02-24-0/+4
| | | | | | Erratum A008336 applied to LS2085A. Signed-off-by: York Sun <yorksun@freescale.com>
* ls2085/configs: Ensure right banners are printed for EMU and SIMUBhupesh Sharma2015-02-24-3/+6
| | | | | | | | This patch enusres that right banners are printed for LS2085A emulator and simulator platforms. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ARMv8/ls2085a: Move kernel image load addressStuart Yoder2015-02-24-1/+1
| | | | | | | | Move the load address of the kernel image to get it away from the region of the uncompressed kernel. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ARMv8/ls2085a: Switch to passing earlycon to kernelArnab Basu2015-02-24-4/+4
| | | | | | | | Since Linux v3.16-rc1 earlyprintk has been removed for arm64. Switch to using earlycon. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add sync of refreshYork Sun2015-02-24-0/+64
| | | | | | | Add sync of refresh for multiple DDR controllers. DDRC initialization needs to complete first. Code is re-ordered to keep refresh close. Signed-off-by: York Sun <yorksun@freescale.com>
* ARMv8/LS2085A: Adjust system clock and DDR clockYork Sun2015-02-24-1/+2
| | | | | | Set system clock to 100MHz and DDR clock to 133MHz. Signed-off-by: York Sun <yorksun@freescale.com>
* ARMv8/LS2085A: HugeTLB support is required by default in LS NADKKuldip Giroh2015-02-24-1/+3
| | | | | | | | | | LS NADK memory manager by default works on HugeTLB. Hence bootargs must include parameters default_hugepagesz (default hugepagesize, hugepagesz (hugepage size) and hugepages (number of hugepages to be reserved in kernel for the given size). Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Fix a typo in timing_cfg_8 calculationYork Sun2015-02-24-1/+1
| | | | | | wwt_bg should match rrt_bg. It was a typo in driver. Signed-off-by: York Sun <yorksun@freescale.com>
* ARMv8/LS2085A: Enable auto precharge for DP-DDRYork Sun2015-02-24-0/+1
| | | | | | | DP-DDR benefits from auto precharge because of its specific application. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add support for multiple DDR clocksYork Sun2015-02-24-159/+190
| | | | | | | | | Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Add support for second DDR clockYork Sun2015-02-24-2/+21
| | | | | | | | FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for general DDR controlers, and another clock for DP-DDR. DDR driver needs to change to support multiple clocks. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add workround for erratumn A008514York Sun2015-02-24-5/+17
| | | | | | | Erratum A008514 workround requires writing register eddrtqcr1 with value 0x63b20002. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add workaround for A008336York Sun2015-02-24-0/+27
| | | | | | | Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space for 64-bit DDR controllers. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Adjust CAS to preamble override for emulatorYork Sun2015-02-24-1/+5
| | | | | | | | | On ZeBu emulator, CAS to preamble overrides need to be set to satisfy the timing. This only impact platforms with CONFIG_EMU. These should be set before MEM_EN is set. Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Add fdt-fixup for clock frequency of the DUART nodesBhupesh Sharma2015-02-24-0/+5
| | | | | | | | This patch adds the fdt-fixup logic for the clock frequency of the NS16550A related device tree nodes. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls2085a: Enable cluster timebase for all clustersYork Sun2015-02-24-2/+9
| | | | | | | LS2085A and its variants can have up to four clusters. It is safe to enable timebase for all even some may be disabled. Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stackYork Sun2015-02-24-61/+97
| | | | | | | | | | | | Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com>
* ARMv8/fsl-lsch3: Patch cpu node properties in DT for online coresArnab Basu2015-02-24-9/+23
| | | | | | | | U-Boot should only add "enable-method" and "cpu-release-address" properties to the "cpu" node of the online cores. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Change normal memory shareabilityYork Sun2015-02-24-4/+5
| | | | | | | According to hardware implementation, a single outer shareable global coherence group is defined. Inner shareable has not bee enabled. Signed-off-by: York Sun <yorksun@freescale.com>
* fsl-ch3/lowlevel: TZPC and TZASC programming to configure non-secure accessesBhupesh Sharma2015-02-24-0/+108
| | | | | | | | | | | | | This patch ensures that the TZPC (BP147) and TZASC-400 programming happens for LS2085A SoC only when the desired config flags are enabled and ensures that the TZPC programming is done to allow Non-secure (NS) + secure (S) transactions only for DCGF registers. The TZASC component is not present on LS2085A-Rev1, so the TZASC-400 config flag is turned OFF for now. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2015-02-23-36/+114
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| * mmc: sdhci: fix bus width switching on Samsung SoCsMatt Reimer2015-02-23-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fix bus width switching from 8-bit mode down to 4-bit or 1-bit modes on Samsung SoCs using SDHCI_QUIRK_USE_WIDE8. These SoCs report controller version 2.0 yet they support 8-bit bus widths. If 8-bit mode was previously enabled and then an operation like "mmc dev" caused a switch back down to 4-bit or 1-bit mode, WIDE8 was left set, causing failures. This problem was manifested by "mmc dev" timing out. Signed-off-by: Matt Reimer <mreimer@sdgsystems.com>
| * mmc: print SD/eMMC type for inited mmc devicesPrzemyslaw Marczak2015-02-23-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Depending on the boot priority, the eMMC/SD cards, can be initialized with the same numbers for each boot. To be sure which mmc device is SD and which is eMMC, this info is printed by 'mmc list' command, when the init is done. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
| * mmc: exynos dwmmc: check boot mode before init dwmmcPrzemyslaw Marczak2015-02-23-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, the mmc devices were always registered in the same order. So dwmmc channel 0 was registered as mmc 0, channel 1 as mmc 1, etc. In case of possibility to boot from more then one device, the CONFIG_SYS_MMC_ENV_DEV should always point to right mmc device. This can be achieved by init boot device as first, so it will be always registered as mmc 0. Thanks to this, the 'saveenv' command will work fine for all mmc boot devices. Exynos based boards usually uses mmc host channels configuration: - 0, or 0+1 for 8 bit - as a default boot device (usually eMMC) - 2 for 4bit - as an optional boot device (usually SD card slot) And usually the boot order is defined by OM pin configuration, which can be changed in a few ways, eg. - Odroid U3 - eMMC card insertion -> first boot from eMMC - Odroid X2/XU3 - boot priority jumper By this commit, Exynos dwmmc driver will check the OM pin configuration, and then try to init the boot device and register it as mmc 0. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Simon Glass <sjg@chromium.org> Cc: Akshay Saraswat <akshay.s@samsung.com>
| * sunxi: mmc: Always declare High Capacity capabilityHans de Goede2015-02-23-5/+1
| | | | | | | | | | | | | | | | | | High Capacity (e)MMC cards work fine on sun4i / sun5i, and not having this capability set causes u-boot to not recognize the eMMC on an Utoo P66 A13 tablet, so always set it thereby fixing this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * mmc: exynos_dw_mmc: use the exynos specific data structureJaehoon Chung2015-02-23-14/+48
| | | | | | | | | | | | | | | | Clksel value is exynos specific value. It removed "clksel_val" into dwmci_host and created the "dwmci_exynos_priv_data" structure for exynos specific data. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: exynos_dw_mmc: set to clksel_val into board-init functionJaehoon Chung2015-02-23-0/+4
| | | | | | | | | | | | | | | | | | "clksel_val" is assigned to property of mmc or defined value. But it doesn't write at initial sequence. There is a reason that get the wrong source-clock value. This patch fixed it. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: dw_mmc: fixed the wrong bit controlJaehoon Chung2015-02-23-1/+1
| | | | | | | | | | | | If mode is not DDR-mode, then it needs to clear it. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: Implement SD/MMC versioning properlyPantelis Antoniou2015-02-23-21/+43
| | | | | | | | | | | | | | | | | | | | | | The SD/MMC version scheme was buggy when dealing with standard major.minor.change cases. Fix it by using something similar to the linux's kernel versioning method. Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Reported-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* | Merge git://git.denx.de/u-boot-sunxiTom Rini2015-02-21-12/+192
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| * sunxi: Machine id hack to prevent loading buggy sunxi-3.4 kernelsSiarhei Siamashka2015-02-21-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Right now U-Boot supports the CONFIG_OLD_SUNXI_KERNEL_COMPAT option, which makes it go out of its way in limiting the selection of PLL clock frequencies and PMIC voltages in order not to upset outdated buggy sunxi-3.4 kernel releases. And if the CONFIG_OLD_SUNXI_KERNEL_COMPAT option is not set, then booting such old kernels exhibits various failures at runtime. This is very user unfriendly, and there were already several incidents when people wasted their time being hit by these runtime failures and trying to debug them. The right solution is not to add hacks and workarounds to the mainline U-Boot, but to fix these bugs in the sunxi-3.4 kernel. And in fact, the updated sunxi-3.4 kernels already exist. Still we need to follow the 'Principle of Least Surprise' and U-Boot needs to ensure that the old buggy kernels are not getting happily booted when the CONFIG_OLD_SUNXI_KERNEL_COMPAT option is not set. And this patch addresses this particular issue. This patch makes U-Boot store the 'compatibility revision' number in the top 4 bits of the machine id and pass it to the kernel. The old buggy kernels will fail to load with a very much googlable error message on the serial console (the "r1 = 0x100010bb" part of it): "Error: unrecognized/unsupported machine ID (r1 = 0x100010bb)" This error message can be documented in the linux-sunxi wiki with proper explanations about how to resolve this situation and where to get the necessary bugfixes for the sunxi-3.4 kernel. The fixed sunxi-3.4 kernels implement a revision compatibility check and clear the top 4 bits of the machine id if everything is alright. By accepting the machine id with the bits 31:28 set to 1, the sunxi-3.4 kernel effectively certifies that it has the PLL5 clock speed and AXP209 DCDC3 voltage fixes applied. It is still possible to set the CONFIG_OLD_SUNXI_KERNEL_COMPAT option in U-Boot if the user desires to use an outdated unpatched sunxi-3.4 kernel. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Set the /chosen/stdout-path fdt property for sunxi boardsHans de Goede2015-02-21-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While discussing with some people how to get the Linux kernel to do the right thing wrt sending output to both the serial console and the hdmi out / lcd screen when booting on ARM devices, Grant Likely pointed out that there already is a solution for this. All we need to do is set the /chosen/stdout-path fdt property, and if no console= arguments were specified on the kernel commandline the kernel will honor this and add this device as a console (next to the primary video output on hdmi). And u-boot already has support for setting this, all we need to do is define OF_STDOUT_PATH and then everything will just work ootb, without people needing to meddle with adding console= arguments in extlinux.conf . Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Tom Rini <trini@ti.com>
| * sunxi: Fix sun5i mbus speed when booting old kernelsHans de Goede2015-02-21-0/+9
| | | | | | | | | | | | | | | | | | Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz, halving the mbus frequency, so set it to 300 MHz ourselves and base the mbus divider on that. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: musb: Check Vbus-det before enabling otg port powerHans de Goede2015-02-21-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | Sending out 5V when there is a charger connected to the otg port is not a good idea, so check for this and error out. Note this commit currently breaks otg support on the q8h tablets, as we need to do some magic with the pmic there to get vbus info, this is deliberate (better safe then sorry), fixing this is on my TODO list. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add support for the UTOO P66 tabletHans de Goede2015-02-21-0/+21
| | | | | | | | | | | | | | | | The UTOO P66 is a 6" A13 tablet / lcd ereader. It features a 6" 480x800 ips lcd screen, 512MB RAM & 4GB emmc. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: mmc: Always declare High Capacity capabilityHans de Goede2015-02-21-5/+1
| | | | | | | | | | | | | | | | | | High Capacity (e)MMC cards work fine on sun4i / sun5i, and not having this capability set causes u-boot to not recognize the eMMC on an Utoo P66 A13 tablet, so always set it thereby fixing this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: video: Add support for tl059wv5c0 lcd panelsHans de Goede2015-02-20-0/+15
| | | | | | | | | | | | | | | | Add support for the 6" 480x800 tl059wv5c0 panel used on e.g. Utoo P66 and Aigo M60/M608/M606 tablets. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: video: Add support for LCD panels which need to be configured via i2cHans de Goede2015-02-20-0/+50
| | | | | | | | | | | | | | | | This commits adds support for configuring a a bitbang i2c controller, which is used on some boards to configure the LCD panel (via i2c). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: video: Add support for LCD reset pinHans de Goede2015-02-20-1/+18
| | | | | | | | | | | | | | On some boards there is a gpio to reset the LCD panel, add support for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
generated by cgit v1.1 at 2024-11-07 20:18:19 +0000