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* x86: config: Enable hook for saving MRC configurationSimon Glass2015-01-24-0/+6
| | | | | | | Add a hook to ensure that this information is saved. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Implement a cache for Memory Reference Code parametersSimon Glass2015-01-24-0/+464
| | | | | | | | | | | The memory reference code takes a very long time to 'train' its SDRAM interface, around half a second. To avoid this delay on every boot we can store the parameters from the last training sessions to speed up the next. Add an implementation of this, storing the training data in CMOS RAM and SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: dts: Add SPI flash MRC details for chromebook_linkSimon Glass2015-01-24-1/+14
| | | | | | | | Correct the SPI flash compatible string, add an alias and specify the position of the MRC cache, used to store SDRAM training settings for the Memory Reference Code. Signed-off-by: Simon Glass <sjg@chromium.org>
* Allow architecture-specific memory reservationSimon Glass2015-01-24-0/+7
| | | | | | | All memory to be reserved for use after relocation by adding a new call to perform this reservation. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: spi: Add device tree supportSimon Glass2015-01-24-0/+8
| | | | | | | As a temporary measure before the ICH driver moves over to driver model, add device tree support to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: rtc: mc146818: Add helpers to read/write CMOS RAMSimon Glass2015-01-24-48/+105
| | | | | | | On x86 we use CMOS RAM to read and write some settings. Add basic support for this, including access to registers 128-255. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Use ipchecksum from net/Simon Glass2015-01-24-97/+4
| | | | | | | The existing IP checksum function is only accessible to the 'coreboot' cpu. Drop it in favour of the new code in the network subsystem. Signed-off-by: Simon Glass <sjg@chromium.org>
* net: Add a separate file for IP checksummingSimon Glass2015-01-23-0/+91
| | | | | | | | Move the checksum code out into its own file so it can be used elsewhere. Also use a new version which supports a length which is not a multiple of 2 and add a new function to add two checksums. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: dts: Add compatible string for Intel ICH9 SPI controllerSimon Glass2015-01-23-0/+2
| | | | | | | Add this to the enum so that we can use the various fdtdec functions. A later commit will move this driver to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* pci: tegra: Fix port information parsingSjoerd Simons2015-01-23-3/+2
| | | | | | | | | | | | | commit a62e84d7b1824a202dd incorrectly changed the tegra pci code to the new fdtdec pci helpers. To get the device index of the root port, the "reg" property should be parsed from the dtb (as was previously the case). With this patch i can successfully network boot my jetson tk1 Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
* x86: Fix various code format issues in start16.SBin Meng2015-01-23-10/+10
| | | | | | | | | | | Various minor code format issues are fixed in start16.S: - U-boot -> U-Boot - 32bit -> 32-bit - Use TAB instead of SPACE to indent - Move the indention location of the GDT comment block Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Test mtrr support flag before accessing mtrr msrBin Meng2015-01-23-2/+19
| | | | | | | | | | On some x86 processors (like Intel Quark) the MTRR registers are not supported. This is reflected by the CPUID (EAX 01H) result EDX[12]. Accessing the MTRR registers on such processors will cause #GP so we must test the support flag before accessing MTRR MSRs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Save mtrr support flag in global dataBin Meng2015-01-23-6/+14
| | | | | | | | CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this flag in x86_cpu_init_f() and save it in global data. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add missing DECLARE_GLOBAL_DATA_PTR for mtrr.cBin Meng2015-01-23-0/+2
| | | | | | | | arch/x86/cpu/mtrr.c has access to the U-Boot global data thus DECLARE_GLOBAL_DATA_PTR is needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: config: Always scroll the display by 5 lines, for speedSimon Glass2015-01-23-0/+1
| | | | | | | | Scrolling a line at a time is very slow for reasons that I don't understand. It seems to take about 100ms to copy 4MB of RAM in the frame buffer. To cope with this, scroll 5 lines each time. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: video: Add support for CONFIG_CONSOLE_SCROLL_LINESSimon Glass2015-01-23-9/+17
| | | | | | | | | | | | | Some machines are very slow to scroll their displays. To cope with this, support the CONFIG_CONSOLE_SCROLL_LINES option. Setting this to 5 allows the display to operate at an acceptable speed by scrolling 5 lines at a time. This same option is available for LCDs so when these systems are unified this code can be unified also. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* x86: Access the VGA ROM when neededSimon Glass2015-01-23-2/+42
| | | | | | | Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fix out of bounds irq handlers accessSebastien Ronsse2015-01-23-1/+1
| | | | | | | | | | | | | | | | | | | | | Using coreboot-x86_defconfig, the following error occurred prior to this modification: CC arch/x86/lib/interrupts arch/x86/lib/interrupts.c: In function ‘do_irqinfo’: arch/x86/lib/interrupts.c:134:24: error: iteration 16u invokes undefined behavior [-Werror=aggressive-loop-optimizations] if (irq_handlers[irq].handler != NULL) { ^ arch/x86/lib/interrupts.c:133:2: note: containing loop for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) { ^ cc1: all warnings being treated as errors scripts/Makefile.build:275: recipe for target 'arch/x86/lib/interrupts.o' failed make[1]: *** [arch/x86/lib/interrupts.o] Error 1 Makefile:1093: recipe for target 'arch/x86/lib' failed make: *** [arch/x86/lib] Error 2 Change-Id: I3572a822081b72ab760f1eb99442e1161d3d167e Signed-off-by: Sebastien Ronsse <sronsse@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ahci: Make sure interface is not busy after enabling the portBin Meng2015-01-23-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each time U-Boot boots on Intel Crown Bay board, the displayed hard drive information is wrong. It could be either wrong capacity or just a 'Capacity: not available' message. After enabling the debug switch, we can see the scsi inquiry command did not execute successfully. However, doing a 'scsi scan' in the U-Boot shell does not expose this issue. SCSI: Target spinup took 0 ms. SATA link 1 timeout. AHCI 0001.0100 32 slots 2 ports 3 Gbps 0x3 impl SATA mode flags: ncq stag pm led clo only pmp pio slum part ccc apst scanning bus for devices... ahci_device_data_io: 0 byte transferred. <--- scsi inquiry fails ahci_device_data_io: 512 byte transferred. ahci_device_data_io: 512 byte transferred. ahci_device_data_io: 512 byte transferred. Device 0: (0:0) Vendor: ATA Prod.: Rev: ?8 Type: Hard Disk Capacity: 912968.3 MB = 891.5 GB (1869759264 x 512) Found 1 device(s). So uninitialized contents on the stack were passed to dev_print() to display those wrong information. The symptom were observed on two hard drives (one is Seagate, the other one is Western Digital). The fix is to make sure the AHCI interface is not busy by checking the error and status information from task file register after enabling the port in ahci_port_start() before proceeding other operations like scsi_scan(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Drop the x86_fb driverSimon Glass2015-01-23-49/+1
| | | | | | | | Now that we have a full VESA driver we may as well use that. We need to support the VESA layer being set up by early start-up code or by running a VGA ROM. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a VESA video driverSimon Glass2015-01-23-0/+75
| | | | | | | | | Add a driver intended to cope with any VESA-compatible x86 graphics adapter. It will not support ROMs which use OpenFirmware (Forth) since there is no support for that in U-Boot. This means that MAC OS cards will not work. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: pci: Don't stop when we get a vendor/device mismatchSimon Glass2015-01-23-1/+1
| | | | | | | These are quite common and we may as well press on and not be so picky. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* bios_emulator: Add some VESA interface debuggingSimon Glass2015-01-23-22/+148
| | | | | | Allow the supported modes to be listed when in debug mode. Signed-off-by: Simon Glass <sjg@chromium.org>
* bios_emulator: Don't display error when emulator terminatesSimon Glass2015-01-23-1/+1
| | | | | | As it turns out this is a normal condition, so suppress the error. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Support ROMs on other archsSimon Glass2015-01-23-1/+8
| | | | | | | | We shouldn't assume that the VGA ROM can always be loaded at c0000. This is only true on x86 machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Correct endianness isues in pci_romSimon Glass2015-01-23-11/+14
| | | | | | | | This code is too x86-dependent at present. Correct it so that it can run on big-endian machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* bios_emulator: Fix an #ifdef typo in the header fileSimon Glass2015-01-23-1/+1
| | | | | | | This stops the debug mode from working properly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200Masahiro Yamada2015-01-23-4752/+5
| | | | | | | | These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* powerpc: mpc5xxx: PM520 board supportMasahiro Yamada2015-01-23-1329/+1
| | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Josef Wagner <Wagner@Microsys.de>
* powerpc: mpc5xxx: remove Total5200 board supportMasahiro Yamada2015-01-23-931/+1
| | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boardsMasahiro Yamada2015-01-23-2175/+2
| | | | | | | | | | | These boards are still non-generic boards. It is a good thing that we can drop board-specific hack code from drivers/mtd/nand/nand_base.c Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
* powerpc: mpc85xx: remove P2020DS board supportMasahiro Yamada2015-01-23-1310/+1
| | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc85xx: remove P2020COME board supportMasahiro Yamada2015-01-23-998/+1
| | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Ira W. Snyder <iws@ovro.caltech.edu>
* powerpc: mpc85xx: remove P1_P2_RDB boardsMasahiro Yamada2015-01-23-2058/+4
| | | | | | | | These boards are still non-generic boards: P1011RDB, P1022RDB, P2010RDB, P2020RDB Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
* powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS supportMasahiro Yamada2015-01-23-2674/+8
| | | | | | | | These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Dave Liu <daveliu@freescale.com> Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-01-23-700/+2073
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| * sunxi: Use a common CONFIG_SYS_PROMPTIan Campbell2015-01-23-7/+2
| | | | | | | | | | | | | | | | | | | | | | The CPU info is already logged during boot e.g. CPU: Allwinner A20 (SUN7I) so the prompt is just one more thing to change for each new SoC, just makes it "sunxi#" instead. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add Hyundai A7HD supportHans de Goede2015-01-23-0/+23
| | | | | | | | | | | | | | | | | | | | The Hyundai A7HD is a 7" 16:9 A10 powered tablet featuring 1G RAM, 8G nand, 1024x600 IPS screen, a mini hdmi port, mini usb receptacle and a headphones port for details see: http://linux-sunxi.org/Hyundai_A7HD Cc: Mark Janssen <maniac@maniac.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: video: Make pwm polarity configurableHans de Goede2015-01-23-6/+18
| | | | | | | | | | | | | | | | It turns out that there are some panels where the pwm input is not active low, so make it configurable. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add support for Mele M5.Ian Campbell2015-01-23-0/+18
| | | | | | | | | | | | | | | | | | HDMI, SATA, USB and Ethernet appear functional, I've not done extensive tests of all peripherals though. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Convert sun7i boards to use auto dram configurationHans de Goede2015-01-23-197/+34
| | | | | | | | | | | | | | | | | | | | | | | | Currently we've separate detailed dram settings for all sun7i boards, this moves them over to using auto dram configuration so that we can get rid of all the per board dram_foo.c files. This has been tested on a A20-Olinuxino-Lime, A20-Olinuxino_MICRO, Bananapi, Bananapro, Cubieboard2, Cubietruck, Mele_M3 and a Linksprite_pcDuino3. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Drop qt840a_defconfigHans de Goede2015-01-23-45/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The qt840a is one of the many tv-boxes using the "i12" A20 pcb, but it populates only one of the 2 places for a 16 bit dram ic, thus reducing the buswidth to 16 bits, and the amount of ram to 512M, which is why we had a separate config for it. This commit switches the generic i12-tvbox_defconfig over to DRAM autoconfiguration, so that it will work with the qt840a too, and drops the qt840a specific config, like we've done with other memory-amount specific configs before. Tested on a generic i12-tvbox with 32 bit bus-width / 1G RAM, and on a qt840a with 16 bit bus-width / 512M RAM. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add new Chuwi V7 CW0825 board / defconfigHans de Goede2015-01-23-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | The Chuwi V7 is an A10 (sun4i) based tablet with 1G of RAM, 16G of nand flash, microsd slot, 7" 1024x768 lvds ips panel, mini hdmi out, headphones out, stereo speakers, front & back camera and usb wifi. It is clearly marked "CHUWI", "V7" and "Model: CW0825" on the back of the tablet. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: video: Add support for Hitachi tx18d42vm LVDS LCD panelsHans de Goede2015-01-23-0/+12
| | | | | | | | | | | | | | | | | | | | Add support for Hitachi tx18d42vm LVDS LCD panels, these panels have a lcd controller which needs to be initialized over SPI, once that is done they work like a regular LVDS panel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * video: Add support for Hitachi tx18d42vm LVDS LCD panelsHans de Goede2015-01-22-3/+103
| | | | | | | | | | | | | | | | | | Add support for Hitachi tx18d42vm LVDS LCD panels, these panels have a lcd controller which needs to be initialized over SPI, once that is done they work like a regular LVDS panel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
| * sunxi: Hookup OTG USB controller supportHans de Goede2015-01-22-3/+49
| | | | | | | | | | | | | | | | | | | | | | Hookup OTG USB controller support and enable the otg controller + USB-keyb on various tablets. This allows tablet owners to interact with u-boot without needing to solder a serial console onto their tablet PCB. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add Gemei G9 (Allwinner A10/sun4i) tabletPriit Laes2015-01-22-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Gemei G9 is an A10 based tablet, with 1G RAM, 16G NAND, 1024x768 IPS LCD display, stereo speakers, 1.3MP front camera and 5 MP rear camera, 8000mAh battery, GT901 2+1 touchscreen, Bosch BMA250 accelerometer and RTL8188CUS USB wifi. It also has MicroSD slot, miniHDMI, 1 x MicroUSB OTG port and 1 x MicroUSB host port and 3.5mm headphone jack. More details are available at: http://linux-sunxi.org/Gemei_G9 Signed-off-by: Priit Laes <plaes@plaes.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: video: Use frontend for dma on sun4i to fix memory bandwidth problemsHans de Goede2015-01-22-4/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Testing has shown that on sun4i the display backend engine does not have deep enough fifo-s causing flickering / tearing in full-hd mode due to fifo underruns. On sun4i use the display frontend engine to do the dma from memory, as the frontend does have deep enough fifo-s. As added advantage of this is that it results in much better memory bandwidth as it reduces the amount of dram bank switches, for more details see: http://ssvb.github.io/2014/11/11/revisiting-fullhd-x11-desktop-performance-of-the-allwinner-a10.html Note that this changes the pipeline searched for in the simplefb node, we can get away with doing this now, since no kernel has yet shipped with simplefb dtb nodes, and I will make sure to get a simplefb node with the new pipeline into 3.19 before it ships. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add Marsboard A10 supportAleksei Mamlin2015-01-22-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add support for Marsboard A10 board. The Marsboard A10 is a A10 based development board with 1G RAM, 1G NAND, micro SD card slot, SATA 2.0 socket, 10/100 ethernet, mini HDMI port, 1 USB OTG port and 2 USB 2.0 ports. Board does not use the AXP209 pmic, it does not have a pmic at all. Board also have 2 expansion 70 pin headers. Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * video: ssd2828: Allow using 'pclk' as the PLL clock sourceSiarhei Siamashka2015-01-22-7/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using the internal 'tx_clk' clock source, it is also possible to use the pixel clock signal from the parallel LCD interface ('pclk') as the reference clock for PLL. The 'tx_clk' clock speed may be different on different boards/devices (the allowed range is 8MHz - 30MHz). Which is not very convenient, especially considering the need to know the exact 'tx_clk' clock speed. This clock speed may be difficult to identify without having device schematics and/or accurate documentation/sources every time. Using 'pclk' is free from all these problems. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Anatolij Gustschin <agust@denx.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
generated by cgit v1.1 at 2024-08-25 14:11:12 +0000