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* OMAP3: pandora: revise GPIO configurationGrazvydas Ignotas2012-05-15-13/+41
| | | | | | | | | | | | Update pandora's GPIO setup code with these changes: - convert to gpiolib - set up dual voltage GPIOs to match supply of 1.8V by clearing VMODE1 - add GPIO_IO_PWRDNZ configuration for DM3730 variation of pandora (required to enable GPIO 126, 127, and 129 I/O cells in DM3730) - add wifi reset pulse as recommended by wifi chip's manufacturer - drop configuration of GPIOs that u-boot doesn't need Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
* OMAP3: pandora: pin mux updates for DM3730 board variantGrazvydas Ignotas2012-05-15-0/+15
| | | | | | | DM3730 needs some additional pin mux configuration for GPIOs 126-129 to work, add it. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
* Makefile: Add a 'checkthumb' ruleTom Rini2012-05-15-0/+12
| | | | | | | | | | | | This rule confirms that if we're on ARM and we have enabled THUMB builds that we have a new enough toolchain to produce a working binary. Changes in v2: - Switch to ALL-$(CONFIG_SYS_THUMB_BUILD) in arch/arm/config.mk (Mike F) - Simplfy checkthumb test after doing the above Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* tools, config.mk: Add gcc-version.sh, cc-version test from LinuxTom Rini2012-05-15-1/+37
| | | | | | Added from Linux - commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9 Signed-off-by: Tom Rini <trini@ti.com>
* OMAP4: enable Thumb buildAneesh V2012-05-15-0/+2
| | | | Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4+: Avoid using __attribute__ ((__packed__))Aneesh V2012-05-15-2/+2
| | | | | | | | | | | | | Avoid using __attribute__ ((__packed__)) unless it's absolutely necessary. "packed" will remove alignment requirements for the respective objects and may cause alignment issues unless alignment is also enforced using a pragma. Here, these packed attributes were causing alignment faults in Thumb build. Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: Use -march=armv7-a and thereby enable Thumb-2Aneesh V2012-05-15-2/+5
| | | | | | | | Enable -march=armv7-a for armv7 platforms if the tool-chain supports it. This in turn results in Thumb-2 code generated for these platforms if CONFIG_SYS_THUMB_BUILD is enabled. Signed-off-by: Aneesh V <aneesh@ti.com>
* ARM: enable Thumb buildAneesh V2012-05-15-7/+23
| | | | | | | | Enable Thumb build and ARM-Thumb interworking based on the new config flag CONFIG_SYS_THUMB_BUILD Signed-off-by: Aneesh V <aneesh@ti.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* armv7: add appropriate headers for assembly functionsAneesh V2012-05-15-49/+58
| | | | | | | | Use ENTRY and ENDPROC with assembly functions to ensure necessary assembler directives for all functions. Signed-off-by: Aneesh V <aneesh@ti.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* arm: adapt asm/linkage.h from LinuxAneesh V2012-05-15-1/+13
| | | | | | | | This will add ARM specific over-rides for the defines from linux/linkage.h Signed-off-by: Aneesh V <aneesh@ti.com> Tested-by: Mike Frysinger <vapier@gentoo.org>
* OMAP5: reset: Use cold reset in case of 5430ES1.0SRICHARAN R2012-05-15-0/+14
| | | | | | | | Warm reset is not functional in case of omap5430ES1.0. So override the weak reset_cpu function to use cold reset instead. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP3+: reset: Create a common reset layer.SRICHARAN R2012-05-15-41/+38
| | | | | | | | | The reset.S has the function to do a warm reset on OMAP based socs. Moving this to a reset.c file so that this acts a common layer to add any reset related functionality for the future. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* mmc: omap5evm: Add eMMC saveenv supportBalaji T K2012-05-15-0/+1
| | | | | | Save env to eMMC Signed-off-by: Balaji T K <balajitk@ti.com>
* omap5: pbias ldo9 turn onBalaji T K2012-05-15-3/+63
| | | | | | | Add omap5 pbias configuration for mmc1/sd lines and set voltage for sd data i/o lines Signed-off-by: Balaji T K <balajitk@ti.com>
* power: twl6035: add palmas PMIC supportSRICHARAN R2012-05-15-3/+90
| | | | | | palmas/TWL6035 is power IC for omap5 evm boards Signed-off-by: Balaji T K <balajitk@ti.com>
* arm: omap5: correct boot device mode7 for eMMCBalaji T K2012-05-15-1/+6
| | | | | | | In OMAP5 Boot device mode of 6 and 7 should be mapped to mmc2/eMMC Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* OMAP4/5: emif: Correct the emif power mgt shadow register bit fields.SRICHARAN R2012-05-15-2/+2
| | | | | | | | PD_TIM bit field which specifies the power down timing is defined to occupy bits 8-11, where as it is actually from 12-15 bits. So correcting this. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: ddr: Change the ddr device name.SRICHARAN R2012-05-15-16/+16
| | | | | | | The ddr part name used in OMAP5 ES1.0 soc is a SAMSUNG part and not a ELPIDA part. So change this. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: defconfig: Align the defconfig for 5430 ES1.0SRICHARAN R2012-05-15-15/+6
| | | | | | Adding the nessecary changes for OMAP5430 ES1.0 silicon. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP4/5: device: Add support to get the device type.SRICHARAN R2012-05-15-1/+13
| | | | | | Add support to identify the device as GP/EMU/HS. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP4/5: Make the sysctrl structure commonSRICHARAN R2012-05-15-16/+19
| | | | | | | | | Make the sysctrl structure common, so that it can be used in generic functions across socs. Also change the base address of the system control module, to include all the registers and not simply the io regs. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: SRAM: Change the SRAM base address.SRICHARAN R2012-05-15-1/+1
| | | | | | | The full internal SRAM of size 128kb is public in the case of OMAP5 soc. So change the base address accordingly. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP4/5: Make the silicon revision variable common.SRICHARAN R2012-05-15-25/+19
| | | | | | | | The different silicon revision variable names was defined for OMAP4 and OMAP5 socs. Making the variable common so that some code can be made generic. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: hwinit: Add the missing break statementSRICHARAN R2012-05-15-0/+1
| | | | | | | The break statement is missing in init_omap_revision function, resulting in a wrong revision identification. So fixing this. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: palmas: Configure nominal opp vdd valuesSRICHARAN R2012-05-15-23/+52
| | | | | | | | | | | The nominal opp vdd values as recommended for ES1.0 silicon is set for mpu, core, mm domains using palmas. Also used the right sequence to enable the vcores as per a previous patch from Nishant Menon, which can be dropped now. http://lists.denx.de/pipermail/u-boot/2012-March/119151.html Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon.SRICHARAN R2012-05-15-28/+188
| | | | | | | | | The OMAP5 silicon has new DDR PHY design, which includes a external PHY as well. So configuring the ext PHY parameters here. Also the EMIF timimg registers and a couple of DDR mode registers needs to be updated based on the testing from the actual silicon. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: io: Configure the io settings for omap5430 sevm board.SRICHARAN R2012-05-15-24/+187
| | | | | | | | | The control module provides options to set various signal integrity parameters like the output impedance, slew rate, load capacitance for different pad groups. Configure these as required for the omap5430 sevm board. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: board: Add pinmux data for omap5_evm board.SRICHARAN R2012-05-15-482/+509
| | | | | | Adding the full pinmux data for OMAP5430 sevm board. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: clocks: Change clock settings as required for ES1.0 silicon.SRICHARAN R2012-05-15-39/+94
| | | | | | | | Aligning all the clock related settings like the dpll frequencies, their respective clock outputs, etc to the ideal values recommended for OMAP5430 ES1.0 silicon. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP3: igep00x0: Reduce lines of code for IGEP-based boards.Enric Balletbò i Serra2012-05-15-273/+11
| | | | | | | | | | | | | | This is rework on config files of IGEP-based boards with the aim to remove duplicated code to be more maintainable. Basically this patch creates a common configuration file for both boards and only sets the specific option in the board config file. On board files the hardcored mach type was replaced in favour of using the CONFIG_MACH_TYPE option. More than 200 duplicated lines have been deleted. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
* OMAP4: scale voltage of core before MPU scalesNishanth Menon2012-05-15-28/+35
| | | | | | | | | | | | | | | | OMAP4 requires that parent domains scale ahead of dependent domains. This is due to the restrictions in timing closure. To ensure a consistent behavior across all OMAP4 SoC, ensure that vdd_core scale first, then vdd_mpu and finally vdd_iva. As part of doing this refactor the logic to allow for future addition of OMAP4470 without much ado. OMAP4470 uses different SMPS addresses and cannot be introduced in the current code without major rewrite. Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP4460: TPS Ensure SET1 is selected after voltage configurationNishanth Menon2012-05-15-7/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms. Currently we control this pin with a mux configuration as part of boot sequence. Current configuration results in the following voltage waveform: |---------------| (SET1 default 1.4V) | --------(programmed voltage) | <- (This switch happens on mux7,pullup) vdd_mpu(TPS) -----/ (OPP boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -----------------------/ (OPP boot voltage) Problem 1) |<----- Tx ------>| timing violation for a duration Tx close to few milliseconds. Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP. By using GPIO as recommended as standard procedure by TI, the sequence changes to: -------- (programmed voltage) vdd_mpu(TPS) ------------/ (Opp boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -------------/ (OPP boot voltage) NOTE: This does not attempt to address OMAP5 - Aneesh please confirm Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP3+: Introduce generic logic for OMAP voltage controllerNishanth Menon2012-05-15-75/+150
| | | | | | | | | | | | | | | | | | | | OMAP Voltage controller is used to generically talk to PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code in multiple SoC code, introduce a common voltage controller logic which can be re-used from elsewhere. With this change, we replace setup_sri2c with omap_vc_init which has the same functionality, and replace the voltage scale replication in do_scale_vcore and do_scale_tps62361 with omap_vc_bypass_send_value. omap_vc_bypass_send_value can also now be used with any configuration of PMIC. NOTE: Voltage controller controlling I2C_SR is a write-only data path, so no register read operation can be implemented. Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM:OMAP+:MMC: Add parameters to MMC initJonathan Solnit2012-05-15-38/+58
| | | | | | | | | | Add parameters to the OMAP MMC initialization function so the board can mask host capabilities and set the maximum clock frequency. While the OMAP supports a certain set of MMC host capabilities, individual boards may be more restricted and the OMAP may need to be configured to match the board. The PRG_SDMMC1_SPEEDCTRL bit in the OMAP3 is an example. Signed-off-by: Jonathan Solnit <jsolnit@gmail.com>
* kirkwood: add support for Cloud Engines Pogoplug E02David Purdy2012-05-15-0/+498
| | | | | | | | | | | This patch adds support for Cloud Engines Pogoplug E02 Information regarding the CE Pogoplug E02 board can be found at: http://archlinuxarm.org/platforms/armv5/pogoplug-v2-pinkgray Signed-off-by: Dave Purdy <david.c.purdy@gmail.com> Cc: prafulla@marvell.com Cc: albert.u.boot@aribaud.net
* kirkwood: add NAS62x0 board supportLuka Perkov2012-05-15-0/+488
| | | | | | | | | | | | | | | Add support for new boards RaidSonic ICY BOX NAS6210 and NAS6220. NAS6210 has 1 SATA and 1 eSATA port while NAS6220 has 2 SATA ports. More information about the boards can be found here: http://www.raidsonic.de/en/products/nas-systems.php?we_objectID=7036 http://www.raidsonic.de/en/products/nas-systems.php?we_objectID=7515 Signed-off-by: Luka Perkov <uboot@lukaperkov.net> Signed-off-by: Gerald Kerma <dreagle@doukki.net> Signed-off-by: Simon Baatz <gmbnomis@gmail.com>
* devkit3250: add Timll DevKit3250 board initial supportVladimir Zapolskiy2012-05-15-0/+231
| | | | | | | | | | | This change adds a basic support for Embest/Timll DevKit3250 board, NOR and UART are the only supported peripherals for a moment. The board doesn't require low-level init, because the initial SDRAM and GPIO configuration is performed during kickstart bootloader execution. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* serial: add LPC32X0 high-speed UART devices supportVladimir Zapolskiy2012-05-15-0/+173
| | | | | | | | | This change adds an implementation of high-speed UART found on NXP LPC32X0 SoCs. Such UARTs are enumerated as UART1, UART2 and UART7. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* arm926ejs: add NXP LPC32x0 cpu series supportVladimir Zapolskiy2012-05-15-0/+985
| | | | | | | | This change adds initial support for NXP LPC32x0 SoC series. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* ARM: dreamplug: Enable FDT supportIan Campbell2012-05-15-0/+2
| | | | | | | | | | | I have tested booting both FDT and non-FDT based Linux kernels (based on http://marc.info/?l=linux-arm-kernel&m=133002679716986 and http://marc.info/?l=linux-arm-kernel&m=132328894303581 respectively). Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Jason <jason@lakedaemon.net> Cc: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
* Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingWolfgang Denk2012-04-30-61/+52
|\ | | | | | | | | | | | | | | | | | | * 'agust@denx.de' of git://git.denx.de/u-boot-staging: lin_gadget: use common linux/compat.h linux/compat.h: rename from linux/mtd/compat.h lin_gadget: use common mdelay gunzip: rename z{alloc, free} to gz{alloc, free} fs/fat: align disk buffers on cache line to enable DMA and cache part_dos: align disk buffers on cache line to enable DMA and cache
| * lin_gadget: use common linux/compat.hMike Frysinger2012-04-30-16/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge our duplicate definitions with the common header. Also fix drivers/usb/gadget/s3c_udc_otg_xfer_dma.c to use min() instead of min_t() since we remove the latter from compat.h. Additionally use memalign() directly as the lin_gadget specific kmalloc() macro is removed from lin_gadget_compat.h by this patch. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Lukasz Majewski <l.majewski@samsung.com>
| * linux/compat.h: rename from linux/mtd/compat.hMike Frysinger2012-04-30-19/+19
| | | | | | | | | | | | This lets us use it in more places than just mtd code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * lin_gadget: use common mdelayMike Frysinger2012-04-30-1/+0
| | | | | | | | | | | | No need to provide our own mdelay() macro when we have a func for it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * gunzip: rename z{alloc, free} to gz{alloc, free}Mike Frysinger2012-04-30-12/+9
| | | | | | | | | | | | | | This allows us to add a proper zalloc() func (one that does a zeroing alloc), and removes duplicate prototypes. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * fs/fat: align disk buffers on cache line to enable DMA and cacheEric Nelson2012-04-30-10/+12
| | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
| * part_dos: align disk buffers on cache line to enable DMA and cacheEric Nelson2012-04-30-3/+3
| | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2012-04-30-301/+507
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of /home/wd/git/u-boot/custodians: powerpc/ppc4xx: Remove typedefs for gdsys FPGA powerpc/ppc4xx: Fix typo in gdsys_fpga.h powerpc/ppc4xx: Update gdsys board configurations powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20 powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes powerpc/ppc4xx: Make gdsys 405ep boards reset more generic powerpc/ppc4xx: Adjust environment size on neo
| * \ Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2012-04-30-301/+507
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-ppc4xx: powerpc/ppc4xx: Remove typedefs for gdsys FPGA powerpc/ppc4xx: Fix typo in gdsys_fpga.h powerpc/ppc4xx: Update gdsys board configurations powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20 powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes powerpc/ppc4xx: Make gdsys 405ep boards reset more generic powerpc/ppc4xx: Adjust environment size on neo
| | * | powerpc/ppc4xx: Remove typedefs for gdsys FPGADirk Eibach2012-04-30-40/+42
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
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