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* powerpc/mpc85xx: add support for MMUv2 page sizesScott Wood2013-01-30-24/+49
| | | | | | | | e6500 implements MMUv2 and supports power-of-2 page sizes rather than power-of-4. Add support for such pages. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: Add BSC9132QDS supportPrabhakar Kushwaha2013-01-30-0/+1618
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BSC9132QDS is a Freescale reference design board for BSC9132 SoC. BSC9132 SOC is an integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. BSC9132QDS Overview -------------------- 2Gbyte DDR3 (on board DDR), Dual Ranki 32Mbyte 16bit NOR flash 128Mbyte 2K page size NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory SD slot USB-ULPI eTSEC1: Connected to SGMII PHY eTSEC2: Connected to SGMII PHY PCIe CPRI SerDes I2C RTC DUART interface: supports one UARTs up to 115200 bps for console display Apart from the above it also consists various peripherals to support DSP functionalities. This patch adds support for mainly Power side functionalities and peripherals Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Add BSC9132/BSC9232 processor supportPrabhakar Kushwaha2013-01-30-2/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8xxxx: FSL DDR debugger auto run of stored commandsJames Yang2013-01-30-11/+47
| | | | | | | | | | | This patch adds the ability for the FSL DDR interactive debugger to automatically run the sequence of commands stored in the ddr_interactive environment variable. Commands are separated using ';'. ddr_interactive=compute; edit c0 d0 dimmparms caslat_X 0x3FC0; go Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* README.fsl-ddr typos and update to reflect hotkeyJames Yang2013-01-30-14/+21
| | | | | | | | Documentation fix to README.fsl-ddr to fix typos and to reflect use of 'd' hotkey to enter the FSL DDR debugger. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Add copy command to FSL DDR interactiveJames Yang2013-01-30-0/+132
| | | | | | | | | Add copy command which allows copying of DIMM/controller settings. This saves tedious retyping of parameters for each identical DIMM or controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Fix data stage name matching issueJames Yang2013-01-30-1/+2
| | | | | | | | | | This fix allows the name of the stage to be specifed after the controler and DIMM is specified. Prior to this fix, if the data stage name is not the first entry on the command line, the operation is applied to all controller and DIMMs. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Move DDR command parsing to separate functionJames Yang2013-01-30-79/+74
| | | | | | | | Move the FSL DDR prompt command parsing to a separate function so that it can be reused. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8xxx: Enable entering DDR debugging by key pressYork Sun2013-01-30-2/+11
| | | | | | | | | | | | | | | Using environmental variable "ddr_interactive" to activate interactive DDR debugging seomtiems is not enough. For example, after updating SPD with a valid but wrong image, u-boot won't come up due to wrong DDR configuration. By enabling key press method, we can enter debug mode to have a chance to boot without using other tools to recover the board. CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the debug mode by key press, press key 'd' shortly after reset, like one would do to abort auto booting. It is fixed to lower case 'd' at this moment. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p2041: set RCW and PBI files for .pbl build or P2041RDBValentin Longchamp2013-01-30-0/+2
| | | | | | | | | | | In order to be able to build a u-boot.pbl image, both the CONFIG_PBLPBI_CONFIG and CONFIG_PBLRCW_CONFIG variables have to be defined. This patch sets these two files for the P2041RDB board. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p2041: add RCW file for P2041RDBValentin Longchamp2013-01-30-0/+11
| | | | | | | | | | | | All the dev boards of Freescale's QorIQ family have a RCW that is supported by the u-boot.pbl build target. This patch adds one for the P2041 dev board. This RCW is suitable for the RAMBOOT_PBL scenarios and was tested on the P2041RDB booting from the eSPI NOR Flash (P2041RDB_SPIFLASH config). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/t4240qds: Print FPGA detail versionPrabhakar Kushwaha2013-01-30-2/+9
| | | | | | | | | | | Qixis FPGA has tag data contains image name and build date. It is helpful to identify the FPGA image precisely. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/t4240qds: Add support to dump switch settings on t4240qds boardShaveta Leekha2013-01-30-0/+60
| | | | | | | | | | This function is called by "qixis_reset switch" command and switch settings are calculated from qixis FPGA registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/b4860qds: Add support to dump switch settings on b4860qds boardShaveta Leekha2013-01-30-0/+47
| | | | | | | | | | This function is called by "qixis_reset switch" command and switch settings are calculated from FPGA/qixis registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/qixis: enable qixis dump command and add switch dumping commandShaveta Leekha2013-01-30-12/+36
| | | | | | | | | | | | | Remove #ifdef so that "qixis dump" command is always available Add "qixis_reset switch" command to dump switch settings Qixis doesn't have 1:1 switch mapping. We need to reverse engineer from registers to figure out switch settings. Not all bits are available. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/b4860qds: Added Support for B4860QDSYork Sun2013-01-30-0/+2536
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4860QDS is a high-performance computing evaluation, development and test platform supporting the B4860 QorIQ Power Architecture processor. B4860QDS Overview ------------------ - DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 4 GB of memory in two ranks of 2 GB. - DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB of memory. Single rank. - SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point 16x16 switch VSC3316 - SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point 8x8 switch VSC3308 - USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode. - B4860 UART port is available over USB-to-UART translator USB2SER or over RS232 flat cable. - A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA connector ports 0 and 2 for AMC mode. - The B4860 configuration may be loaded from nine bits coded reset configuration reset source. The RCW source is set by appropriate DIP-switches: - 16-bit NOR Flash / PROMJet - QIXIS 8-bit NOR Flash Emulator - 8-bit NAND Flash - 24-bit SPI Flash - Long address I2C EEPROM - Available debug interfaces are: - On-board eCWTAP controller with ETH and USB I/F - JTAG/COP 16-pin header for any external TAP controller - External JTAG source over AMC to support B2B configuration - 70-pin Aurora debug connector - QIXIS (FPGA) logic: - 2 KB internal memory space including - IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK, DDRCLK1, 2 and RTCCLK. - Two 8T49N222A SerDes ref clock devices support two SerDes port clocks - total four refclk, including CPRI clock scheme Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:Fix Core cluster configuration loopPrabhakar Kushwaha2013-01-30-8/+22
| | | | | | | | | | | | | | Different personalities/derivatives of SoC may have reduced cluster. But it is not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters". EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC which may not be valid for the personality. So add initiator type check to find valid cluster. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/freescale/common:Add support of QTAG registerPrabhakar Kushwaha2013-01-30-0/+49
| | | | | | | | | | | | | QIXIS FPGA's QIXIS Tag Access register (QTAG) defines TAG, VER, DATE, IMAGE fields. These fields have FPGA build version, image name and build date information. Add support to parse these fields to have complete FPGA image information. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:Add support of B4420 SoCPoonam Aggrwal2013-01-30-1/+77
| | | | | | | | | | | | | | | | | | | | | B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Few updates for B4860 cpu changesPoonam Aggrwal2013-01-30-1/+95
| | | | | | | | | | | | | | | - Added some more serdes1 and serdes2 combinations serdes1= 0x2c, 0x2d, 0x2e serdes2= 0x7a, 0x8d, 0x98 - Updated Number of DDR controllers to 2. - Added FMAN file for B4860, drivers/net/fm/b4860.c Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8544ds: Add USB controller support for MPC8544DSHongtao Jia2013-01-30-0/+12
| | | | | | | | | USB controller in uboot is a required feature for MPC8544DS. Without this support there is no 'usb' command in uboot. Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8572ds: Enable bank interleaving to cs0+cs1 for dual-rank DIMMsHongtao Jia2013-01-30-1/+1
| | | | | | | | | | | | The controller interleaving only takes the usable memory mapped to cs0. In the case of bank interleaving not enabled, only half of dual-rank DIMM will be used. For single-rank DIMM bank interleaving will be auto disabled. Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/t4240qds: Update IFC timing for NOR flashYork Sun2013-01-30-5/+5
| | | | | | | | Relax parameters to give address latching more time to setup. Tighten parameters to make it overall faster. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* boards/T4240qds:Fix IFC AMASK init as per FPGA register spacePrabhakar Kushwaha2013-01-30-1/+1
| | | | | | | | | | T4240QDS's QIXIS FPGA has 4k register space size and IFC controller's Address Mask Registers is initialised 64K size. So Fix the Address Mask Register initilisation as 4K Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/T4240qds:Fix TLB and LAW size of NAND flashPrabhakar Kushwaha2013-01-30-2/+2
| | | | | | | | | | The internal SRAM of Freescale's IFC NAND machine is of 64K and controller's Address Mask Registers is initialised with the same. So Update TLB and LAW size of NAND flash accordingly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Reserve default boot pageYork Sun2013-01-30-0/+16
| | | | | | | | | The boot page in memory is already reserved so OS won't overwrite. As long as the boot page translation is active, the default boot page also needs to be reserved in case the memory is 4GB or more. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/t4qds: move VSC3316 config data from t4qds.h to t4qds.cTimur Tabi2013-01-30-11/+12
| | | | | | | | | | Static variables should be defined in C files, not header files, because otherwise every C file that #includes the header file will generate a duplicate of the variables. Since the vsc3316_xxx[] arrays are only used by t4qds.c anyway, just put the variables there. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p2041: move Lanes mux to board early initShaohui Xie2013-01-30-39/+44
| | | | | | | | | | Lanes mux currently is configured in eth.c when initializing FMAN ethernet ports, but SRIO and PCIe also need lanes mux, so we move the lanes mux to p2041rdb.c which implements a board-specific initialization and will be called at early stage. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-01-29-39/+4
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| * Remove unused CONFIG_SYS_I2C_BUS[_SELECT]Michael Jones2013-01-29-35/+0
| | | | | | | | | | | | | | | | "CONFIG_SYS_I2C_BUS" and "CONFIG_SYS_I2C_BUS_SELECT" don't appear anywhere outside of config files. Signed-off-by: Michael Jones <michael.jones@matrix-vision.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * i2c: mxs: Staticize the functions in the driverMarek Vasut2013-01-29-4/+4
| | | | | | | | | | | | | | | | The local functions in the mxs i2c driver are not marked static, make it so. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxTom Rini2013-01-29-149/+96
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| * Merge remote-tracking branch 'mpc83xx/next'Kim Phillips2013-01-16-149/+96
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| | * powerpc/mpc83xx: convert MPC8313ERDB to new-SPLScott Wood2012-12-19-183/+37
| | | | | | | | | | | | | | | | | | | | | This converts MPC8313ERDB NAND boot to use the new SPL infrastructure. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * powerpc/mpc83xx: add support for new SPLScott Wood2012-12-19-22/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds arch support for PPC mpc83xx to boot "minimal" (4K) SPLs using the new infrastructure. Existing nand_spl targets are updated to deal with the name change from nand_init.c to spl_minimal.c (as in theory this isn't limited to NAND anymore). Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * spl: Change PAD_TO to CONFIG_SPL_PAD_TOScott Wood2012-12-19-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was already used by some SPL targets, and allows the pad amount to be specified by board config headers rather than only in makefile fragments. Also supply a pad-to of zero if the variable is undefined. It works without this, but this avoids relying on undocumented behavior. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | README.mips: update known issues and TODOsDaniel Schwierzeck2013-01-16-5/+6
| | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | README.qemu-mips: move README file from board to doc directoryDaniel Schwierzeck2013-01-16-0/+0
| | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | MIPS: qemu-mips: update and fix example usage in READMEDaniel Schwierzeck2013-01-16-7/+21
| | | | | | | | | | | | | | | | | | | | | | | | By now U-Boot supports Qemu MIPS for little and big endian as well as 32 bit and 64 bit. Update and fix the example usage in the README to reflect this. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | MIPS: qemu-mips: add '-M mips' switch to the example usage commandGabor Juhos2013-01-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the example command from the README file does not work as expected. qemu shows a text similar to the one below and it hangs. $ qemu-system-mips -L . -nographic Could not open option rom 'pxe-pcnet.rom': No such file or directory qemu-system-mips: pci_add_option_rom: failed to find romfile "vgabios-cirrus.bin" qemu: terminating on signal 15 from pid 19726 This happens because qemu emulates a Malta board by default if the machine type is not defined explicitely on the command line. For a working test, the '-M mips' switch is required: $ qemu-system-mips -M mips -L . -nographic Could not open option rom 'vgabios.bin': No such file or directory U-Boot 2013.01-rc2-00132-g1e8e648-dirty (Jan 08 2013 - 09:06:42) Board: Qemu -M mips CPU: 24Kf proc_id=0x19300 DRAM: 128 MiB ## Unknown flash on Bank 1 - Size = 0x00000000 = 0 MB Flash: 0 Bytes *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: NE2000 Hit any key to stop autoboot: 0 qemu-mips # Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Vlad Lungu <vlad.lungu@windriver.com>
* | | MIPS: qemu-mips: fix a typo in READMEGabor Juhos2013-01-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'Limitations & comments' section refers to the '-m mips' switch which is not valid. The '-m' switch can be used for setting the virtual RAM size: $qemu-system-mips --help | grep '^-m ' -m megs set virtual RAM size to megs MB [default=128] $ The correct switch for specifying the machine type is '-M'. Fix the text to refer to that. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Vlad Lungu <vlad.lungu@windriver.com>
* | | MIPS: bootm.c: add support for 'prep' and 'go' subcommandsGabor Juhos2013-01-16-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bootm command supports subcommands since long time however those subcommands are not yet usable on MIPS. The patch is based on the ARM implementation, and it adds support for the 'prep' and 'go' subcommands only. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* | | MIPS: bootm.c: separate environment initializationGabor Juhos2013-01-16-23/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the environment initialization code into a separate function. This make the code reusable for bootm subcommands. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* | | MIPS: bootm.c: separate linux jump codeGabor Juhos2013-01-16-13/+19
| | | | | | | | | | | | | | | | | | | | | | | | Move the actual jump code into a separate function. This make the code reusable for bootm subcommands. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* | | MIPS: bootm.c: use debug macro to print debug messageGabor Juhos2013-01-16-3/+1
|/ / | | | | | | | | | | | | | | The '## Transferring control ...' message is printed only if DEBUG is enabled. Get rid of the 'ifdef DEBUG' statement and use the debug macro instead. Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
* | Prepare v2013.01Tom Rini2013-01-15-1/+1
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | pxa: Save lr register in relocate_code functionŁukasz Dałek2013-01-14-0/+2
| | | | | | | | | | | | | | | | | | | | | | When u-boot is compiled for PXA25x processor, pxa/start.S is calling cpu_init_crit by BL instruction. BL is overwriting lr register so relocate_code is going into infinite loop. This patch preservs lr register in r12 before calling cpu_init_crit and after function returns restores it. Signed-off-by: Lukasz Dalek <luk0104@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2013-01-14-5/+8
|\ \
| * | VIDEO: better document the correct use of CONFIG_FB_ADDRWolfgang Denk2013-01-14-4/+7
| | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> cc: Anatolij Gustschin <agust@denx.de>
| * | lcd: restore ability to display 8 bpp BMPs on 16 bpp LCDsNikita Kiryanov2013-01-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit fb6a9aab7ae78c (LCD: display 32bpp decompressed bitmap image) broke the check that allowed U-Boot to display 8 bpp BMPs on a 16 bpp LCD screen, effectively turning this feature off. Restore this feature by changing the check back to the same meaning it originally had. To avoid future confusion, the check has also been rephrased to make its meaning clear. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
generated by cgit v1.1 at 2024-12-29 19:53:34 +0000