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* MLK-11159-2 Revert "MLK-11028 imx: mx6qp change L2 prefetch offset to 0"rel_imx_3.14.38_6qp_betal5.1.1_2.0.0_6qp-betaimx_v2014.04_3.14.38_6qp_betaRobby Cai2015-06-24-1/+1
| | | | | | | | | | | This reverts commit 2bc93d766dee5d5dc33035446f82622c4f1fb784. After further investigation, find L2 prefetch offset setting of 0xF is not the root cause for USB stress reboot failure. With the fix in USB driver, and L2 prefetch offset setting of 0xF, the reboot stress test has passed 4-days both on imx6q and imx6qp sabreauto board. Signed-off-by: Robby Cai <r63905@freescale.com>
* MLK-11159-1 Revert "MLK-11114 imx: mx6qp disable double line feature"Robby Cai2015-06-24-8/+0
| | | | | | | | | | | This reverts commit 046e55efa686f40b4cad312e1e64348f19107bd9. After further investigation, find the L2 cache double line fill is not the root cause for USB or SD3.0 stress reboot failure. With the fix in USB driver, and the L2 double line fill enabled, the reboot stress test has passed 4-days. So revert the patch to make L2 double line fill enabled on imx6qp by default. Signed-off-by: Robby Cai <r63905@freescale.com>
* MLK-11114 imx: mx6qp disable double line featurePeng Fan2015-06-16-0/+8
| | | | | | | | | | | With L2 double line fill enabled, the stress reboot test failure is met on USB(MLK10738) or SD3.0(MLK11072). By disabling L2 double line fill, the stress reboot can pass. Note we are still investigating on this issue to find the evidence how these issues are corelated with L2 double line fill. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11028 imx: mx6qp change L2 prefetch offset to 0Peng Fan2015-06-12-1/+1
| | | | | | | Change L2 prefetch offset to 0 to make system stable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 5cab58016a032ea364c8e5df3994ac51fdf60b0a)
* MLK-11035 imx: mx6 update thermal slope factorsPeng Fan2015-06-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | From temp sensor guys: " I confirmed the math with him(had do the accuracy study) today. The new, final equation is: Tmeas = (Nmeas - n1) / slope + t1 + offset n1= fused room count t1= 25 offset=3.580661 slope= 0.4148468 – 0.0015423*n1 " 87723f903454aaf17336e0fe9098ea7911c19f3c update the thermal with not accurate slope parameters. This patch fix it. Conflicts: drivers/thermal/imx_thermal.c Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit f02e68977da7d91d347f6015a5301fc82d72878f) (cherry picked from commit 5bf7dc588d3311a5493fe66cba9b36a239f3ddfd)
* MLK-10827 imx: mx6 update thermal driver according new equationPeng Fan2015-06-10-23/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From IC guys: " After a thorough accuracy study of the Temp sense circuit, we found that with our current equation, an average part can read 7 degrees lower than a known forced temperature. We also found out that the standard variance was around 2C; which is the tightest distribution that we could create. We need to change the temp sense equation to center the average part around the target temperature. Old Equation: Temp = Troom,cal – slope*(Count measured – Count room fuse) Where Troom,cal = 25C and Slope = 0.4297157 – (0.0015974 * Count room fuse) New Equation: Temp = Troom,cal – slope*(Count measured – Count room fuse) +offset Where Troom,cal = 25C and Slope = 0.4445388 – (0.0016549 * Count room fuse) Offset = 3.580661 " According the new equation, update the thermal driver. c1 and c2 changed to u64 type and update comments. Conflicts: drivers/thermal/imx_thermal.c since to imx_v2014.04, there is no imx_thermal driver, implement the new equation in arch/arm/cpu/armv7/mx6/soc.c. Also drop the orignial way to calculate temp, but use the way in imx_v2015.04 which aligns with linux kernel Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 87723f903454aaf17336e0fe9098ea7911c19f3c) (cherry picked from commit 7f8fa8b46f90d41fe3f37fbac40d8d773cdee5ce)
* MA-6732 Add sparse image flash support for uboot's fastbootguoyin.chen2015-06-09-59/+102
| | | | | | | | | Add aboot.o based on CONFIG_FASTBOOT Add partition index for fastboot ptn table Add return value for write_sparse_image to know the sparse write status Add path to write_sparse_image based on the image received and partition to be flashed Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
* aboot: fix block addressing for don't care chunk typeRob Herring2015-06-09-0/+1
| | | | | | | | | | | CHUNK_TYPE_DONT_CARE should skip over the specified number of blocks, but currently fails to increment the device block address. This results in filesystem images getting written incorrectly. Add the missing block address incrementing. Cc: Steve Rae <srae@broadcom.com> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Steve Rae <srae@broadcom.com>
* implement the Android sparse image formatSteve Rae2015-06-09-53/+111
| | | | | | update to provide usable implementation to U-Boot Signed-off-by: Steve Rae <srae@broadcom.com>
* cleanup code which handles the Android sparse image formatSteve Rae2015-06-09-41/+56
| | | | | | | - port dprintf() to debug() - update formatting Signed-off-by: Steve Rae <srae@broadcom.com>
* update code which handles Android sparse image formatSteve Rae2015-06-09-2438/+0
| | | | | | - remove unnecessary functions Signed-off-by: Steve Rae <srae@broadcom.com>
* add code to handle Android sparse image formatSteve Rae2015-06-09-0/+2643
| | | | | | | | Add original file (pristine) from : https://www.codeaurora.org/cgit/quic/la/kernel/lk/plain/app/aboot/aboot.c?h=master [3b5092d20bd15a7a2879c13e9f64acc48d04af2d] Signed-off-by: Steve Rae <srae@broadcom.com>
* add header for Android sparse image formatColin Cross2015-06-08-0/+49
| | | | | | | | | | Add a BSD-3 relicensed version of the Android sparse format image header from: https://android.googlesource.com/platform/system/core/+/28fa5bc347390480fe190294c6c385b6a9f0d68b/libsparse/sparse_format.h Unchanged except for the license header. Cc: Tom Rini <trini@ti.com> Signed-off-by: Colin Cross <ccross@android.com>
* MLK-11064 imx: mx6qp: Adjust AQos settings for peripheralsYe.Li2015-06-08-0/+3
| | | | | | | | | | To resolve USB camera bandwidth issue, the patch sets recommended AQoS setting from IC team value for peripheral and only on imx6qp. The address is: 0xbb0608, the value is: 0x80000201 Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit d00e9400bfbfb097ab5b0b26fae92db3dc1dd047)
* MLK-10957: ARM: mx6qp: do not turn off PURobin Gong2015-05-25-1/+2
| | | | | | | | | There is narrow window that PRE driver is ready but GPU driver probe later, and the later GPU driver turn on PU may cause 'PRE hang' issue. To simplify thing, do not turn off PU in u-boot. Signed-off-by: Robin Gong <b38343@freescale.com> (cherry picked from commit 6b0787b726e2ff32210d742d93ecd3f4bb2ae402)
* MLK-10740: add maximum ecc platfrom can supportHan Xu2015-04-30-1/+7
| | | | | | | | Add maximum ecc strength for each platfrom to avoid the calculated ecc exceed the limitation. Signed-off-by: Han Xu <b45815@freescale.com> (cherry picked from commit fdc5bac6ae8b699924c4e84b86e38aa73f694827)
* MLK-10747-2 video: ipu: Enable/disable LDB_DI clock when necessaryLiu Ying2015-04-30-7/+65
| | | | | | | | This patch adds enable/disable hooks support for ldb_di[0/1] clocks and enables/disables them when necessary. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 839a1da941be48baf27c9cb28939cc6b2030424a)
* MLK-10747-1 video: ipu: Build ldb_di clock relevant code only for MX6 and MX53Liu Ying2015-04-30-2/+14
| | | | | | | | The LDB is found in MX6 variants and MX53, so this patch makes the ldb_di clock relevant code be built only for them. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit c0dc175a9780505ec8939bda5dda9c2ec549a7f0)
* MLK-10756 imx: mx7darm2: Add support for MX7D 19x19 LPDDR3 ARM2 boardYe.Li2015-04-27-0/+1085
| | | | | | | | | | | | Add pre-codes for i.MX7D 19x19 LPDDR3 validation board to support devices: EIMNOR, NAND, USDHC1, i2C, ENET2, PMIC, USB, QSPI, SPINOR. build target: mx7d_19x19_lpddr3_arm2_config mx7d_19x19_lpddr3_arm2_eimnor_config Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f8f3a9f2323412168216e0515c5ad53cd006e076)
* fs: fat: read: fix fat16 ls/read issuePrzemyslaw Marczak2015-04-27-18/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The present fat implementation ignores FAT16 long name directory entries which aren't placed in a single sector. This was becouse of the buffer was always filled by the two sectors, and the loop was made also for two sectors. If some file long name entries are stored in two sectors, the we have two cases: Case 1: Both of sectors are in the buffer - all required data for long file name is in the buffer. - Read OK! Case 2: The current directory entry is placed at the end of the second buffered sector. And the next entries are placed in a sector which is not buffered yet. Then two next sectors are buffered and the mentioned entry is ignored. - Read fail! This commit fixes this issue by: - read two sectors after loop on each single is done - keep the last used sector as a first in the buffer before the read of two next The commit doesn't affects the fat32 imlementation, which works good as previous. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Mikhail Zolotaryov <lebon@lebon.org.ua> Cc: Tom Rini <trini@ti.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Simon Glass <sjg@chromium.org> Cc: Suriyan Ramasami <suriyan.r@gmail.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Wolfgang Denk <wd@denx.de> Tested-by: Simon Glass <sjg@chomium.org> (cherry picked from commit 64f65e1e36adffc39730635d104399937ea21949)
* MLK-10733 imx: imx6qpsabreauto: Update IPU QoS settingsLiu Ying2015-04-24-3/+3
| | | | | | | | | | | | | Update IPU QoS settings from 0x007f007f to 0x77177717 according to the SoC team's recommendation. This change should be able to balance AXI ID0/2/3 priority and set AXI ID1 priority relatively lower, which matches the way we use AXI ID0/1/2/3 for IDMAC23(0), regular IDMACs, IDMAC27 and IDMAC28 respectively in kernel. The specific priority values for each AXI ID are supposed to be picked for the sake of an overall good system performance. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* MA-6580 recovery.img cannot be authenticated by HABguoyin.chen2015-04-23-9/+13
| | | | | | | | | Remove the authentication size to be a fixed size, due to recovery.img may be much bigger than the boot.img Add signature size to boot or recovery image size, which is added by boot_signer in android build process Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
* MLK-10708 imx:mx6qp Update Saturation THR for PRExPeng Fan2015-04-21-4/+4
| | | | | | | Update settings for PRE. Value for Saturation THR of PREx, changed from 0x20 to 0x10 to make system more stable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10702 imx: mx7d: clock: correct fec MDC root clockFugang Duan2015-04-21-1/+1
| | | | | | | In i.MX7d platform, fec MDC root clock is ENET_AXI_ROOT_CLK, not ipg clock, correct it. Signed-off-by: Fugang Duan <B38611@freescale.com>
* MLK-10701 net: fec_mxc: setup right value for mdio hold timeFugang Duan2015-04-21-1/+3
| | | | | | | | | | | | | The minimal hold time according to IEE802.3 (clause 22) is 10 ns. HOLDTIME + 1 is the number of clk cycles the fec is holding the output. Set the right hold time value when the MDC root clock is greater than 100Mhz. The issue was reported on i.MX28 and is fixed by Uwe Kleine-König in kernel: https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/ drivers/net/ethernet/freescale/fec_main.c?id=63c607321492c5efc7a31bc4ea734b877f8e7f87 Signed-off-by: Fugang Duan <B38611@freescale.com>
* MLK-10674-2 imx: mx6qp settings for PREPeng Fan2015-04-17-0/+38
| | | | | | | | | | | | | | | | | | | | | Since the following piece settings can not be in DCD table, we add them in enable_ipu_clock. " setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0 setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1 setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2 setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3 setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0 setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1 setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2 setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE " CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h, the settings sure will effect. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10674-1 imx: mx6qpsabreauto Update to 1.05 DDR ScriptPeng Fan2015-04-17-1/+9
| | | | | | | | | | | | | | | | | | | Update to 1.05 ddr script, url: http://compass.freescale.net/livelink/livelink?func=ll& objId=233944823&objAction=browse&viewType=1 File name: arik_r2_sabre_ddr3_528_1.05c.inc Update: Read latency Aging control for IPU1/PRE0/PRE3 Aging control for IPU2/PRE1/PRE2 Test results: 3 boards passed overnight memtester stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10658 imx: mx7d 12x12 arm2: Update plugin codes to use latest DDR scriptYe.Li2015-04-15-23/+27
| | | | | | | | | The LPDDR3 intialization in plugin codes were missed to update in previous DDR script upgrading. So update the plugin codes to LPDDR3 script: 7D_lpddr3_0_2.ds5 Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10655 Video: Fix second line string display issueYe.Li2015-04-14-4/+5
| | | | | | | | The string display on second line repeats the last word of first line and does not show full. This is the bug introduced by the fixing to MLK-10542. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10647 armv7: Fix Dcache disable issue on i.MX7Ye.Li2015-04-14-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue on the i.MX7D is that, there is one cache-able memory access between the L1 and L2 cache flush by calling the flush_dache_all-> v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code. L1-cache-flush -> This will flush L1 cache to L2 cache in the end. Cache-able memory access -> This will have the chance cause the L1 line-fill with dirty data from L2 cache(L1 cache-line dirty, L2 clean) L2-cache-flush -> This will only flush L2 cache to L3, but still some dirty data on the L1 cacheline. After C & M bit clean, -> The dirty data on the L1 cache line lost, which will cause memory coherent issue if that dirty cache line has some useful data The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush. This patch should works fine on the i.MX6 and i.MX7. The second cache flush have zero impact on the i.MX6, but this is really need for the i.MX7D platform due to the L1 line-fill during the first dcache_flush. And the second flush will not bring in the L1 dirty cache line due to the C bit is clear now, which means the dcache is disabled. Acked-by: Jason Liu<r64343@freescale.com> Reviewed-by: Jason Liu<r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10542 video: Support multiple lines version string displayYe.Li2015-04-10-7/+23
| | | | | | | | | | | The caculation of left space for version string is not correct, should use VIDEO_COLS not VIDEO_LINE_LEN / 2, otherwise we will get larger space than actual have and cause string to overlay logo picture. Also current version string display only supports two lines words at max. This also causes overlay when the LCD pixel colume size is not enough. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10617 imx: mx7d 12x12 arm2: Update LPDDR3 script to 7D_lpddr3_0_2.ds5Ye.Li2015-04-10-1/+1
| | | | | | | | | | | | | | [The compass link for this script] http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153 &objAction=browse&sort=name [Changes in the script] This script enable MDLL, but make it much more margin for the unlock state . [DDR stress test result] 2 boards run the memtester for 3 days, and passed. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10597: arm: imx7d: extend iomuxc-lpsr IO pads config optionsAdrian Alonso2015-04-08-4/+39
| | | | | | | | * Extend IOMUXC-LPSR IO pads configuration options * Add alternative configuration modes for IO pads from IOMUXC-LPSR Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* MLK-10504 imx: mx6dqarm2: Fix CCM setting for lpddr2 400Mhz supportYe.Li2015-04-08-0/+6
| | | | | | | | | | | | | | | | | Current uboot supports for running LPDDR2 at 400MHz on MX6Q ARM2 board, but there is a problem in switching pre_periph_clk_sel to pll2_pfd2. We cannot directly change the parent of pre_periph_clk_sel as this mux is not a glitchless mux. We need to follow the correct procedure and wait for the busy bits to clear before switching. Change to follow the procedure: 1. Set periph_clk2 to OSC. 2. Switch the periph_clk to periph_clk2, checking the CCM_CDHIPR for periph_clk , ahb_podf and axi_podf busy bits. 3. Setting the pre_periph_clk to PLL2 PFD 396M. 4. Switch the periph_clk back to pre_periph_clk and checking CCM_CDHIPR busy bits. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10569 imx7d: call set_epdc_qos unconditionallyRobby Cai2015-04-07-4/+1
| | | | | | | This EPDC/EPXP QoS setting is needed for EPDC stress test to pass. This patch remove the #ifdef to make sure set_epdc_qos be called always. Signed-off-by: Robby Cai <r63905@freescale.com>
* MLK-10590: arm :imx7d: correct iomuxc-lpsr daisy chainAdrian Alonso2015-04-06-3/+3
| | | | | | | | | * Correct daisy chain settings for LPSR iomux controller * Add IOMUX_LPSR_SEL_INPUT_OFS only when pad is identified to be part of lpsr-iomuxc domain Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* MLK-10522-3: imx: mx7d_12x12_ddr3_arm2: add target board supportAdrian Alonso2015-04-03-0/+744
| | | | | | | | | | * Add mx7d_12x12_ddr3_arm2 target board support * Initial support for mx7d_12x12_ddr3_arm2 target board add support for base hardware eMMC, SD and ECSPI boot. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10522-2: arm: imx7d: add iomuxc-lpsr i2c pad settingsAdrian Alonso2015-04-03-1/+4
| | | | | | | | | | * Add IMX7D iomuxc-lpsr I2C1 and I2C2 pad configuration settings * Input select offset input_sel_ofs = 0x05xx + IOMUX_LPSR_SEL_INPUT_OFS allows to access register in iomuxc controller for imx_iomux_v3_setup_pad I2C daisy chaing configuration. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10522-1: mx7d_arm: allow override mtest settingsAdrian Alonso2015-04-03-0/+2
| | | | | | | | * Allow to override mtest settings for target board variants that differs on physical sdram memory size Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10566: arm :imx7d: fix iomuxc-lpsr daisy chain settingsAdrian Alonso2015-04-03-0/+4
| | | | | | | | | | | | | | * For IOMUXC LPSR pads when daisy chain register needs to be set the result offsets for sel_input register is incorrect as base address is 0x302C0000 and the passed offset does not resolve to the intended input sel pad register; input sel base offset should start in 0x30330000. * Add an addiotional fixed offset of 0x70000 to address the input sel offset: INPUT_SEL = 0x302C0000 + 0x70000 + sel_input_ofs. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10576 ARM: i.MX6: exclude the ARM errata from i.MX6 UP systemNitin Garg2015-04-03-0/+3
| | | | | | | | | | | | | | | The ARM errata 751472, 794072, 761320, 845369 only applied to the following configuration: This erratum affects configurations with either: - One processor if the ACP is present - Two or more processors i.MX6 family does not have the ACP and thus only the MPCore system will be impacted, which are the i.MX6DQ, i.MX6DL, and i.MX6QP. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* MLK-10568 imx: mx7d arm2: Update LPDDR3 script to 7D_lpddr3_0_1.ds5Ye.Li2015-04-05-19/+16
| | | | | | | | | | | | | | | | | | | | | [The compass link for this script] http://compass.freescale.net/livelink/livelinkfunc=ll&objid=233861153 &objAction=browse&sort=name [Changes in the script] 1. Change the DDR freq to 528Mhz. 2. Disable ddr phy dll, just force a dll output. IC suspects the dll in ddr phy may unlock sometimes. The side-effect is we will lost the ability to compensate the voltage/temperature change, so it may easy to fail at H/L temperature. [DDR stress test result] 3 boards involved the two days stress test by using memtester tool. One board met a kernel oops after one day test. Other two pass the two days test. Compared to previous DDR script, the result is much positive. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10567: Extend u-boot imximage to support check bits set/clrNitin Garg2015-04-02-15/+29
| | | | | | | | | | Add support for HAB "Check data" all bits set and clear check functionality. Rename CHECK_DATA to CHECK_BITS_SET. Flag=0 -> (*address & mask) == 0 | All bits clear Flag=2 -> (*address & mask) == mask | All bits set Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* mx6: drop ARM errata 742230Shawn Guo2015-03-31-1/+0
| | | | | | | | | | | | | | | | Commit e9fd66defd7e (ARM: mx6: define CONFIG_ARM_ERRATA_742230) enables errata 742230 for imx6, because it helps remove one reboot issue. However, this errata does not really apply on imx6, because Cortex-A9 on imx6 is r2p10 while the errata only applies to revisions r1p0..r2p2. At a later time, commit f71cbfe3ca5d (ARM: Add workaround for Cortex-A9 errata 794072) adds support of errata 794072, which applies to all Cortex-A9 revisions. As the workaround for both errata are exactly same, it makes a lot more sense to select 794072 instead of 742230 for imx6. Since we already enable 794072 for imx6, it's time to drop errata 742230 to avoid confusion. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* MLK-10524: iMX6x: Implement workaround for Cortex-A9 errata 845369Nitin Garg2015-03-31-0/+7
| | | | | | | | | Under very rare timing circumstances, transitioning into streaming mode might create a data corruption. Present on Two or more processors or 1 core with ACP, all revisions. This erratum can be worked round by setting bit[22] of the undocumented Diagnostic Control Register to 1. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* MLK-10520 add clk_ignore_unused in i.MX7d u-boot parameterHan Xu2015-03-31-0/+2
| | | | | | add this parameter in u-boot as a temporary workaround. Signed-off-by: Han Xu <b45815@freescale.com>
* MLK-10513 mx7: HAB: Fix HAB RVT addresses to unified sectionYe.Li2015-03-31-11/+5
| | | | | | | Incorrect hab_rvt addresses were used for getting HAB functions. Need to change to addresses in unified section. Signed-off-by: Ye.Li <B37916@freescale.com>
* MA-6483 Add imx6qp sabreauto boards support in Androidguoyin.chen2015-03-30-0/+1
| | | | | | Add nand config for android imx6qp sabreauto board Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
* MLK-10503 imx:mx6qp add missed macroPeng Fan2015-03-30-1/+4
| | | | | | is_mx6dqp should be only applied for MX6 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10499 imx:mx6qp update printed cpu infoPeng Fan2015-03-30-5/+14
| | | | | | We should print "MX6QP Rev1.0", but not "MX6Q Rev2.0". Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
generated by cgit v1.1 at 2024-11-21 12:44:30 +0000