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* MLK-10496: Check the PL310 version for applying errataNitin Garg2015-03-27-11/+15
| | | | | | | | | | | Apply errata based on PL310 version instead of compile time. Also set Prefetch offset to 15, since it improves memcpy performance by 35%. Don't enable Incr double Linefill enable since it adversely affects memcpy performance by about 32MB/s and reads by 90MB/s. Tested with 4K to 16MB sized src and dst aligned buffer. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* MLK-10492-2 imx: mx7dsabresd: Add TFT43AB LCD supportYe.Li2015-03-27-10/+10
| | | | | | | The mx7dsabresd uses new LCD TFT43AB which has 480 x 272 pixels. Update panel info for this LCD. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10492-1 imx: mx7d: Update LCDIF clock settingsYe.Li2015-03-27-7/+54
| | | | | | | | To support lower clock frequency, needs to set post divider and test divider in PLL_VIDEO. So update LCDIF clock settings function to support this feature. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10477-5 imx: mx7dsabresd: Add EPDC supportYe.Li2015-03-27-103/+267
| | | | | | | | | | | | | | | To enable the EPDC feature: 1. Uncomments CONFIG_SPLASH_SCREEN and CONFIG_MXC_EPDC settings in mx7dsabresd.h 2. cd <kernel_dir>/firmware/imx 3. python ihex2bin.py -i epdc_ED060XD4C1_TC.fw.ihex -o epdc_splash.bin 4. cp epdc_splash.bin to [FAT partition on SD card] Since the EPDC has pinmux conflicts with ENET and QSPI. These two modules can't work at same time. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10477-4 imx: mx7d 12x12 lpddr3 ARM2: Add EPDC supportYe.Li2015-03-27-2/+286
| | | | | | | | | | | | To enable the EPDC feature: 1. Uncomments CONFIG_SPLASH_SCREEN and CONFIG_MXC_EPDC settings in mx7d_12x12_lpddr3_arm2.h 2. cd <kernel_dir>/firmware/imx 3. python ihex2bin.py -i epdc_ED060XD4C1_TC.fw.ihex -o epdc_splash.bin 4. cp epdc_splash.bin to [FAT partition on SD card] Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10477-3 EPDC: Update EPDC driver head file for v2Ye.Li2015-03-27-207/+324
| | | | | | | To support EPDC V2 on mx7d, update the mxc_epdc_fb.h for new registers layout. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10477-2 imx: mx7d: Add EPDC clock init and base addressYe.Li2015-03-27-0/+34
| | | | | | Ungate the EPDC clock at system up if the EPDC is enabled Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10477-1 imx: mx7d: Add QoS settings for EPDCYe.Li2015-03-27-0/+34
| | | | | | Add the QoS settings function which is used for EPDC Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10478 mx6: EPDC: Improve EPDC usage and configurationYe.Li2015-03-27-180/+86
| | | | | | | | | | Change to load EPDC waveform from FAT partition and allocate waveform buffer, framebuffer and working buffer in dynamic manner not static. So many EPDC configurations are removed. To enable the EPDC feature, must define CONFIG_MXC_EPDC and CONFIG_SPLASH_SCREEN. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10487 imx: mx7dsabresd: Add build target for QPSI and NANDYe.Li2015-03-27-0/+2
| | | | | | | | Add targets for building u-boot to support QSPI booting and NAND booting. NAND booting can't work on mx7d TO1.0 Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10486 imx: mx6qpsabreauto: Add android supportYe.Li2015-03-27-0/+1
| | | | | | | | | Add Android build target for mx6qpsabreauto board to support android u-boot. target: mx6qpsabreautoandroid_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10476 imx: mx7dsabresd: Fix 74LV driver issueYe.Li2015-03-26-8/+9
| | | | | | | Should write the bits to SDI in reverse order because of the bits will be shifted. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10467 mtd:spi Add ATMEL AT45DB021E supportPeng Fan2015-03-26-1/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to add atmel AT45DB021E spi flash support. Since this flash is different from the spi flash that we previous use such as m25p32 and spanion spi nor flashes, pieces of code are added. 1. The default page size is 264 bytes, but the mtd/spi framework can not handle such page. So we need to configure the page size from 264 to 256 bytes. Page Size command seq “Power of 2” binary page size (256 bytes)| 3Dh 2Ah 80h A6h DataFlash page size (264 bytes) | 3Dh 2Ah 80h A7h And when probe the flash, configure the flash to 256 bytes page size, if the page size is already 256bytes, just return and do not configure it again. The page size configuration times is only about 10000, so to avoid configuring it each time. 2. Add the flash params in sf_params.c. 3. This flash support 2K block erase, add this flag. 4. The status command is 0xD7, different from others. It's polling status bit is Bit 7 -> 0 Device is busy with an internal operation. -> 1 Device is ready. This patch has been tested on mx7d 19x19 ddr3 arm2 board. And tested on mx7d 12x12 lpddr3 board. All works fine. Note: Since this flash is only 256KB, we can not test spi boot on mx7d 19x19 arm2 board. If want to test this flash, open CONFIG_SYS_USE_SPINOR. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MA-6381 Add HAB support for the whole boot.imgguoyin.chen2015-03-25-25/+73
| | | | | | | | boot.img includes kernel image, ramdisk img, dtb, and bootargs. All are critical for android security. Protect the whole boot.img with HAB. Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
* MLK-10453 mmc: fix possible unintialized ocrPeng Fan2015-03-20-1/+4
| | | | | | | | | | | This commit ca4113da25b42bce44a2e7998966a47352f11613 "mmc: fix OCR Polling" does not consider cmd structure, and may leave it in uninitialized state. We can directly use op_cond_response here, since until here, op_cond_response already get the OCR value from chip. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Suggested-by: Ye.Li <B37916@freescale.com>
* MLK-10448-6 imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board supportYe.Li2015-03-23-1/+347
| | | | | | | | | | | | | 1. Add DDR script v1.04 for i.MX6DQP SABREAUTO board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN. Build target: mx6qpsabreauto_config Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10448-5 imx: mx6qp: Enable PRG clock for IPUYe.Li2015-03-23-0/+6
| | | | | | | | | The i.MX6QP has a PRG module, need to enable its clock for using IPU. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Brown Oliver <B37094@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10448-4 mx6: hab : Remove the cache issue workaroud in hab for i.MX6QPYe.Li2015-03-23-2/+3
| | | | | | | Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10448-3 mx6: ccm: Change the clock settings for i.MX6QPYe.Li2015-03-23-22/+60
| | | | | | | | | | Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes. A new CONFIG_MX6QP is introduced here and is used for the CCM difference. At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10448-2 mx6: L2cache: Enable the double line fill for i.MX6DQPYe.Li2015-03-23-0/+3
| | | | | | | Since i.MX6DQP has fixed the L2 cache issue, enable the double line fill feature to provide better performance. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10448-1 mx6: Add MX6DQP CPU rev typeYe.Li2015-03-23-2/+10
| | | | | | | | Add new cpu type for i.MX6DQP and providing a dynamical detecting function. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10380 imx: mx6sx: update VDDSOC standby voltageBai Ping2015-03-21-6/+6
| | | | | | | | | | According the latest datasheet Rev.0,2/2015, the VDDSOC_IN voltage in standby/DSM mode is 1.05V. As we use PFM mode of pFuse and this mode has 3% tolerance issue, so the standby mode voltage should be (1.05 * 1.03) = 1.0815, we use 1.10V as the minimal step is 25mV. For i.MX6sx SDB RevB boards, the VDDARM and VDDSOC use the same supply, so the DSM voltage for VDDARM also need to be updated. Signed-off-by: Bai Ping <b51503@freescale.com>
* mxc_ocotp: Do not disable the OCOTP clock after every accessFabio Estevam2015-03-19-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Leave the OCOTP turned on, so that we subsequent access do not fail. After enabling the thermal driver on a mx6sxsabresd board: U-Boot 2015.01-rc1-18267-g99d4189-dirty (Nov 24 2014 - 12:59:01) CPU: Freescale i.MX6SX rev1.0 at 792 MHz CPU: Temperature 48 C Reset cause: POR Board: MX6SX SABRE SDB I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 00:01.0 - 16c3:abcd - Bridge device 01:00.0 - 8086:08b1 - Network controller In: serial Out: serial Err: serial Net: (hang) As the thermal driver accesses the ocotp registers, its clock will be disabled afterwards. Then when the MAC address is read (also from ocotp registers) it will cause a hang. Do not disable the ocotp clock to prevent this problem. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
* MLK-10446: mx7d_12x12_lpddr3_arm2: Enable 1.8V on PHY ctrlFabio Estevam2015-03-19-2/+0
| | | | | | | | Enable 1.8V on PHY control, so that Gigabit PHY operation can be functional. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* MLK-10445 mmc: fix OCR PollingPeng Fan2015-03-19-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If in mmc_send_op_cond, OCR_BUSY is set in CMD1's response, then state is transfered to Ready state, and there is no need to send CMD1 again. Otherwise following CMD1 will recieve no response, or timeour error from driver such as fsl_esdhc.c. If not into Ready state in previous CMD1, then continue CMD1 command. In mmc_complete_op_cond, we use the value mmc->op_cond_response from mmc_send_op_cond, since there should be no CMD1 command between mmc_send_op_cond and mmc_complete_op_cond Before fixing this, uboot log shows: " CMD_SEND:0 ARG 0x00000000 MMC_RSP_NONE CMD_SEND:8 ARG 0x000001AA MMC_RSP_R1,5,6,7 0x18EC1504 CMD_SEND:55 ARG 0x00000000 MMC_RSP_R1,5,6,7 0x18EC1504 CMD_SEND:0 ARG 0x00000000 MMC_RSP_NONE CMD_SEND:1 ARG 0x00000000 MMC_RSP_R3,4 0x00FF8080 CMD_SEND:1 ARG 0x40300000 MMC_RSP_R3,4 0xC0FF8080 --> Already OCR_BUSY set CMD_SEND:1 ARG 0x40300000 MMC_RSP_R3,4 0x0096850A --> Failed CMD1 MMC init failed " Using this patch, this issue is fixed, emmc can be detected correctly. This issue exists on mx7dsabresd and mx7d_12x12_lpddr3_arm2 board. Upstream Patchwork: https://patchwork.ozlabs.org/patch/451775/ Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10391 imx: mx7dsabresd: Fix issues in QSPI supportYe.Li2015-03-10-3/+3
| | | | | | | | Change QSPI FLASH vendor config from to MACRONIX, otherwise the flash device can't be recognized. Also change default sf probe parameter to 0:0 which means bus 0, cs 0. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10385-4 imx: mx7dsabresd: Add board codes for NAND flash supportYe.Li2015-03-10-61/+67
| | | | | | | | | | | | | Update board codes to support GPMI NAND flash. Since the GPMI NAND needs board rework, it is disabled at default. Two ways to enable GPMI NAND: 1. Define CONFIG_SYS_BOOT_NAND for NAND boot case 2. Modify the line 306 in mx7dsabresd.h from QSPI to NAND. #define CONFIG_SYS_USE_QSPI /* Enable the QSPI flash at default */ to #define CONFIG_SYS_USE_NAND /* Enable the NAND flash at default */ Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10385-3 imx: mx7: Enable rawnand clock at init for APBH-DMAYe.Li2015-03-10-0/+4
| | | | | | For APBH-DMA enabled case, we have to enable rawnand clock for mxs_dma_init. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10385-2 imx: nand: Update GPMI NAND driver to support MX7DYe.Li2015-03-09-4/+4
| | | | | | Update GPMI NAND driver and BCH head file with definitions for CONFIG_MX7 Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10385-1 imx: apbh_dma: Update APBH-DMA for MX7DYe.Li2015-03-09-8/+8
| | | | | | Update APBH-DMA driver and head files with definitions for CONFIG_MX7 Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10374 imx: mx6sx 14x14 arm2: Change dtb file name to 14x14 arm2Ye.Li2015-03-05-2/+2
| | | | | | | | The default DTB file name used for i.MX6SX 14x14 lpddr2 arm2 board is 17x17 arm2, since kernel has added a new dtb for 14x14 board, change the default file name to the new imx6sx-14x14-arm2.dtb Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10215 Add elan init in i.MX6SL-EVK boardHaibo Chen2015-03-05-1/+56
| | | | | | | | | | | | | | | | | | | | EPDC board contain a elan touch screen, this screen is a i2c slave. If this EPDC board connect to i.MX6SL-EVK board, after uboot boot up, if we do i2c operation, like i2c probe, then the i2c bus block. This is due to the elan touch screen i2c slave. This device needs to do some initialization opearation before its i2c operation, otherwise this i2c device pull down the i2c clk line, and make the i2c bus hang. This means elan needs a special flow on i2c before its address is acked, otherwise the i2c bus will be hang. This patch is a workaround, it add a void function which is defined as a weak symbol in i2c driver, and it is called before every i2c operation. In mx6slevk, this function was overwrite to execute elan initialization. So that, for mx6slevk board, it will initialize elan before every i2c operation, but for other boards, it just work as before. Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
* MLK-10370: imx7d-12x12-arm2 imximage: update dcd table for lpddr3Adrian Alonso2015-03-04-14/+22
| | | | | | | | | * Update DCD table for lpddr3 @400Mhz * Boot kernel linux and run memtester for memory stress memtester 1G 100000 Signedoff-by: Ye.Li <B37916@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* MLK-10363-3 Android: Add android support for MX7D SABRESD boardYe.Li2015-03-04-0/+160
| | | | | | | Enable android fastboot, recovery, booti features for mx7d sabresd board by using new build target: mx7devkandroid_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10363-2 imx: mx7: Enable SNVS clockYe.Li2015-03-04-0/+2
| | | | | | Enable SNVS clock in clock_init function as default enabled clock. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10363-1 udc: Update i.MX udc driver to support MX7Ye.Li2015-03-04-31/+12
| | | | | | | Update driver codes and registers define for MX7. Implement udc callback function in MX7 arch. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10362 imx: mx7dsabresd: Add support for MX7D SABRESD boardYe.Li2015-03-04-0/+1594
| | | | | | | | | | | Add i.MX7D SABRESD board BSP codes, with enabled modules: UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX. Build target: mx7dsabresd_config Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10361 imx: mx7d arm2: Change to use WDOG_B resetYe.Li2015-03-04-5/+34
| | | | | | | | | | | | | | | | | | | The default u-boot reset is a internal WDOG reset (warm reset on i.MX6) which does not have power and DDR reset. So the peripherals and DDR may meet problem. When using the internal WDOG reset on i.MX7D ARM2 boards, we meets two DDR issues: 1. On 12x12 ARM2, sometimes the system may hang in DCD because the DDRC Operating Mode does not become to normal. 2. On 19x19 ARM2, the reset always brings system to USB download because the DDR3 turns to unstable. On the i.MX7D ARM2 board, the WDOG_B signal connects to POR_B or PMIC_PWRON. This gives a chance to use a stronger reset. So in this patch, we set the IOMUX for WDOG_B pin and enable WDOG_B signal output in WDOG WCR register. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10360 imx: iomux-v3: Fix the driver issue for MUX_CTL with offset 0Ye.Li2015-03-03-2/+1
| | | | | | | | | | | | | The IOMUX-v3 driver checks the MUX_CTL register offset. If the offset is zero, it will skip the MUX_CTL register setting. This behavior is correct for previous platforms like i.MX6, but on i.MX7, the IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00 is at offset 0. Thus, it causes the MUX setting to this pin always not working. This fix removes this condition checking since it is unnecessary. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10358 imx: imx6sx_17x17arm2_wp: Add the i.MX6SX 17x17wp ARM2 board supportJason Liu2015-03-03-0/+119
| | | | | | Add the i.MX6SX 17x17wp ARM2 board support. SCH: SPF-28432 Signed-off-by: Jason Liu <r64343@freescale.com>
* MLK-10351 imx: mx7d: Add 19x19 DDR3L ARM2 board supportYe.Li2015-03-02-0/+1072
| | | | | | | | | | Add BSP codes, configuration head file and build target for 19x19 DDR3L ARM2 board with basic functions: ENET2, I2C, SD/eMMC/MMC, USB, QSPI, ECSPI, pfuze3000 PMIC. Build target: mx7d_19x19_ddr3_arm2_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10288: imx: mx7: change the imx7d board config qspi target nameHan Xu2015-02-24-1/+1
| | | | | | | | change the target name from mx7d_12x12_lpddr3_arm2_qspi to mx7d_12x12_lpddr3_arm2_qspi1, it could be more convenient for yocto build Signed-off-by: Han Xu <b45815@freescale.com>
* MLK-10260-2: imx: MX6DQ POP: Add i.MX6DQ POP ARM2 board changesYe.Li2015-02-12-3/+8
| | | | | | | | | The SD3 CD pin is changed to DNP, so hardcode the CD pin to always connected. Enable the SD3 VSELECT pin, because the 1.8/3.3v selection works on this board. Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10260-1: imx: MX6DQ POP: Change the DDR size to 256M bytesYe.Li2015-02-12-1/+1
| | | | | | | The DDR encapsulated in MX6DQ POP is 256M bytes not the 1G. Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10208 qspi: fix at least 16 bytes fifo issuePeng Fan2015-02-09-4/+5
| | | | | | | | | | | | | | | | | | | This patch "http://sw-git.freescale.net/cgi-bin/gitweb.cgi?p=uboot-imx.git; a=commitdiff;h=71779872ed7072f0ca90dd4db776dd8960b595f4" does not consider the corner case, such as 2, 3, 6, 7, 10 bytes. If len is 2, then t1 is 0, t2 is 2. The original way: t3 = t1 + t2 --> t3 = 2 --> 12 bytes are wrote but not 16. The new way: t3 = t1 + ((t2 + 3) >> 2) --> t3 = 1 --> 16 bytes are wrote. Here t2 is not zero, 4 bytes are wrote, there are still 12 bytes need to be wrote. Since t1 is 0, t3 = 1, for (t3 = 1; t3 < 4; t3++) will write the other 12 bytes. In this patch, when write data, QUADSPI_MCR_CLR_TXF_MASK should be used to clear TXFIFO, but not QUADSPI_MCR_CLR_RXF_MASK. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10206-2 imx: mx7: Fix temperature checking issueYe.Li2015-02-06-14/+16
| | | | | | | | It is the same temperature checking problem as mx6 codes. The patch fixes this issue by blocking the booting until the temperature is lower than TEMPERATURE_HOT. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10206-1 imx: mx6: Fix temperature checking issueYe.Li2015-02-06-15/+17
| | | | | | | | | The current temperature checking will not stop booting when temperature is over TEMPERATURE_MAX value. This is a bug in the temperature polling. The patch fixes this issue by blocking the booting until the temperature is lower than TEMPERATURE_HOT. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10209 imx: mx7d_12x12_lpddr3_arm2: Add targets for QSPI and SPI bootYe.Li2015-02-05-0/+2
| | | | | | | | | Add two build targets for booting from QSPI NOR and SPI CS1 NOR respectively. When using these images, the u-boot environment variables are stored to NOR flash not the SD card. Signed-off-by: Ye.Li <B37916@freescale.com>
* ARM: Fix overflow in MMU setupMarek Vasut2015-02-05-1/+1
| | | | | | | | | | | | | | | | | | | The patch fixes a corner case where adding size to DRAM start resulted in a value (1 << 32), which in turn overflew the u32 computation, which resulted in 0 and it therefore prevented correct setup of the MMU tables. The addition of DRAM bank start and it's size can end up right at the end of the address space in the special case of a machine with enough memory. To prevent this overflow, shift the start and size separately and add them only after they were shifted. Hopefully, we only have systems in tree which have DRAM size aligned to 1MiB boundary. If not, this patch would break such systems. On the other hand, such system would be broken by design anyway. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> (cherry picked from commit 221a49d5bd4a512596c03bbc59fb28f4ef48bf6e)
* MLK-10200 imx: mx7: Add M4 booting supportYe.Li2015-02-05-2/+18
| | | | | | Implement the auxiliary core booting for Cortex M4 on i.MX7 Signed-off-by: Ye.Li <B37916@freescale.com>
generated by cgit v1.1 at 2024-12-18 02:00:10 +0000