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* MLK-10496: Check the PL310 version for applying errataimx_v2014.04_3.14.28_1.0.0_gaNitin Garg2015-04-07-8/+15
| | | | | | | | | | | | Apply errata based on PL310 version instead of compile time. Also set Prefetch offset to 15, since it improves memcpy performance by 35%. Don't enable Incr double Linefill enable since it adversely affects memcpy performance by about 32MB/s and reads by 90MB/s. Tested with 4K to 16MB sized src and dst aligned buffer. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 48277f0a5162d2e1d67e6cfb830be9799f1c1904)
* MLK-10576 ARM: i.MX6: exclude the ARM errata from i.MX6 UP systemNitin Garg2015-04-03-0/+3
| | | | | | | | | | | | | | | | The ARM errata 751472, 794072, 761320, 845369 only applied to the following configuration: This erratum affects configurations with either: - One processor if the ACP is present - Two or more processors i.MX6 family does not have the ACP and thus only the MPCore system will be impacted, which are the i.MX6DQ, i.MX6DL. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit 0db960784ba4f631ee5c0321b5d25f3b1ac55640)
* MLK-10524: iMX6x: Implement workaround for Cortex-A9 errata 845369Nitin Garg2015-03-31-0/+7
| | | | | | | | | | Under very rare timing circumstances, transitioning into streaming mode might create a data corruption. Present on Two or more processors or 1 core with ACP, all revisions. This erratum can be worked round by setting bit[22] of the undocumented Diagnostic Control Register to 1. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 70ad44e523680de67dd8b7a7505d7f27799980ee)
* mx6: drop ARM errata 742230Shawn Guo2015-03-31-1/+0
| | | | | | | | | | | | | | | | Commit e9fd66defd7e (ARM: mx6: define CONFIG_ARM_ERRATA_742230) enables errata 742230 for imx6, because it helps remove one reboot issue. However, this errata does not really apply on imx6, because Cortex-A9 on imx6 is r2p10 while the errata only applies to revisions r1p0..r2p2. At a later time, commit f71cbfe3ca5d (ARM: Add workaround for Cortex-A9 errata 794072) adds support of errata 794072, which applies to all Cortex-A9 revisions. As the workaround for both errata are exactly same, it makes a lot more sense to select 794072 instead of 742230 for imx6. Since we already enable 794072 for imx6, it's time to drop errata 742230 to avoid confusion. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* MLK-10215 Add elan init in i.MX6SL-EVK boardrel_imx_3.14.28_1.0.0_gaHaibo Chen2015-03-05-1/+56
| | | | | | | | | | | | | | | | | | | | EPDC board contain a elan touch screen, this screen is a i2c slave. If this EPDC board connect to i.MX6SL-EVK board, after uboot boot up, if we do i2c operation, like i2c probe, then the i2c bus block. This is due to the elan touch screen i2c slave. This device needs to do some initialization opearation before its i2c operation, otherwise this i2c device pull down the i2c clk line, and make the i2c bus hang. This means elan needs a special flow on i2c before its address is acked, otherwise the i2c bus will be hang. This patch is a workaround, it add a void function which is defined as a weak symbol in i2c driver, and it is called before every i2c operation. In mx6slevk, this function was overwrite to execute elan initialization. So that, for mx6slevk board, it will initialize elan before every i2c operation, but for other boards, it just work as before. Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
* MLK-10134 imx: mx6dqarm2: Add MX6DQ PoP validation board supportYe.Li2015-01-23-4/+403
| | | | | | | | | | The MX6DQ PoP validation board is similar as MX6DQ ARM2 board. So reuse the ARM2 BSP codes with new DDR script used. The build target for MX6DQ PoP validation board is: mx6qarm2_pop_lpddr2_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MA-6048 Correct word in uboot log for android recovery modeguoyin.chen2014-12-23-1/+1
| | | | | | Change "founded" to "found" Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
* MLK-10035-2: supports NAND chips with oob size up to 744 byteAllen Xu2014-12-16-11/+19
| | | | | | | | | | | | | Update the u-boot code to support NAND chips with oob size up to 744 byte. For the NAND flash MT29F32G08CBADA, which consists of 2 planes x 1064 blocks per plane. Obviously the block number is not power-of-2. But all MTD driver assumes the page per block and block per plane must be a power of 2 number. So the last 40 blocks in each plane must be truncated. Signed-off-by: Allen Xu <b45815@freescale.com>
* MLK-10035-1: truncate the number of blocks to power-of-2 for MT29F32G08CBADAWPBrian Norris2014-12-16-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some bright specification writers decided to write this in the ONFI spec (from ONFI 3.0, Section 3.1): "The number of blocks and number of pages per block is not required to be a power of two. In the case where one of these values is not a power of two, the corresponding address shall be rounded to an integral number of bits such that it addresses a range up to the subsequent power of two value. The host shall not access upper addresses in a range that is shown as not supported." This breaks every assumption MTD makes about NAND block/chip-size dimensions -- they *must* be a power of two! And of course, an enterprising manufacturer has made use of this lovely freedom. Exhibit A: Micron MT29F32G08CBADAWP "- Plane size: 2 planes x 1064 blocks per plane - Device size: 32Gb: 2128 blockss [sic]" This quickly hits a BUG() in nand_base.c, since the extra dimensions overflow so we think it's a second chip (on my single-chip setup): ONFI param page 0 valid ONFI flash detected NAND device: Manufacturer ID: 0x2c, Chip ID: 0x44 (Micron MT29F32G08CBADAWP), 4256MiB, page size: 8192, OOB size: 744 ------------[ cut here ]------------ kernel BUG at drivers/mtd/nand/nand_base.c:203! Internal error: Oops - BUG: 0 [#1] SMP ARM [... trim ...] [<c02cf3e4>] (nand_select_chip+0x18/0x2c) from [<c02d25c0>] (nand_do_read_ops+0x90/0x424) [<c02d25c0>] (nand_do_read_ops+0x90/0x424) from [<c02d2dd8>] (nand_read+0x54/0x78) [<c02d2dd8>] (nand_read+0x54/0x78) from [<c02ad2c8>] (mtd_read+0x84/0xbc) [<c02ad2c8>] (mtd_read+0x84/0xbc) from [<c02d4b28>] (scan_read.clone.4+0x4c/0x64) [<c02d4b28>] (scan_read.clone.4+0x4c/0x64) from [<c02d4c88>] (search_bbt+0x148/0x290) [<c02d4c88>] (search_bbt+0x148/0x290) from [<c02d4ea4>] (nand_scan_bbt+0xd4/0x5c0) [... trim ...] ---[ end trace 0c9363860d865ff2 ]--- So to fix this, just truncate these dimensions down to the greatest power-of-2 dimension that is less than or equal to the specified dimension. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Allen Xu <b45815@freescale.com>
* MLK-9891-2: board: freescale: mx6sxsabreauto: enable WDOG_B settingRobin Gong2014-12-17-0/+2
| | | | | | Enable WDOG_B setting to workaround QSPI boot issue. Signed-off-by: Robin Gong <b38343@freescale.com>
* MLK-9891-1: ARM: imx6: split WDOG_B setting from set_anatop_bypass() functionRobin Gong2014-12-17-15/+21
| | | | | | | | We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to reboot whole board, so split these code to independent function so that board file can call it freely. Signed-off-by: Robin Gong <b38343@freescale.com>
* MA-6012 imx:Enlarge the bootargs number limitation for imx6 boardsguoyin.chen2014-12-16-3/+3
| | | | | | Set CONFIG_SYS_MAXARGS to be 256, which aligned with mx6sx boards config Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
* MA-5830 Align Fastboot NAND config with bootloader partition 64Mguoyin.chen2014-12-04-4/+10
| | | | | | | Align the "MLK-9918: Reserve more space in uboot partition for NAND boot configurations" to enlarge the bootloader partition to be 64M Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
* MLK-9953 pcie: disable pcie on imx6sx platformsRichard Zhu2014-12-04-1/+11
| | | | | | | | | | | | | | The PCIe support in uboot would bring failures in i.MX6SX PCIe EP/RC validations. Disable PCIe support in uboot here. RootCause: The bit10(ltssm_en) of GPR12 would be set in uboot, thus the i.MX6SX PCIe EP would be cheated that the other i.MX6SX PCIe RC had been configured and trying to setup PCIe link directly, although the i.MX6SX RC is not properly configured at that time. PCIe can be supported in uboot, if the i.MX6SX PCIe EP/RC validation is not running. Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
* MLK-9938 GIS: Enable GIS function on imx6sx SDB boardSandor Yu2014-12-01-1/+7
| | | | | | | Enable GIS function on imx6sx SDB uboot. Expand CONFIG_SYS_MALLOC_LEN to 16M. Signed-off-by: Sandor Yu <R01008@freescale.com>
* MLK-9933 imx:mx6sxsabresd correct info for PFUZEPeng Fan2014-12-01-1/+6
| | | | | | | | | We use PFUZE200 for SX SDB RevB board and PFUZE100 for SX SDB RevA board. Show correct msg according DeviceID, since PFUZE200 and PFUZE100 have different DeviceID. PFUZE200's id is 1, while PFUZE100's is 0. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 6ad39425bbc8b6dcade3ecd4883f624e277588c1)
* MLK-9927 - change the kernel and dtb location for nand readAllen Xu2014-11-28-6/+6
| | | | | | | | kernel and dtb file location should be changed from 0x1000000 and 0x2000000 to 0x4000000 and 0x5000000, since the uboot partition expanded to 64M. Signed-off-by: Allen Xu <b45815@freescale.com>
* MLK-9918: Reserve more space in uboot partition for NAND boot configurationsAllen Xu2014-11-22-7/+7
| | | | | | | Expand the uboot space to 64m to reserve enough space for FCB, DBBT and u-boot. Signed-off-by: Allen Xu <b45815@freescale.com>
* MLK-9898 imx:mx6 fix ana2 offset of fuse bank1Peng Fan2014-11-24-0/+2
| | | | | | | | | According to RM, there is 16bytes between offset ana1 and offset ana2. So should add 3 int hole 'u32 reserved[3]' between ana1 and ana2. Also add the reserved bytes for ana2 in this patch. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-9890 imx:mx6sxsabresd add bmode sd3 supportPeng Fan2014-11-21-0/+1
| | | | | | | Current uboot does not support bmode sd3. So add this to make 'bmode sd3' command in uboot can work fine. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-9854 mtd index change for imx6 sabreautoAllen Xu2014-11-15-0/+7
| | | | | | | | Modified the mtd index for imx6 sabreauto board, split the parallel nor to two partitions and the NAND index could be align with imx6sx board for mfgtool download. Signed-off-by: Allen Xu <b45815@freescale.com>
* MLK-9853 changed the mtd index for rootfs on imx6sx sabreautoAllen Xu2014-11-15-1/+1
| | | | | | | | On imx6sx sabreauto, both QSPI1 and NAND would be mapped as mtd devices, since we have already set the kernel to load QSPI1 first, the mtd index for NAND need to be changed. Signed-off-by: Allen Xu <b45815@freescale.com>
* MLK-9852: U-Boot documentation needs note about booting from NANDJay Monkman2014-11-14-2/+3
| | | | | | Note added to README.mxc_hab Signed-off-by: Jay Monkman <jay.monkman@freescale.com>
* MLK-9807: add 14x14 arm2 nand bootFrank Li2014-11-12-0/+1
| | | | | | Add 14x14 arm2 nand support Signed-off-by: Frank Li <Frank.Li@freescale.com>
* MLK-9819: ARM: mx6sx: clear WDOG3 Power Down Enable bit for i.mx6sxRobin Gong2014-11-11-0/+19
| | | | | | | | | | Since we use WDOG_B reset now, we have to clear WDOG3 Power Down Enable bit to avoid system reboot during normal kernel boot. For mx6sxsabresd board, we have to make sure pad setting for WDOG_B ready before mux ready, otherwise also cause reboot. But that dependes on hardware design, only need on mx6sxsabresd board. Signed-off-by: Robin Gong <b38343@freescale.com>
* MLK-9343 QSPI signal pin pad setting - drive strength too strongAllen Xu2014-11-10-8/+8
| | | | | | | Changed the QSPI PAD setting, the previous output drive strength is too strong. Signed-off-by: Allen Xu <b45815@freescale.com>
* MLK-9748 imx: mx6sxsabreauto: Add GIS supportYe.Li2014-10-27-1/+7
| | | | | | | | | MX6SX sabreauto board has analog video input from VADC. Add the GIS support for this board that video input can display on LVDS at booting. The environment variable "gis" must be set to "vadc" to enable the function. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9733 imx: mx6sxsabreauto/mx6sxarm2: Fix nand clock glitchYe.Li2014-10-24-3/+18
| | | | | | | Since the qspi2_clk_root is the root clock of u_gpmi_bch_input_gpmi_io_clk, before switching the parent of qspi2_clk_root, we must gate off it. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9734 imx: mx6sxsabreauto: Add NAND boot environment variablesYe.Li2014-10-24-0/+23
| | | | | | | For NAND boot, the kernel zImage and rootfs also need to load from NAND. Add the environment variables for this. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9697 pcie: PERST_GPIO and POWER_GPIO are currently swappedRichard Zhu2014-10-24-2/+2
| | | | | | Fix the GPIO assignments as per the board schematics. Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
* MLK-9735 new config for 19x19 ARM2 board NAND bootAllen Xu2014-10-23-0/+1
| | | | | | supported NAND boot on 19x19 ARM2 board. Signed-off-by: Allen Xu <b45815@freescale.com>
* MLK-9714 imx: imximage tool: Fixed the bootdata.size calculationYe.Li2014-10-22-1/+1
| | | | | | | | The bootdata.size should contain the IVT offset part, but the calculation for bootdata.size in imximage tool does not. This will cause some data at the end of image not be loaded into memory. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9706 imx: mx6sx19x19arm2: Fix ENET card MAX7322 reset issueYe.Li2014-10-20-5/+5
| | | | | | | | | | | The MAX7322 will fail to work on 19x19 arm2 revB board. This failure is caused by the MAX7322 reset pin is not released when calling the setup_fec function. The MAX7322 reset pin is same as PHY reset pin. This patch fixes the issue by moving the PHY reset from setup_iomux_fec1 to setup_fec. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9705 imx: mx6sxsabreauto: add MAX7310 support to reset peripheralsYe.Li2014-10-20-0/+46
| | | | | | | | | The MAX7310 uses I2C3 bus. At system initialization, enable the driver to: 1. Reset CPU_PER_RST_B signal 2. Set the steering for ENET 3. Enable the LVDS display Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9705 imx: mx6sx: Set the pad setting SION for I2C3 pinsYe.Li2014-10-20-2/+2
| | | | | | When set the pinmux to I2C functionality, the SION is required to enabled. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9676 imx: mx6sx 19x19arm2: Fix ethernet phy reset issueYe.Li2014-10-11-2/+2
| | | | | | | The PHY reset on 19x19 arm2 board is GPIO6_18, not GPIO4_22. This causes the ethernet phy failed to work. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9652 Android: imx6sxsabreauto: Add android features supportYe.Li2014-10-09-0/+170
| | | | | | Add android fastboot, recovery and booti support for mx6sx sabreauto board. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9668 imx: mx6sxsabreauto: Fix bmode valueYe.Li2014-10-09-3/+3
| | | | | | Set the correct bmode value for booting from SDA/SDB/QSPI1/NAND Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9665-2 mx6sx: define CONFIG_SPI_FLASH_BARPeng Fan2014-10-09-0/+3
| | | | | | | | | | | | define CONFIG_SPI_FLASH_BAR in mx6sx_arm2.h mx6sxsabreauto.h to enable access to flash array higher than 16MB. CONFIG_SPI_FLASH_BAR is also set in mx6sxsabresd.h for RevB board. Actually, if QSPI flash size <= 16MB, setting CONFIG_SPI_FLASH_BAR has not effect. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-9665-1 QuadSPI: Support flash bigger than 16MBPeng Fan2014-10-09-1/+50
| | | | | | | | | | | | By introducing CONFIG_SPI_FLASH_BAR and add related command in LUT to enable fsl_qspi.c can handle flash size bigger that 16M. Because uboot does not support 32bits address access, this means bank address should be used to access bigger flash. It is hard to let qspi driver dynamically set LUT, so BRRD BRWR RDEAR and WREAR are all supported. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-9636 QuadSPI: add 4k erase supportPeng Fan2014-10-08-1/+13
| | | | | | | | OPCODE_BE_4K is supported. To qspi flashes which support 4k sector erase, spi framework will use OPCODE_BE_4K command. Thus add this support to let uboot can erase such qspi flashes. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-9640 ARM: imx6sx: enable ldo-bypass on mx6sxsabresd boardRobin Gong2014-09-30-16/+109
| | | | | | enable ldo-bypass check on all mx6sxsabresd boards. Signed-off-by: Robin Gong <b38343@freescale.com>
* MLK-9646 imx: mx6sxsabreauto: Change DDR size to 2GYe.Li2014-09-29-1/+1
| | | | | | | | The mx6sx sabreauto boards uses 2G DDR3. Modify the configuration PHYS_SDRAM_SIZE to this size. Signed-off-by: Ye.Li <B37916@freescale.com> Acked-by: Jason Liu
* ENGR00333317 imx: mx6sxsabreauto: Add BSP support for AI boardYe.Li2014-09-26-0/+1589
| | | | | | | | | | | | | | | | Create mx6sx sabreauto BSP file and configurations. The devices below have been supported: 1. SD/MMC/eMMC on SDA/SDB (base board) sockets 2. USB OTG port and USB HOST port (base board) 3. NAND flash 4. QuadSPI flash on QSPI1 5. I2C 6. PMIC PFUZE100 7. Onboard ethernet chip on ENET2 8. Splash screen on LVDS Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00333299: Add support for i.MX6SX 14x14 lpddr2 arm2 boardNitin Garg2014-09-25-0/+302
| | | | | | | Add support for i.MX6SX 14x14 lpddr2 arm2 board, same as 17x17 arm2 except lpddr2 instead of ddr3. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* sf: probe: Fix quad bit set pathPoddar, Sourav2014-09-25-10/+10
| | | | | | | | | | Currently, flash quad bit is set in "spi_flash_validate_params" and later at the end in the same api, we write 0 to status register for few flashes, thereby overriding the quad bit set. This fix moves the quad bit setting outside this api in "spi_flash_probe_slave" Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* ENGR00332535 imx: mx6sx: Remove WEIM plugin work around for TO 1.2 and higherYe.Li2014-09-23-1/+7
| | | | | | | | ROM fixes the WEIM plugin issue in TO 1.2. The work around for hacking WEIM base address to ROM variable is not needed. To avoid hacking useful data, remove the work around for TO 1.2 and higher revisions. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331269 arm: mx6: select OSC as uart's clk parentAnson Huang2014-09-18-0/+9
| | | | | | | | As M4 is sourcing UART clk from OSC, to make UART work when M4 is enabled, need to select OSC as clk parent, 24M OSC is enough for debug UART in uboot. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00331706-5 imx: mx6: Enable 24Mhz OSC for GPTYe.Li2014-09-18-0/+1
| | | | | | | Set the CONFIG_MXC_GPT_HCLK configuration in mx6_common.h, so that enable the 24Mhz OSC GPT on all MX6 platforms. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331706-4 imx: mx6sl: Set the preclk clock source to OSC 24MhzYe.Li2014-09-18-0/+16
| | | | | | | For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the preclk setting with kernel. Signed-off-by: Ye.Li <B37916@freescale.com>
generated by cgit v1.1 at 2024-11-21 15:06:11 +0000