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* sf: probe: Add support for EN25Q64Jagannadha Sutradharudu Teki2013-10-07-0/+1
| | | | | | Add support for EON EN25Q64 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Remove unneeded flash drivers filesJagannadha Sutradharudu Teki2013-10-07-1508/+0
| | | | | | | Now the common probing is handled in spi_flash_probe.c hence removed the unneeded flash drivers. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: ramtron: Add support for separate flash driverJagannadha Sutradharudu Teki2013-10-07-284/+125
| | | | | | | | Compared to other spi flashes, ramtron has a different probing and implementation on flash ops, hence moved ramtron probe code into ramtron driver. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add proper comment style on spi_flash structureJagannadha Sutradharudu Teki2013-10-07-28/+39
| | | | | | | Added proper comment style on spi_flash structure to make more readable. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Simply the BAR configuration logicJagannadha Sutradharudu Teki2013-10-07-54/+20
| | | | Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Add support for flag status pollingJagannadha Sutradharudu Teki2013-10-07-5/+12
| | | | | | | | From Micron, 512MB onwards, flash requires to poll flag status instead of read status- hence added E_FSR flag on spectific flash parts. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Add support for erase sector selection flagJagannadha Sutradharudu Teki2013-10-07-84/+100
| | | | | | | | SECT_4K, SECT_32K and SECT_64K opeartions are performed to to specific flash by adding a SECT* flag on respective spi_flash_params.flag param. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Add support to clear flash BP# bitsJagannadha Sutradharudu Teki2013-10-07-0/+7
| | | | | | | | | | Few of the flashes(Atmel, Macronix and SST) require to clear BP# bits in flash power ups. So clear these BP# bits at probe time, so-that the flash is ready for user operations. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Add support for SST_WPJagannadha Sutradharudu Teki2013-10-07-77/+188
| | | | | | | | | | Most of the SST flashes needs to write up using SST_WP, AAI Word Program, so added a flag param on spi_flash_params table. SST flashes, which supports SST_WP need to use a WP write sst_write_wp instead of common flash write. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Give proper spacing on flash table paramsJagannadha Sutradharudu Teki2013-10-07-77/+77
| | | | | | Given proper spacing between flash table params. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Add support for AT45DB* flash partsJagannadha Sutradharudu Teki2013-10-07-1/+9
| | | | | | | | | | Added AT45DB* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Add support for SST25* flash partsJagannadha Sutradharudu Teki2013-10-07-1/+12
| | | | | | | | | | | Added SST25* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
* sf: probe: Add support for S25FL* flash partsJagannadha Sutradharudu Teki2013-10-07-6/+25
| | | | | | | | | | Added S25FL* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Add support for W25* flash partsJagannadha Sutradharudu Teki2013-10-07-1/+32
| | | | | | | | | | Added W25* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Add support for MX25L* flash partsJagannadha Sutradharudu Teki2013-10-07-1/+9
| | | | | | | | | | Added MX25L* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Add support for GD25* flash partsJagannadha Sutradharudu Teki2013-10-07-1/+4
| | | | | | | | | | Added GD25* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Add support for EN25Q* flash partsJagannadha Sutradharudu Teki2013-10-07-1/+4
| | | | | | | | | | Added EN25Q* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Add support for M25P* flash partsJagannadha Sutradharudu Teki2013-10-07-1/+8
| | | | | | | | | Added M25P* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Add new spi_flash_probe supportJagannadha Sutradharudu Teki2013-10-07-122/+385
| | | | | | | | | | | Added new spi_flash_probe support, currently added N25Q* flash part attributes support. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Divide spi_flash into multiple partsJagannadha Sutradharudu Teki2013-10-07-567/+596
| | | | | | | | | | | | | | | | Divided the spi_flash framework into mutiple parts for - spi_flash.c: spi flash core file, interaction for spi/qspi driver to spi_flash framework. - spi_flash_ops.c spi flash preffered operations, erase,write and read. - spi_flash_probe.c spi flash probing, easy to extend probing functionality. This change will support to extend the functionality in a proper manner. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-04-2/+476
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| * ARM: VExpress: enable ARMv7 virt support for VExpress A15Andre Przywara2013-10-03-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable hypervisors utilizing the ARMv7 virtualization extension on the Versatile Express board with the A15 core tile, we add the required configuration variable. Also we define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the VExpress specific manner. There is no need to provide a custom smp_waitloop() function here. This also serves as an example for what to do when adding support for new boards. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: extend non-secure switch to also go into HYP modeAndre Przywara2013-10-03-9/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the KVM and XEN hypervisors to be usable, we need to enter the kernel in HYP mode. Now that we already are in non-secure state, HYP mode switching is within short reach. While doing the non-secure switch, we have to enable the HVC instruction and setup the HYP mode HVBAR (while still secure). The actual switch is done by dropping back from a HYP mode handler without actually leaving HYP mode, so we introduce a new handler routine in our new secure exception vector table. In the assembly switching routine we save and restore the banked LR and SP registers around the hypercall to do the actual HYP mode switch. The C routine first checks whether we are in HYP mode already and also whether the virtualization extensions are available. It also checks whether the HYP mode switch was finally successful. The bootm command part only calls the new function after the non-secure switch. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: add SMP support for non-secure switchAndre Przywara2013-10-03-1/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the non-secure switch is only done for the boot processor. To enable full SMP support, we have to switch all secondary cores into non-secure state also. So we add an entry point for secondary CPUs coming out of low-power state and make sure we put them into WFI again after having switched to non-secure state. For this we acknowledge and EOI the wake-up IPI, then go into WFI. Once being kicked out of it later, we sanity check that the start address has actually been changed (since another attempt to switch to non-secure would block the core) and jump to the new address. The actual CPU kick is done by sending an inter-processor interrupt via the GIC to all CPU interfaces except the requesting processor. The secondary cores will then setup their respective GIC CPU interface. While this approach is pretty universal across several ARMv7 boards, we make this function weak in case someone needs to tweak this for a specific board. The way of setting the secondary's start address is board specific, but mostly different only in the actual SMP pen address, so we also provide a weak default implementation and just depend on the proper address to be set in the config file. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: trigger non-secure state switch during bootm executionAndre Przywara2013-10-03-0/+13
| | | | | | | | | | | | | | | | | | To actually trigger the non-secure switch we just implemented, call the switching routine from within the bootm command implementation. This way we automatically enable this feature without further user intervention. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: add C function to switch to non-secure stateAndre Przywara2013-10-03-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core specific part of the work is done in the assembly routine in nonsec_virt.S, introduced with the previous patch, but for the full glory we need to setup the GIC distributor interface once for the whole system, which is done in C here. The routine is placed in arch/arm/cpu/armv7 to allow easy access from other ARMv7 boards. We check the availability of the security extensions first. Since we need a safe way to access the GIC, we use the PERIPHBASE registers on Cortex-A15 and A7 CPUs and do some sanity checks. Boards not implementing the CBAR can override this value via a configuration file variable. Then we actually do the GIC enablement: a) enable the GIC distributor, both for non-secure and secure state (GICD_CTLR[1:0] = 11b) b) allow all interrupts to be handled from non-secure state (GICD_IGROUPRn = 0xFFFFFFFF) The core specific GIC setup is then done in the assembly routine. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: add assembly routine to switch to non-secure stateAndre Przywara2013-10-03-2/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While actually switching to non-secure state is one thing, another part of this process is to make sure that we still have full access to the interrupt controller (GIC). The GIC is fully aware of secure vs. non-secure state, some registers are banked, others may be configured to be accessible from secure state only. To be as generic as possible, we get the GIC memory mapped address based on the PERIPHBASE value in the CBAR register. Since this register is not architecturally defined, we check the MIDR before to be from an A15 or A7. For CPUs not having the CBAR or boards with wrong information herein we allow providing the base address as a configuration variable. Now that we know the GIC address, we: a) allow private interrupts to be delivered to the core (GICD_IGROUPR0 = 0xFFFFFFFF) b) enable the CPU interface (GICC_CTLR[0] = 1) c) set the priority filter to allow non-secure interrupts (GICC_PMR = 0xFF) Also we allow access to all coprocessor interfaces from non-secure state by writing the appropriate bits in the NSACR register. The generic timer base frequency register is only accessible from secure state, so we have to program it now. Actually this should be done from primary firmware before, but some boards seems to omit this, so if needed we do this here with a board specific value. The Versatile Express board does not need this, so we remove the frequency from the configuration file here. After having switched to non-secure state, we also enable the non-secure GIC CPU interface, since this register is banked. Since we need to call this routine also directly from the smp_pen later (where we don't have any stack), we can only use caller saved registers r0-r3 and r12 to not mess with the compiler. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: add secure monitor handler to switch to non-secure stateAndre Przywara2013-10-03-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A prerequisite for using virtualization is to be in HYP mode, which requires the CPU to be in non-secure state first. Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine which switches the CPU to non-secure state by setting the NS and associated bits. According to the ARM architecture reference manual this should not be done in SVC mode, so we have to setup a SMC handler for this. We create a new vector table to avoid interference with other boards. The MVBAR register will be programmed later just before the smc call. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: prepare armv7.h to be included from assembly sourceAndre Przywara2013-10-03-1/+5
| | | | | | | | | | | | | | | | armv7.h contains some useful constants, but also C prototypes. To include it also in assembly files, protect the non-assembly part appropriately. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* | Prepare v2013.04-rc4Tom Rini2013-10-02-1/+1
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-02-1569/+3918
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| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-10-02-93/+3269
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| | * i.MX6DQ/DLS: Add pad MX6_PAD_GPIO_1__USB_OTG_IDEric Nelson2013-09-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the pad to i.MX6DQ and changes the i.MX6DLS declaration to match the Linux kernel declaration. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
| | * mx6: Fix use of improper value in enable_ipu_clockPierre Aubert2013-09-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The value MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET that was used to initialize the CCGR3 register caused an undefined value for CG0. Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * mx35pdk: Fix error handling in board_late_init()Fabio Estevam2013-09-27-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | If smc911x_initialize() fails we should return the error immediately. While at it, also check the error from cpu_eth_init(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * mx28evk: Propagate the error if cpu_eth_init() failsFabio Estevam2013-09-27-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | If cpu_eth_init() fails we should return the error immediately. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| | * mx28evk: Propagate the error if cpu_eth_init() failsFabio Estevam2013-09-27-0/+2
| | | | | | | | | | | | | | | | | | If cpu_eth_init() fails we should return the error immediately. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * tools/imximage.c: Fix compiling warningYork Sun2013-09-27-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert set_hdr_func(struct imx_header *imxhdr) to set_hdr_func(void) to get rid of the warning warning: ‘imxhdr’ is used uninitialized in this function Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * net: fec_mxc: Fix timeouts during tftp transferFabio Estevam2013-09-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Performing tftp transfers on mx28 results in random timeouts. Hector Palacios and Robert Hodaszi analyzed the root cause being related to the wrong alignment of the 'buff' buffer inside fec_recv(). Benoît Thébaudeau provided an excellent analysis of the alignment bug that is present on older versions, such as GCC 4.5.4: http://marc.info/?l=u-boot&m=137942904906131&w=2 Use ALLOC_CACHE_ALIGN_BUFFER() to avoid alignment issues from older GCC versions. Reported-by: Hector Palacios <hector.palacios@digi.com> Tested-by: Oliver Metz <oliver@freetz.org> Tested-by: Hector Palacios <hector.palacios@digi.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
| | * mx6sabresd: Fix the fdt file for the mx6dl versionFabio Estevam2013-09-20-0/+4
| | | | | | | | | | | | | | | | | | | | | We need to load 'imx6dl-sabresd.dtb' in the mx6dl version. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| | * doc: README.mxs: Add instruction to install 'libssl-dev'Fabio Estevam2013-09-20-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit bce883707 (ARM: mxs: tools: Add mkimage support for MXS bootstream) the following build error is seen when doing a MAKEALL build: $ ./MAKEALL mx28evk Configuring for mx28evk - Board: mx28evk, Options: ENV_IS_IN_MMC mxsimage.c:18:25: fatal error: openssl/evp.h: No such file or directory Add an entry about the need of installing the 'libssl-dev' package. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| | * mx28evk: Fix checkpatch warningFabio Estevam2013-09-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following checkpatch warning: $ ./tools/checkpatch.pl -F board/freescale/mx28evk/mx28evk.c CHECK: Alignment should match open parenthesis #109: FILE: freescale/mx28evk/mx28evk.c:109: + writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, + &clkctrl_regs->hw_clkctrl_enet); Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * i.MX6DL/S: add drive-strength back to pads DISP0_DAT2/DAT10Eric Nelson2013-09-20-2/+2
| | | | | | | | | | | | | | | | | | | | | This patch fixes a regression introduced by commit 87d720e0. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| | * mx6slevk: Add Ethernet supportFabio Estevam2013-09-20-0/+130
| | | | | | | | | | | | | | | | | | | | | | | | mx6slevk has a SMSC8720 connected in RMII mode. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * net: fec_mxc: Add support for mx6 solo-liteFabio Estevam2013-09-20-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Similarly as mx25 and mx53, mx6solo-lite needs to setup the MII gasket for RMII mode. Add support for mx6solo-lite. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6qsabreauto: Return error if cpu_eth_init() failsFabio Estevam2013-09-20-1/+1
| | | | | | | | | | | | | | | | | | | | | Currently board_eth_init() always return 0, but we should propagate the error when cpu_eth_init() fails. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6sabresd: Return error if cpu_eth_init() failsFabio Estevam2013-09-20-1/+1
| | | | | | | | | | | | | | | | | | | | | Currently board_eth_init() always return 0, but we should propagate the error when cpu_eth_init() fails. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx35pdk: Remove CONFIG_SYS_CACHELINE_SIZEFabio Estevam2013-09-20-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In arch/arm/cpu/arm1136/cpu.c we have: #ifndef CONFIG_SYS_CACHELINE_SIZE #define CONFIG_SYS_CACHELINE_SIZE 32 #endif ,so there is no need to define 'CONFIG_SYS_CACHELINE_SIZE' with the default size in the board config file. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mmc: fsl_esdhc: Check the result from malloc()Fabio Estevam2013-09-20-0/+2
| | | | | | | | | | | | | | | | | | malloc can fail, so we should better check its return value before using it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6sabresd: Reset counter to prevent error messageFabio Estevam2013-09-20-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a HDMI cable is not connected, the following message is seen on boot: CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: POR Board: MX6-SabreSD DRAM: 1 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 No panel detected: default to HDMI unsupported panel HDMI Reset the 'i' variable to fix the 'unsupported panel' message. This follows the same idea of commit 47ac53d7ae (imx: nitrogen6x/mx6qsabrelite: Fix bug in board_video_skip). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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