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* km_arm: change CONFIG_SYS_TEXT_BASE to end of RAMValentin Longchamp2011-10-05-1/+1
| | | | | | | | | This allows to test a larger part of the RAM in the memory tests. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Cc: Heiko Schocher <hs@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com>
* POST: add new memory regions testValentin Longchamp2011-10-05-19/+73
| | | | | | | | | | | | | | | This test is similar to the actual POST memory test but quicker and far less complete. It checks the address and data lines and then only tests some regularly placed sub regions of the RAM. This can be useful when we want to test the RAM but we do not have enough time to run the full memory test. The POST memory test code was rearranged in order to avoid code duplication between the two tests but the memory test functionnality remains the same. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Ackey-by: Mike Frysinger <vapier@gentoo.org>
* POST: drivers/memory.c coding style cleanupValentin Longchamp2011-10-05-56/+57
| | | | | | | This is needed for a further patch adding a new memory test. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* POST: make env test flags fetching optionalValentin Longchamp2011-10-05-5/+15
| | | | | | | | | | | | | | Some boards have the environment variables defined in a slow EEPROM. post_run accesses these environment variables to define which tests have to be run (in post_get_flags). This is very slow before the code relocation on some boards with a slow I2C EEPROM for environement variables. This patch adds a config option to skip the fetching of the test flags in the environment variables. The test flags assigned to the tests then only are the ones statically defined for the test in post/tests.c. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* POST: add post_log_res field for post results in global dataValentin Longchamp2011-10-05-4/+10
| | | | | | | | | | | | | | | | The current post_log_word in global data is currently split into 2x 16 bits: half for the test start, half for the test success. Since we alredy have more than 16 POST tests defined and more could be defined, this may result in an overflow and the post_output_backlog would not work for the tests defined further of these 16 positions. An additional field is added to global data so that we can now support up to 32 (depending of architecture) tests. The post_log_word is only used to record the start of the test and the new field post_log_res for the test success (or failure). The post_output_backlog is for this change also adapted. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* POST: allow redefinition of post_word_load/storeValentin Longchamp2011-10-05-0/+8
| | | | | | | | | | The predefinde post_word_load/store functions do not fit all boards, so we introduce a way to define post_word_load/store as externs in post.h that then can be defined in board specific files. This is done with the CONFIG_POST_EXTERNAL_WORD_FUNCS #define Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* POST/arm: adaptations needed for POST on ARM to workValentin Longchamp2011-10-05-0/+6
| | | | | | | | | | | For post to run on ARM, 3 things are needed: - post_log_word to be defined in gd - a post.h include in arch/arm/lib/board.c Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Cc: Mike Frysinger <vapier@gentoo.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* console: Implement pre-console bufferGraeme Russ2011-10-05-2/+88
| | | | | | | | | | | | | Allow redirection of console output prior to console initialisation to a temporary buffer. To enable this functionality, the board (or arch) must define: - CONFIG_PRE_CONSOLE_BUFFER - Enable pre-console buffer - CONFIG_PRE_CON_BUF_ADDR - Base address of pre-console buffer - CONFIG_PRE_CON_BUF_SZ - Size of pre-console buffer (in bytes) The pre-console buffer will buffer the last CONFIG_PRE_CON_BUF_SZ bytes Any earlier characters are silently dropped.
* Makefile: remove mx31pdk exceptionStefano Babic2011-10-05-10/+2
| | | | | | | | | An entry in the main Makefile for the mx31pdk board is not necessary, and the board is added to boards.cfg as all other targets. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Wolfgang Denk <wd@denx.de>
* Makefile: drop imx31_phycore from general MakefileStefano Babic2011-10-05-8/+2
| | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* Makefile: remove tx25 exceptionStefano Babic2011-10-05-4/+0
| | | | | | | | | An entry in the main Makefile for the tx25 board is not necessary, and the board is added to boards.cfg as all other targets. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Wolfgang Denk <wd@denx.de>
* PPC: Cleanup tqm8xx_pcmcia.cMarek Vasut2011-10-05-73/+81
| | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Tested-by: Wolfgang Denk <wd@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* TQM8xx: make room for growing code size due to I/O accessor cleanupWolfgang Denk2011-10-05-136/+2
| | | | | | | | | | | | | Commit "PPC: Cleanup tqm8xx_pcmcia.c" will clean up the PCMCIA code to use I/O accessors instead of plain volatile pointer accesses. This will result in about 300 byte bigger code. Fix custom linker script to make room for this. While we are at it, drop unmaintained u-boot.lds.debug linker script. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Tested-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-nand-flashWolfgang Denk2011-10-04-125/+185
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-nand-flash: PPC: Fix socrates NAND problem PPC: Fix fsl_upm.c by renaming nand handling functions NAND: Make page, erase, oob size available via cmd_nand mtd: eLBC NAND: remove elbc_fcm_ctrl->oob_poi NAND: Add -y option to nand scrub command NAND: Add nand read.raw and write.raw commands NAND: Really ignore bad blocks when scrubbing spl, nand: add 4bit HW ecc oob first nand_read_page function mxc_nand: fix a problem writing more than 32MB mxc_nand: fixed some typos (cosmetic) nand: increase chip_delay in mv kirkwood nand driver
| * PPC: Fix socrates NAND problemMarek Vasut2011-10-03-35/+35
| | | | | | | | | | | | | | | | | | nand.c:36: error: static declaration of 'nand_read_buf' follows non-static declaration /home/marex/u-boot/include/nand.h:139: error: previous declaration of 'nand_read_buf' was here Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * PPC: Fix fsl_upm.c by renaming nand handling functionsMarek Vasut2011-10-03-8/+8
| | | | | | | | | | | | | | | | This avoids colision with nand subsystem's functions. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * NAND: Make page, erase, oob size available via cmd_nandMarek Vasut2011-10-03-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "nand info" and "nand device" now set shell/environment variables: nand_writesize ... nand page size nand_oobsize ..... nand oob area size nand_erasesize ... nand erase block size Also, the "nand info" command now displays this info. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> [scottwood@freescale.com: removed unnecessary memsets] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * mtd: eLBC NAND: remove elbc_fcm_ctrl->oob_poimhench2011-10-03-30/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The eLBC NAND driver currently follows up each program/write operation with a read-back of the page, in order to [ostensibly] fill in ECC data for the caller. However, the page address used for this read is always -1, so the read will never work correctly. Remove this useless (and potentially problematic) block of code. v2: fix broken mailer Signed-off-by: mhench <mhench@elutions.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * NAND: Add -y option to nand scrub commandMarek Vasut2011-10-03-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | This allows the scrub command to scrub without asking the user if he really wants to scrub the area. Useful in scripts. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * NAND: Add nand read.raw and write.raw commandsMarek Vasut2011-10-03-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | These commands should work around various "hardware" ECC and BCH methods. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> [scottwood@freescale.com: s/write the page/access the page/] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * NAND: Really ignore bad blocks when scrubbingMarek Vasut2011-10-03-22/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> [scottwood@freescale.com: use chip instead of redundant priv_nand] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * spl, nand: add 4bit HW ecc oob first nand_read_page functionHeiko Schocher2011-10-03-0/+42
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * mxc_nand: fix a problem writing more than 32MBHelmut Raiger2011-10-03-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When writing 0x4000 to the unlockend_blkaddr register, large writes to a 2k page NAND sometimes fail. The current kernel driver writes 0xFFFF to this register for V2 of the nand controller. However on an i.MX31 this also fixes writes larger than 32MB. The datasheet is very unspecific, but (0x4000=16384)*2000 roughly fits the limits we're encountering with NAND writes. This problem might be NAND chip specific. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * mxc_nand: fixed some typos (cosmetic)Helmut Raiger2011-10-03-10/+9
| | | | | | | | | | Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * nand: increase chip_delay in mv kirkwood nand driverStefan Bigler2011-10-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The new SAMSUNG NAND Flash K9F1G08U0D require a bigger chip_delay. The Data Transfer from Cell to Register is >= 35us. Other Vendors and older chips normally use >= 25us. To have enough margin 40us is selected. Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Stefan Roese <sr@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-10-04-737/+12055
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/p3060: Add SoC related support for P3060 platform powerpc/85xx: Add support for setting up RAID engine liodns on P5020 powerpc/85xx: Refactor some defines out of corenet_ds.h fm-eth: Add ability for board code to disable a port powerpc/mpc8548: Add workaround for erratum NMG_LBC103 powerpc/mpc8548: Add workaround for erratum NMG_DDR120 powerpc/mpc85xxcds: Fix PCI speed powerpc/mpc8548cds: Fix booting message powerpc/p4080: Add support for secure boot flow powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards powerpc/p2041rdb: remove watch dog related codes powerpc/p2041rdb: updated description of cpld command powerpc/p2041rdb: add more ddr frequencies support powerpc/p2041rdb: set sysclk according to status of physical switch SW1 powerpc/p2041rdb: update cpld reset command according to CPLD 2.0 powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver powerpc/mpc8xxx: Add DDR2 to unified DDR driver powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps() powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en powerpc/85xx: Refactor P2041RDB to use common p_corenet files powerpc/85xx: refactor common P-Series CoreNet files for FSL boards powerpc/85xx: Enable CMD_REGINFO on corenet boards powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries powerpc/85xx: Fix USB protocol definitions for P1020RDB powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM powerpc/mpc8xxx: Move DDR RCW overriding to common code powerpc/mpc8xxx: Extend CWL table powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536 powerpc/85xx: Cleanup extern in corenet_ds board code powerpc/p2041rdb: Add ethernet support on P2041RDB board powerpc/85xx: Add networking support to P1023RDS powerpc/hydra: Add ethernet support on P5020/P3041 DS boards powerpc/85xx: Add FMan ethernet support to P4080DS powerpc/85xx: Add support for FMan ethernet in Independent mode powerpc/mpc8548cds: Cleanup mpc8548cds.c powerpc/mp: add support for discontiguous cores powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries fdt: Add new fdt_create_phandle helper fdt: Rename fdt_create_phandle to fdt_set_phandle powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010) powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC) fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010) powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB nand: Freescale Integrated Flash Controller NAND support powerpc/85xx: Add basic support for P1010RDB powerpc/85xx: Add support for new P102x/P2020 RDB style boards powerpc/85xx: relocate CCSR before creating the initial RAM area powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0 powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
| * | powerpc/p3060: Add SoC related support for P3060 platformShengzhou Liu2011-10-03-1/+403
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Add support for setting up RAID engine liodns on P5020Kumar Gala2011-10-03-2/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Refactor some defines out of corenet_ds.hKumar Gala2011-10-03-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move some SoC/board specific defines out of corenet_ds.h and into the corresponding P3041DS/P4080DS/P5020.h. We moved CONFIG_MMC, CONFIG_PCIE3, & CONFIG_FSL_NGPIXIS because the P3060 SoC/reference board does not have these devices and it will share the same board code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fm-eth: Add ability for board code to disable a portKumar Gala2011-10-03-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SoC configuration may have more ports enabled than a given board actually can utilize. Add a routinue that allows the board code to disable a port that it knows isn't being used. fm_disable_port() needs to be called before cpu_eth_init(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc8548: Add workaround for erratum NMG_LBC103Kumar Gala2011-10-03-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document. Any local bus transaction may fail during LBIU resynchronization process when the clock divider [CLKDIV] is changing. Ensure there is no transaction on the local bus for at least 100 microseconds after changing clock divider LCRR[CLKDIV]. Refer to the erratum LBIU3 of mpc8548. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc8548: Add workaround for erratum NMG_DDR120Kumar Gala2011-10-03-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some early version silicons. The default settings of the DDR IO receiver biasing may not work at cold temperature. When a failure occurs, a DDR input latches an incorrect value. The workaround will set the receiver to an acceptable bias point. Signed-off-by: Gong Chen Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc85xxcds: Fix PCI speedchenhui zhao2011-10-03-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | The CDS uses PCICLK as SYSCLK. The PCICLK should be 33333333Hz or 66666666Hz. Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc8548cds: Fix booting messagechenhui zhao2011-10-03-3/+3
| | | | | | | | | | | | | | | | | | Align the output for PCI. Replace "PCI" with "PCI1". Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
| * | powerpc/p4080: Add support for secure boot flowRuchika Gupta2011-10-03-3/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASHRuchika Gupta2011-10-03-2/+19
| | | | | | | | | | | | | | | Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com>
| * | powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boardsKumar Gala2011-10-03-0/+2
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/p2041rdb: remove watch dog related codesShaohui Xie2011-10-03-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPLD 2.2 removed board watch dog support due to the limitation of CPLD capacity after adding all the requested features, such as switch overriding. There is no pin-compatible upgrade part available for current PCB design. So remove codes related to it. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/p2041rdb: updated description of cpld commandShaohui Xie2011-10-03-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | According to CPLD 2.2, the default configuration is changed, so updated the description of CPLD command, otherwise it will confusing. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/p2041rdb: add more ddr frequencies supportShaohui Xie2011-10-03-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This table covers DDR frequencies from 666 to 1666. Frequencies 666, 833, 1000, 1066 and 1333 were verified on this board with SO-DIMM (UG51U6400N8SU-ACF). Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/p2041rdb: set sysclk according to status of physical switch SW1Shaohui Xie2011-10-03-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8], software need to read the SW1 status to decide what the sysclk needs. SW1[8~6] : frequency 0 0 1 : 83.3MHz 0 1 0 : 100MHz others: 66.667MHz Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/p2041rdb: update cpld reset command according to CPLD 2.0Shaohui Xie2011-10-03-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | CPLD 2.0 provides a new register which bit[0] is set to '1' will reset board with initializing the CPLD registers to default values. And add bit[6] of register at offset 0x5 to use to enable flash bank selection. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driverYork Sun2011-09-29-11/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update MPC8349EMDS to use unified DDR driver instead of spd_sdram.c. The unified driver can initialize data using DDR controller. No need to use DMA if just to initialze for ECC. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driverYork Sun2011-09-29-19/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unified DDR driver is maintained for better performance, robustness and bug fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of overall improvement. It requires changes for board files to customize platform-dependent parameters. To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx in the header file. No more boards will be accepted without such definition. Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1 and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc8xxx: Add DDR2 to unified DDR driverYork Sun2011-09-29-17/+287
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR2 has different ODT table and values. Adding table according to Samsung application note. Fix additive latency calculation to avoid interger underflow. Also converted typedef dynamic_odt_t to struct dynamic_odt. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()York Sun2011-09-29-15/+11
| | | | | | | | | | | | | | | | | | | | | Reduce the calculation error to 1ps. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slotsYork Sun2011-09-29-4/+7
| | | | | | | | | | | | | | | | | | | | | The two slots on the same controller have different addresses. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_enYork Sun2011-09-29-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | Check second DIMM slot in case the first one is empty. Honor DQS enable option for SDRAM mode register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Refactor P2041RDB to use common p_corenet filesKumar Gala2011-09-29-202/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The P2041RDB has almost identical setup for TLB, LAWS, and PCI with other P-Series CoreNet platforms. The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the TLB and LAW setup tables. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: refactor common P-Series CoreNet files for FSL boardsKumar Gala2011-09-29-5/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently support 4 SoC/Boards from the P-Series of QorIQ SoCs that are based on the 'CoreNet' Architecture: P2041RDB, P3041DS, P4080DS, and P5020DS. There is a significant amount of commonality shared between these boards that we can refactor into common code: * Initial LAW setup * Initial TLB setup * PCI setup We start by moving the shared code between P3041DS, P4080DS, and P5020DS into a common directory to be shared with other P-Series CoreNet boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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