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* USB storage countKim B. Heino2010-04-08-6/+9
| | | | | | | | | | | | | | | | Here's another USB storage patch. Currently U-Boot handles storage devices #0 - #4 as valid devices, even if there is none connected. This patch fixes usb_stor_get_dev() to check detected device count instead of MAX-define. This is very important for ill behaving devices. usb_dev_desc[] can be partially initialized if device probe fails. After fixing get_dev() it was easy to fix "usb part" etc commands. Previously it outputed "Unknown partition table" five times, now it's "no USB devices available". Signed-off-by: Kim B. Heino <Kim.Heino@bluegiga.com>
* EHCI: add NEC PCI IDSergei Shtylyov2010-04-08-0/+1
| | | | | | | | | Add NEC EHCI controller to the list of the supported devices. Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com> drivers/usb/host/ehci-pci.c | 1 + 1 file changed, 1 insertion(+)
* EHCI: fix port reset reportingSergei Shtylyov2010-04-08-15/+17
| | | | | | | | | Commit b416191a14770c6bcc6fd67be7decf8159b2baee (Fix EHCI port reset.) didn't move the code that checked for successful clearing of the port reset bit from ehci_submit_root(), relying on wait_ms() call instead. The mentioned code also erroneously reported port reset state when the reset was already completed. Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
* EHCI: fix off-by-one error in ehci_submit_root()Sergei Shtylyov2010-04-08-1/+1
| | | | | | | | | | | USB devices on the 2nd port are not detected and I get the following message: The request port(1) is not configured That's with default CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS value of 2. 'req->index' is 1-based, so the comparison in ehci_submit_root() can't be correct. Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
* EHCI: fix root hub device descriptorSergei Shtylyov2010-04-08-2/+2
| | | | | | | | On little endian machines, EHCI root hub's USB revision is reported as 0.2 -- cpu_to_le16() was missed in the initializer for the 'bcdUSB' descriptor field. The same should be done for the 'bcdDevice' field. Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
* Merge branch 'master' of git://git.denx.de/u-boot-cfi-flashWolfgang Denk2010-04-08-0/+2
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| * cfi_flash: reset timer in flash status checkThomas Chou2010-04-07-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds reset_timer() before the flash status check waiting loop. Since the timer is basically running asynchronous to the cfi code, it is possible to call get_timer(0), then only a few _SYSCLK_ cycles later an interrupt is generated. This causes timeout even though much less time has elapsed. So the timer period registers should be reset before get_timer(0) is called. There is similar usage in nand_base.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2010-04-08-304/+517
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| * | ppc/85xx: Use CONFIG_NS16550_MIN_FUNCTIONS to reduce NAND_SPL sizeKumar Gala2010-04-07-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8536DS_NAND SPL build was failing due to code size increase introduced by commit: commit 33f57bd553edf29dffef5a6c7d76e169c79a6049 Author: Kumar Gala <galak@kernel.crashing.org> Date: Fri Mar 26 15:14:43 2010 -0500 85xx: Fix enabling of L1 cache parity on secondary cores We built in some NS16550 functions that we dont need and can get rid of them via CONFIG_NS16550_MIN_FUNCTIONS. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | p2020ds: add alternate boot bank support using the ngPIXIS FPGATimur Tabi2010-04-07-89/+222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale P2020DS board uses a new type of PIXIS FPGA, called the ngPIXIS. The ngPIXIS has one distinct new feature: the values of the on-board switches can be selectively overridden with shadow registers. This feature is used to boot from a different NOR flash bank, instead of having a register dedicated for this purpose. Because the ngPIXIS is so different from the previous PIXIS, a new file is introduced: ngpixis.c. Also update the P2020DS checkboard() function to use the new macros defined in the header file. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fsl: improve the PIXIS code and fix a few bugsTimur Tabi2010-04-07-170/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx boards. This makes the code easier to read and more flexible. Delete pixis.h, because none of the exported functions were actually being used by any other file. Make all of the functions in pixis.c 'static'. Remove "#include pixis.h" from every file that has it. Remove some unnecessary #includes. Make 'pixis_base' into a macro, so that we don't need to define it in every function. Add "while(1);" loops at the end of functions that reset the board, so that execution doesn't continue while the reset is in progress. Replace in_8/out_8 calls with clrbits_8, setbits_8, or clrsetbits_8, where appropriate. Replace ulong/uint with their spelled-out equivalents. Remove unnecessary typecasts, changing the types of some variables if necessary. Add CONFIG_SYS_PIXIS_VCFGEN0_ENABLE and CONFIG_SYS_PIXIS_VBOOT_ENABLE to make it easier for specific boards to support variations in the PIXIS registers sets. No current boards appears to need this feature. Fix the definition of CONFIG_SYS_PIXIS_VBOOT_MASK for the MPC8610 HPCD. Apparently, "pixis_reset altbank" has never worked on this board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx: Set HID1[mbdd] on e500v2 rev5.0 or greaterSandeep Gopalpet2010-04-07-0/+15
| | | | | | | | | | | | | | | | | | | | | The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize the performance of mbar/eieio instructions. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
| * | 85xx: Added various P1012/P1013/P1021/P1022 definesKumar Gala2010-04-07-6/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list * Added number of LAWs for P1012/P1013/P1021/P1022 * Set CONFIG_MAX_CPUS to 2 for P1021/P1022 * PCI port config Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | ppc/8xxx: Delete PCI nodes from device tree if not configuredKumar Gala2010-04-07-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the PCI controller wasn't configured or enabled delete from the device tree (include its alias). For the case that we didn't even configure u-boot with knowledge of the controller we can use the fact that the pci_controller pointer is NULL to delete the node in the device tree. We determine that a controller was not setup (because of HW config) based on the fact that cfg_addr wasn't setup. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fdt: Add fdt_del_node_and_alias helperKumar Gala2010-04-07-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Add a helper function that given an alias will delete both the node the alias points to and the alias itself Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
| * | 85xx: Add defines for BUCSR bits to make code more readableKumar Gala2010-04-07-5/+10
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fsl-ddr: change the default burst mode for DDR3Dave Liu2010-04-07-4/+10
| | | | | | | | | | | | | | | | | | | | | For 64B cacheline SoC, set the fixed 8-beat burst len, for 32B cacheline SoC, set the On-The-Fly as default. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | fsl-ddr: Fix the turnaround timing for TIMING_CFG_4Dave Liu2010-04-07-9/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and OTF case, BL/2 cycles is enough for fixed BL8. Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 will improve the memory performance. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | fsl_esdhc: Only modify the field we are changing in WMLRoy Zang2010-04-07-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | When we set the read or write watermark in WML we should maintain the rest of the register as is, rather than using some hard coded value. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fsl_esdhc: Add function to reset the eSDHC controllerJerry Huang2010-04-07-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support multiple block read command we must set abort or use auto CMD12. If we booted from eSDHC controller neither of these are used and thus we need to reset the controller to allow multiple block read to function. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fsl_esdhc: Always stop clock before changing frequencyKumar Gala2010-04-07-10/+4
| |/ | | | | | | | | | | | | | | We need to stop the clocks on 83xx/85xx as well as imx. No need to make this code conditional to just imx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefano Babic <sbabic@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2010-04-08-1/+50
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| * | i2c: Move PPC4xx I2C driver into drivers/i2c directoryStefan Roese2010-04-06-1/+50
| |/ | | | | | | | | | | | | | | This patch moves the PPC4xx specific I2C device driver into the I2C drivers directory. All 4xx config headers are updated to include this driver. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-04-08-90/+463
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| * | arm/integrator: Remove unneccessary CONFIG_PCI check.Detlev Zundel2010-04-04-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pci_eth_init() is already conditional to CONFIG_PCI so not every caller needs to have conditionals. This is the only place in the current code base where such a check is still at the calling site. Signed-off-by: Detlev Zundel <dzu@denx.de> CC: Ben Warren <biggerbadderben@gmail.com> CC: Peter Pearse <peter.pearse@arm.com>
| * | at91: use C structs for AT91 OHCI codeMatthias Fuchs2010-04-03-20/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is part of migrating the AT91 support towards using C struct for all SOC access. It removes one more CONFIG_AT91_LEGACY warning. at91_pmc.h needs cleanup after migration of the drivers has been done. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
| * | using AT91_PMC_MCKR_MDIV_ instead of LEGACY one in at91/clock.cAsen Dimov2010-04-03-1/+2
| | | | | | | | | | | | Signed-off-by: Asen Dimov <dimov@ronetix.at>
| * | Nomadik: fix reset_timer()Alessandro Rubini2010-04-03-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous code was failing when reading back the timer less than 400us after resetting it. This lead nand operations to incorrectly timeout any now and then. Moreover, writing the load register isn't immediately reflected in the value register. We must wait for a clock edge, so read_timer now waits for the value to change at least once, otherwise nand operation would timeout anyways (though less frequently). Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
| * | Convert at91 watchdog driver to new SoC accessAchim Ehrlich2010-04-03-10/+11
| | | | | | | | | | | | | | | | | | | | | This converts the at91 watchdog driver to new c structure type to access registers of the SoC Signed-off-by: Achim Ehrlich <aehrlich@taskit.de>
| * | at91: boards cleanup for deprecated CONFIG_CMD_AUTOSCRIPTDaniel Gorsulowski2010-04-03-2/+0
| | | | | | | | | | | | | | | | | | | | | CONFIG_CMD_AUTOSCRIPT support is deprecated and non-existing This clean up patch removes the references for esd boards Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
| * | ep93xx timer: refactoringMatthias Kaehlcke2010-04-03-28/+24
| | | | | | | | | | | | | | | | | | | | | ep93xx timer: Simplified the timer code by eliminating clk_to_systicks() and performing (almost) all manipulation of the timer structure in read_timer() Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
| * | ep93xx timer: Rename struct timer_reg pointersMatthias Kaehlcke2010-04-03-6/+6
| | | | | | | | | | | | | | | | | | | | | ep93xx timer: Renamed pointers to struct timer_regs from name 'timer' to 'timer_regs' in order to avoid confusion with the global variable 'timer' Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
| * | SAMSUNG: SMDKC100: Adds ethernet support.Naveen Krishna CH2010-04-03-1/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add setup for ethernet on SMDKC100, allowing kernel/ramdisk to be loaded over tftp. The preinit function will configure GPIO (GPK0CON) & SROMC to look for environment in SROM Bank 3. Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | S5PC100: Function to configure the SROMC registers.Naveen Krishna CH2010-04-03-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | Nand Flash, Ethernet, other features might need to configure the SROMC registers accordingly. The config_sromc() functions helps with this. Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | S5PC100: Memory SubSystem Header file, register description(SROMC).Naveen Krishna CH2010-04-03-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand, NAND Flash, DDRs. smc.h is a common place for the register description of Memory subsystem of S5PC100. Note: Only SROM related registers are descibed now. Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | s5pc1xx: update the README fileMinkyu Kang2010-04-03-1/+17
| | | | | | | | | | | | | | | | | | Because adds support the GPIO Interface, README file is updated. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | s5pc1xx: support the GPIO interfaceMinkyu Kang2010-04-03-0/+173
| | | | | | | | | | | | | | | | | | This patch adds support the GPIO interface Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | s3c64xx: Add ifdef at the S3C64XX only codesJoonyoung Shim2010-04-03-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The s3c6400.h file is only for S3C64XX cpu and the pheripheral port address(0x70000000 - 0x7fffffff) exists at only S3C64XX cpu, so they should be included by only S3C64XX cpu. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | S5PC100: Moves the Macros to a common header fileNaveen Krishna CH2010-04-03-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The get_pll_clk(int) API returns the PLL frequency based on the (int) argument which is defined locally in clock.c Moving that #define to common header file (clk.h) would be helpful when using the API from other files. Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | MAINTAINERS: sort the list of ARM Maintainers by last nameMinkyu Kang2010-04-03-11/+11
| | | | | | | | | | | | Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | SPEAr : Adding maintainer name for spear SoCsVipin KUMAR2010-04-03-0/+7
| |/ | | | | | | Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
* | nios2: Reload timer count in reset_timer()Scott McNutt2010-04-02-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the timestamp is incremented via interrupt and the interrupt period is greater than 1 msec, successive calls to get_timer() can produce inaccurate timing since the interrupts are asynchronous to the timing loop. For example, with an interrupt period of 10 msec two successive calls to get_timer() could indicate an elapsed time of 10 msec after only several hundred usecs -- depending on when the next interrupt actually occurs. This behavior can cause reliability issues with components such as CFI and NAND. This can be remedied by calling reset_timer() prior to establishing the base timestamp with get_timer(0), provided reset_timer() resets the hardware timer (rather than simply resetting only the timestamp). This has the effect of synchronizing the interrupts (and the advance of the timestamp) with the timing loop. Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | nios2: pass command line and initrd to linux in bootm.cThomas Chou2010-04-02-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds bootargs passing to nios2 linux. The args passing is enabled with, r4 : 'NIOS' magic r5 : pointer to initrd start r6 : pointer to initrd end r7 : pointer to command line Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | nios2: Fix AMDLV065D flash write bug in altera board common tree.Scott McNutt2010-04-02-1/+1
| | | | | | | | Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | nios2: Set CONFIG_SYS_HZ to 1000 all nios2 boards.Scott McNutt2010-04-02-30/+40
| | | | | | | | | | | | | | CONFIG_SYS_HZ was being calculated (incorrectly) in nios2 configuration headers. Updated comments to accurately describe timebase macros. Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | nios2: Fix outx/writex parameter order in io.hScott McNutt2010-04-02-53/+53
| | | | | | | | | | | | | | | | | | The outx/writex macros were using writex(addr, val) rather than the standard writex(val, addr), resulting in incompatibilty with architecture independent components. This change set uses standard parameter order. Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | nios2: Add support for EPCS16 and EPCS64 configuration devices.Scott McNutt2010-04-02-4/+8
| | | | | | | | Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | nios2: Add missing Ethernet initialization to board_init().Scott McNutt2010-04-02-0/+7
| | | | | | | | Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | nios2: add struct stat support in linux/stat.hThomas Chou2010-04-02-1/+1
| | | | | | | | | | | | | | This is needed for jffs2 support. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | nios2: use bitops from linux-2.6 asm-genericThomas Chou2010-04-02-10/+342
| | | | | | | | | | | | | | These are needed to use ubi/ubifs. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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