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* fsl_esdhc: Fix DMA transfer completion waiting loopAndrew Gabbasov2013-04-14-3/+4
| | | | | | | | | | | Rework the waiting for transfer completion loop condition to continue waiting until both Transfer Complete and DMA End interrupts occur. Checking of DLA bit in Present State register looks not needed in addition to interrupts status checking, so it can be removed from the condition. Also, DMA Error condition is added to the list of data errors, checked in the loop. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
* fsl_esdhc: flush cache after IO completionEric Nelson2013-04-14-3/+2
| | | | | | | | | The cache should invalidate the read buffer for the SD card interface after the transfer complete, not command-complete. Tested-by: Andrew Gabbasov <Andrew_Gabbasov@mentor.com> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* spi: mxc_spi: Set master mode for all channelsFabio Estevam2013-04-13-8/+11
| | | | | | | | | | | | | | The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6qsabre{sd, auto}: Fix environment as 'mmc rescan' takes no argumentsOtavio Salvador2013-04-13-1/+1
| | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
* spi: mxc_spi: Fix ECSPI reset handlingDirk Behme2013-04-04-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reviewing the ECSPI reset handling shows two issues: 1. For the enable/reset bit (MXC_CSPICTRL_EN) in the control reg (ECSPIx_CONGREG) the i.MX6 technical reference manual states: -- cut -- ECSPIx_CONREG[0]: EN: Writing zero to this bit disables the block and resets the internal logic with the exception of the ECSPI_CONREG. -- cut -- Note the exception mentioned: The CONREG itself isn't reset. Fix this by manually writing the reset value 0 to the whole register. This sets the EN bit to zero, too (i.e. includes the old ~MXC_CSPICTRL_EN). 2. We want to reset the whole SPI block here. So it makes no sense to first read the old value of the CONREG and write it back, later. This will give us the old (historic/random) value of the CONREG back. And doesn't reset the CONREG. To get a clean CONREG after the reset of the block, too, don't use the old (historic/random) value of the CONREG while doing the reset. And read the clean CONREG after the reset. This was found while working on a SPI boot device where the i.MX6 boot ROM has already initialized the SPI block. The initialization by the boot ROM might be different to what the U-Boot driver wants to configure. I.e. we need a clean reset of SPI block, including the CONREG. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
* i.MX6: mx6qsabrelite: README: don't pass chip-select to sf probe commandJavier Martinez Canillas2013-04-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | board/freescale/mx6qsabrelite/README explain a procedure to update the SPI-NOR on the SabreLite board without Freescale manufacturing tool but following this procedure leads to both "sf erase" and "sf write" failing on a mx6qsabrelite board: MX6QSABRELITE U-Boot > sf probe 1 MX6QSABRELITE U-Boot > sf erase 0 0x40000 SPI flash erase failed MX6QSABRELITE U-Boot > sf write 0x10800000 0 0x40000 SPI flash write failed This is because the chip-select 1 is wrong and the correct value is 0x7300. Since commit c1173bd0 ("sf command: allow default bus and chip selects") the chip-select and bus arguments for the sf probe command are optional so let's just remove it and use "sf probe" instead. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
* wandboard: Remove CONFIG_SYS_FSL_USDHC_NUMFabio Estevam2013-04-03-1/+0
| | | | | | | CONFIG_SYS_FSL_USDHC_NUM is not used for wandboard. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* mx6qsabrelite: Remove duplicate 'mmc dev'Fabio Estevam2013-04-03-1/+0
| | | | | | | No need to call 'mmc dev' twice. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* wandboard: Remove duplicate 'mmc dev'Fabio Estevam2013-04-03-1/+0
| | | | | | | No need to call 'mmc dev' twice. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* mx6: Fix get_board_rev() for the mx6 solo caseFabio Estevam2013-04-03-20/+12
| | | | | | | | | | | | | | | | | | When booting a Freescale kernel 3.0.35 on a Wandboard solo, the get_board_rev() returns 0x62xxx, which is not a value understood by the VPU (Video Processing Unit) library in the kernel and causes the video playback to fail. The expected values for get_board_rev are: 0x63xxx: For mx6quad/dual 0x61xxx: For mx6dual-lite/solo So adjust get_board_rev() accordingly and make it as weak function, so that we do not need to define it in every mx6 board file. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
* mx23_olinuxino: Fix netboot consoleAlexandre Pereira da Silva2013-04-03-1/+1
| | | | | | | | The netargs variable was referencing the non-existing variable console_mainline. Change that to console variable instead. Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a boardAbbas Raza2013-04-03-0/+16
| | | | | | | | | | | | | | | | | | Maximum bus width supported by some i.MX6 boards is not 8bit like others. In case where both host controller and card support 8bit transfers, they agree to communicate on 8bit interface while some boards support only 4bit interface. Due to this reason the mmc 8bit default mode fails on these boards. To rectify this, define maximum bus width supported by these boards (4bit). If max_bus_width is not defined, it is 0 by default and 8bit width support will be enabled in host capabilities otherwise host capabilities are modified accordingly. It is tested with a MMCplus card. Signed-off-by: Abbas Raza <Abbas_Raza@mentor.com> cc: stefano Babic <sbabic@denx.de> cc: Andy Fleming <afleming@gmail.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
* mx23_olinuxino: Change definitions to use spaces instead of tabsOtavio Salvador2013-04-03-80/+80
| | | | | | Change all "#define/ifdef<TAB>" sequences into "#define/ifdef<SPACE>". Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mx25pdk: Enable imxdi RTCBenoît Thébaudeau2013-04-03-0/+4
| | | | | | | | The mx25pdk board supports the i.MX25 DryIce RTC (imxdi), so enable it. This allows to compile-test the imxdi driver in the mainline tree. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6qsabrelite: README: No need to pass 'u-boot.imx'Fabio Estevam2013-04-03-1/+1
| | | | | | | The u-boot.imx binary is generated by default, so no need to pass it in the 'make' line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx28evk: Introduce a new target for saving env vars to NANDFabio Estevam2013-04-03-2/+50
| | | | | | | | | | | | | Introduce 'mx28evk_nand' target for saving environment variables into NAND. The mx28evk board does not come with a NAND flash populated from the factory. It comes with an empty slot (U23), which allows the insertion of a 48-pin TSOP flash device. Tested with a K9LBG08U0D. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
* mx6qsabre{sd,auto}: Add boot mode selectOtavio Salvador2013-04-03-0/+42
| | | | | | | | Adds support for 'bmode' command which let user to choose where to boot from; this allows U-Boot to load system from another storage without messing with jumpers. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mx6qsabresd: Fix card detection for invalid card id caseOtavio Salvador2013-04-03-4/+10
| | | | | | | This changes the code so in case an unkown value is passed it will return as invalid. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mx6qsabresd: Document the mapping of USDHC[2-4]Otavio Salvador2013-04-03-0/+7
| | | | | | | This documents the SD card identifier so it is easier for user to spot which card number will be used, if need. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* Add initial support for Wandboard dual lite and solo.Fabio Estevam2013-03-20-0/+467
| | | | | | | | | Wandboard is a development board that has two variants: one version based on mx6 dual lite and another one based on mx6 solo. For more details about Wandboard, please refer to: http://www.wandboard.org/ Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* i.MX6: mx6qsabrelite: discard override of CONFIG_ARP_TIMEOUTEric Nelson2013-03-20-2/+0
| | | | | | | Nothing on the SABRE Lite board warrants a shorter than normal ARP timeout. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* i.MX6: Add hdmidet command to detect attached HDMI monitorEric Nelson2013-03-20-0/+38
| | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx28evk: Disable CONFIG_CMD_I2CFabio Estevam2013-03-20-1/+0
| | | | | | | | | | | | | | | | When loading a Freescale 2.6.35 on a mx28evk the following issue is seen: sgtl5000_hw_read: read reg error : Reg 0x00 Device with ID register 0 is not a SGTL5000 Disabling CONFIG_CMD_I2C makes the sgtl5000 probe to succeed. Mainline kernel does not show this problem. Until the real cause is not identified, disable 'CONFIG_CMD_I2C' for the time being. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* imx-common: timer: fix 32-bit overflowKnut Wohlrab2013-03-20-19/+7
| | | | | | | | | | | | | | | The i.MX6 common timer uses the 32-bit variable tbl (time base lower) to record the overflow of the 32-bit counter. I.e. if the counter overflows, the variable tbl does overflow, too. To capture this overflow, use the variable tbu (time base upper), too. Return the combined value of tbl and tbu. lastinc is unused then, remove it. Signed-off-by: Knut Wohlrab <knut.wohlrab@de.bosch.com> Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de>
* configs: mx28evk: Use single-line commentsFabio Estevam2013-03-20-45/+15
| | | | | | | No need to use multi-line style comments for single-line contents. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: spl_mem_init: Align DDR2 init with FSL bootlets sourceFabio Estevam2013-03-20-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently the following kernel hang happens when loading a 2.6.35 kernel from Freeescale on a mx28evk board: RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. Bus freq driver module loaded IMX usb wakeup probe usb h1 wakeup device is registered mxs_cpu_init: cpufreq init finished ... Loading the same kernel using the bootlets from the imx-bootlets-src-10.12.01 package, the hang does not occur. Comparing the DDR2 initialization from the bootlets code against the U-boot one, we can notice some mismatches, and after applying the same initialization into U-boot the 2.6.35 kernel can boot normally. Also tested with 'mtest' command, which runs succesfully. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Tested-by: Marek Vasut <marex@denx.de>
* Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-15-1570/+2881
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| * Tegra114: Dalmore: Add pad config tables/code based on pinmux codeTom Warren2013-03-14-14/+292
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, no padcfg entries exist. SDIO3CFG will be added when the MMC driver is added as per the TRM to work with the SD-card slot on Dalmore E1611. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra114: fdt: Move aliases from dtsi to dts file as per other TegrasTom Warren2013-03-14-8/+8
| | | | | | | | | | | | | | All other Tegra boards have their alias nodes in the .dts file Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra114: Dalmore: Always use DEFAULT instead of DISABLE for lock bitsTom Warren2013-03-14-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinmux code issues a warning if the caller attempts to disable the lock bit in a pinmux register, since this is impossible (once it's locked, the only way to unlock it is to reset the device/pmt controller). The I2C/DDC/CEC/USB macros expect a lock setting to be passed in, and the previous setting of DISABLE caused the pinmux table parsing code to issue the warning. Changing the lock bits in these table entries to DEFAULT (i.e. don't touch it) fixes this. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra114: Fix/update GP padcfg register structTom Warren2013-03-14-8/+26
| | | | | | | | | | | | | | Differences in padcfg registers (some removed, some added) between Tegra30 and Tegra114 weren't picked up when I first ported this file. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra114: pinmux: Fix bad CAM_MCLK func 3 table entryTom Warren2013-03-14-1/+1
| | | | | | | | | | | | | | | | This caused CAM_MCLK's pinmux reg to be locked out, since the table parsing code couldn't find a matching entry for VI_ALT3 and wrote garbage to the register. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: enable a common set of disk-related commands everywhereStephen Warren2013-03-14-80/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable a common set of partition types, filesystems, and related commands in tegra-common.h, so that they are available on all Tegra boards. This allows boot.scr (loaded and executed by the default built-in environment) on those boards to assume that certain features are always available. Do this in tegra-common.h, so that individual board files can undefine the features if they really don't want any of them. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * disk: define HAVE_BLOCK_DEVICE if CONFIG_CMD_PARTStephen Warren2013-03-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | Various code that is conditional upon HAVE_BLOCK_DEVICE is required by code conditional upon CONFIG_CMD_PART. So, enable HAVE_BLOCK_DEVICE if CONFIG_CMD_PART is enabled. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * disk: define HAVE_BLOCK_DEVICE in a common placeStephen Warren2013-03-14-40/+15
| | | | | | | | | | | | | | | | | | | | This set of ifdefs is used in a number of places. Move its definition somewhere common so it doesn't have to be repeated. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: make bounce buffer option commonStephen Warren2013-03-14-6/+3
| | | | | | | | | | | | | | | | | | All Tegra devices will need CONFIG_BOUNCE_BUFFER. Move it to tegra-common.h to ensure it's always set. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra30: MMC: Enable DT MMC driver support for Tegra30 Cardhu boardsTom Warren2013-03-14-1/+22
| | | | | | | | | | | | | | | | | | Tested on my Cardhu-A04 tablet, eMMC and SD-Card work fine, can load a kernel off of an SD card OK, card detect works, and the env is now stored in eMMC (end of the 2nd 'boot' sector, same as Tegra20). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra30: mmc: Add Tegra30 SDMMC compatible entry to fdtdec & driverTom Warren2013-03-14-1/+3
| | | | | | | | | | | | | | | | | | Tegra30 SD/MMC controller differs enough from Tegra20 that it needs its own entry in the compat_names/compat_id tables and in the Tegra MMC driver. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * mmc: Tegra: Add SD bus power/voltage function and MMC pad init call.Tom Warren2013-03-14-8/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra30 requires the SD Bus Voltage & Power bits be set in the SD Power Control register. Tegra20 works w/o them set, but do it anyway for those SoCs as it's part of the SD spec. Also call a common board pad init routine (pad_init_mmc) in mmc_reset(), used by Tegra30 only for now. Note that Tegra20 SD/MMC HW differs enough from Tegra20 that a new compatible entry is used in the fdt compat_names/id tables. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra30: MMC: Add SD bus power-rail and SDMMC pad init routinesTom Warren2013-03-14-1/+81
| | | | | | | | | | | | | | T30 requires specific SDMMC pad programming, and bus power-rail bringup. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra: MMC: Added/update SDMMC registers/base addresses for T20/T30Tom Warren2013-03-14-6/+29
| | | | | | | | | | | | | | | | Removed SDMMC base addresses from tegra.h since they're no longer used. Added additional vendor-specific SD/MMC registers and bus power defines. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra30: fdt: Add SDMMC (sdhci) nodes for T30 boards (Cardhu for now)Tom Warren2013-03-14-0/+47
| | | | | | | | | | | | | | Took these values directly from the kernel dts files. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra30: Cardhu: Add pad config tables/code based on pinmux codeTom Warren2013-03-14-5/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, only SDIO1CFG is changed as per the TRM to work with the SD-card slot on Cardhu. Thanks to StephenW for the suggestion/original idea. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra114: pinmux: Update pinmux tables & code, fix a bug w/SDMMC3 initTom Warren2013-03-14-377/+449
| | | | | | | | | | | | | | | | | | | | | | | | | | Use the latest tables & code from our internal U-Boot repo. The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup table were off by a few indices, causing the pinmux init code to write bad data to the PINMUX_AUX_ regs. This also enabled the lock bit, which made it impossible to reconfig the pads correctly for SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N, USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra30: Cardhu: Remove unneeded cardhu.c.mmc fileTom Warren2013-03-14-151/+0
| | | | | | | | | | | | | | | | This was an older debug/developmental file that got added accidentally. Not needed/used in any Cardhu build. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra114: fdt: Sync DT nodes with kernel DT files (GPIO, tegra_car)Tom Warren2013-03-14-1/+18
| | | | | | | | | | | | | | Minor edit to tegra_car node, add gpio node. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra: Remove unused CONFIG_SYS_CPU_OSC_FREQUENCY defineTom Warren2013-03-14-5/+3
| | | | | | | | | | | | | | This wasn't used anywhere in any Tegra build. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra: Add twarren as maintainer for Tegra30 and Tegra114 SoCsTom Warren2013-03-14-0/+2
| | | | | | | | | | Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: implement WAR for Tegra114 CPU reset vectorStephen Warren2013-03-14-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | A Tegra114 HW bug prevents the main CPU vector from being modified under certain circumstances. Tegra114 A01P and later with a patched boot ROM set the CPU reset vector to 0x4003fffc (end of IRAM). This allows placing an arbitrary jump instruction at that location, in order to redirect to the desired reset vector location. Modify Tegra114's start_cpu() to make use of this feature. This allows CPUs with the patched boot ROM to boot. Based-on-work-by: Jimmy Zhang <jimmzhang@nvidia.com>. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra30: fdt: Sync DT nodes with kernel DT files (I2C, SPI, GPIO, clock)Tom Warren2013-03-14-34/+61
| | | | | | | | | | | | | | Minor edits to clock, apbdma and SPI, make I2C match kernel DT, and add gpio Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
generated by cgit v1.1 at 2024-11-09 10:00:17 +0000