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* [Blackfin][PATCH] code cleanupAubrey Li2007-03-12-168/+139
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* [Blackfin][PATCH] code cleanupAubrey Li2007-03-10-551/+518
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* [Blackfin][PATCH-2/2] Common files changed to support bf533 platformAubrey.Li2007-03-09-14/+22
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* [Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform ↵Aubrey.Li2007-03-09-3253/+5182
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* Minor cleanup.Wolfgang Denk2007-03-08-3/+2
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* Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xxWolfgang Denk2007-03-08-2619/+5838
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| * mpc83xx: fix implicit declaration of function 'ft_get_prop' warningsKim Phillips2007-03-02-0/+6
| | | | | | | | (cherry picked from c5bf13b02284c3204a723566a9bab700e5059659 commit)
| * mpc83xx: Fix config of Arbiter, System Priority, and Clock ModeKumar Gala2007-03-02-46/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Were not being used when setting the appropriate register Added: * CFG_SCCR_USBMPHCM * CFG_SCCR_USBDRCM * CFG_SCCR_PCICM * CFG_SCCR_ENCCM To allow full config of the SCCR. Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 that were just bogus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc83xx: update [local-]mac-address properties on UEC based devicesKim Phillips2007-03-02-0/+42
| | | | | | | | | | | | | | 8360 and 832x weren't updating their [local-]mac-address properties. This patch fixes that. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * mpc83xx: write MAC address to mac-address and local-mac-addressTimur Tabi2007-03-02-0/+8
| | | | | | | | | | | | | | | | | | Some device trees have a mac-address property, some have local-mac-address, and some have both. To support all of these device trees, this patch updates ftp_cpu_setup() to write the MAC address to mac-address if it exists. This function already updates local-mac-address. Signed-off-by: Timur Tabi <timur@freescale.com>
| * mpc83xx: add command line editing by defaultKim Phillips2007-03-02-0/+4
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| * mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffersKim Phillips2007-03-02-1/+8
| | | | | | | | | | | | | | | | | | | | Disable G1TXCLK, G2TXCLK h/w buffers. This patch fixes a networking timeout issue with MPC8360EA (Rev.2) PBs. Verified on Rev. 1.1, Rev. 1.2, and Rev. 2.0 boards. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Emilian Medve <Emilian.Medve@freescale.com>
| * mpc83xx: Add DDR2 controller fixed/SPD Init for MPC83xxXie Xiaobo2007-03-02-62/+354
| | | | | | | | | | | | | | The code supply fixed and SPD initialization for MPC83xx DDR2 Controller. it pass DDR/DDR2 compliance tests. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
| * mpc83xx: Add the cpu specific code for MPC8360E rev2.0 MDSXie Xiaobo2007-03-02-4/+33
| | | | | | | | | | | | | | MPC8360E rev2.0 have new spridr,and PVR value, The MDS board for MPC8360E rev2.0 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
| * mpc83xx: Add the cpu and board specific code for MPC8349E rev3.1 MDSXie Xiaobo2007-03-02-13/+61
| | | | | | | | | | | | | | MPC8349E rev3.1 have new spridr,and PVR value, The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>
| * mpc83xx: Fix empty i2c reads/writes in fsl_i2c.cJoakim Tjernlund2007-03-02-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix empty i2c reads/writes, i2c_write(0x50, 0x00, 0, NULL, 0) which is used to se if an slave will ACK after receiving its address. Correct i2c probing to use this method as the old method could upset a slave as it wrote a data byte to it. Add a small delay in i2c_init() to let the controller shutdown any ongoing I2C activity. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
| * mpc83xx: Add support for the MPC8349E-mITX-GPTimur Tabi2007-03-02-288/+447
| | | | | | | | | | | | | | | | Add support for the MPC8349E-mITX-GP, a stripped-down version of the MPC8349E-mITX. Bonus features include support for low-boot (BMS bit in HRCW is 0) for the ITX and a README for the ITX and the ITX-GP. Signed-off-by: Timur Tabi <timur@freescale.com>
| * mpc83xx: Delete sdram_init() for MPC8349E-mITXTimur Tabi2007-03-02-87/+1
| | | | | | | | | | | | | | There is no SDRAM on any of the 8349 ITX variants, so function sdram_init() never does anything. This patch deletes it. Signed-off-by: Timur Tabi <timur@freescale.com>
| * mpc83xx: Fix the LAW1/3 bugDave Liu2007-03-02-3/+3
| | | | | | | | | | | | | | | | | | | | | | The patch solves the alignment problem of the local bus access windows to render accessible the memory bank and PHY registers of UPC 1 (starting at 0xf801 0000). What we actually did was to adjust the sizes of the bus access windows so that the base address alignment requirement would be met. Signed-off-by: Chereji Marian <marian.chereji@freescale.com> Signed-off-by: Gridish Shlomi <gridish@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
| * mpc83xx: don't hang if watchdog configured on 8360, 832xKim Phillips2007-03-02-4/+0
| | | | | | | | | | | | | | don't hang if watchdog configured on 8360, 832x The watchdog programming model is the same across all 83xx devices; make the code reflect that.
| * mpc83xx: protect memcpy to bad address if a local-mac-address is missing from dtKim Phillips2007-03-02-0/+2
| | | | | | | | protect memcpy to bad address if a local-mac-address is missing from dt
| * mpc83xx: make 8360 default environment fdt be 8360 (not 8349)Kim Phillips2007-03-02-1/+1
| | | | | | | | make 8360 default environment fdt be 8360 (not 8349)
| * mpc83xx: Fix alternating tx error / tx buffer not ready bug in QE UECEmilian Medve2007-03-02-1/+1
| | | | | | | | | | | | | | | | The problem is not gcc4 but the code itself. The BD_STATUS() macro can't be used for busy-waiting since it strips the 'volatile' property from the bd variable. gcc3 was working by pure luck. This is a follow on patch to "Fix the UEC driver bug of QE"
| * mpc83xx: Replace CONFIG_MPC8349 and use CONFIG_MPC834X insteadKumar Gala2007-03-02-15/+15
| | | | | | | | | | | | | | | | The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all MPC834X class processors. Change the protections from CONFIG_MPC8349 to CONFIG_MPC834X so they are more generic. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc83xx: add MPC832XEMDS and sbc8349 to MAKEALLKim Phillips2007-03-02-1/+2
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| * mpc83xx: sort Makefile targetsKim Phillips2007-03-02-19/+20
| | | | | | | | reordered targets alphabetically
| * mpc83xx: U-Boot support for Wind River SBC8349Paul Gortmaker2007-03-02-0/+2077
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I've redone the SBC8349 support to match git-current, which incorporates all the MPC834x updates from Freescale since the 1.1.6 release, including the DDR changes. I've kept all the SBC8349 files as parallel as possible to the MPC8349EMDS ones for ease of maintenance and to allow for easy inspection of what was changed to support this board. Hence the SBC8349 U-Boot has FDT support and everything else that the MPC8349EMDS has. Fortunately the Freescale updates added support for boards using CS0, but I had to change spd_sdram.c to allow for board specific settings for the sdram_clk_cntl (it is/was hard coded to zero, and that remains the default if the board doesn't specify a value.) Hopefully this should be mergeable as-is and require no whitespace cleanups or similar, but if something doesn't measure up then let me know and I'll fix it. Thanks, Paul.
| * mpc83xx: Remove a redundant semicolon in mpc8349itx.cSam Song2007-03-02-1/+1
| | | | | | | | | | | | | | A redundant semicolon existed in mpc8349itx.c should be removed. Signed-off-by: Sam Song <samsongshu@yahoo.com.cn>
| * mpc83xx: Put the version (and magic) after the HRCW.Jerry Van Baren2007-03-02-12/+16
| | | | | | | | | | | | | | Put the version (and magic) after the HRCW. This puts it in a fixed location in flash, not at the start of flash but as close as we can get. Signed-off-by: Jerry Van Baren <vanbaren@cideas.com>
| * mpc83xx: Add the MPC832XEMDS board readmeDave Liu2007-03-02-0/+129
| | | | | | | | | | | | Add the MPC832XEMDS board readme Signed-off-by: Dave Liu <daveliu@freescale.com>
| * mpc83xx: Add support for the MPC832XEMDS boardDave Liu2007-03-02-32/+1488
| | | | | | | | | | | | This patch supports DUART, ETH3/4 and PCI etc. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * mpc83xx: streamline the 83xx immr head fileDave Liu2007-03-02-2061/+1122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For better format and style, I streamlined the 83xx head files, including immap_83xx.h and mpc83xx.h. In the old head files, 1) duplicated macro definition appear in the both files; 2) the structure of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The macro definition put inside the each structure. So, I cleaned up the structure of QE immr from immap_83xx.h, deleted the duplicated stuff and moved the macro definition to mpc83xx.h, Just like MPC8260. CHANGELOG *streamline the 83xx immr head file Signed-off-by: Dave Liu <daveliu@freescale.com>
| * mpc83xx: Fix the UEC driver bug of QEDave Liu2007-03-02-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch prevents the GCC tool chain from striping useful code for optimization. It will make UEC ethernet driver workable, Otherwise the UEC will fail in tx when you are using gcc4.x. but the driver can work when using gcc3.4.3. CHANGELOG *Prevent the GCC from striping code for optimization, Otherwise the UEC will tx failed when you are using gcc4.x. Signed-off-by: Dave Liu <daveliu@freescale.com>
* | Minor cleanupWolfgang Denk2007-03-08-1/+178
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* | Merge with /home/hs/jupiter/u-bootWolfgang Denk2007-03-08-6/+821
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| * | [PATCH] Added support for the jupiter board.Heiko Schocher2007-02-16-0/+815
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-08-644/+171
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| * \ \ Merge with /home/stefan/git/u-boot/yucca-ddr2Stefan Roese2007-03-08-644/+171
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| | * | | [PATCH] Update AMCC Luan 440SP eval board supportStefan Roese2007-03-08-240/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | [PATCH] Update AMCC Yucca 440SPe eval board supportStefan Roese2007-03-08-378/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | ppc4xx: Small AMCC Katmai 440SPe updateStefan Roese2007-03-08-0/+11
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | ppc4xx: Update 440SP/440SPe DDR SPD setup code to support 440SPStefan Roese2007-03-08-26/+63
| | | |/ | | |/| | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-07-68/+48
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| * | | [PATCH] Use dynamic SDRAM TLB setup on AMCC Ocotea eval boardStefan Roese2007-03-07-64/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the DDR memory are dynamically programmed matching the total size of the equipped memory (DIMM modules). Signed-off-by: Stefan Roese <sr@denx.de>
| * | | [PATCH] Fix AMCC 44x SPD SDRAM init code to support 2 DIMM'sStefan Roese2007-03-07-4/+27
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a problem that occurs when 2 DIMM's are used. This problem was first spotted and fixed by Gerald Jackson <gerald.jackson@reaonixsecurity.com> but this patch fixes the problem in a little more clever way. This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. As this feature is new to the "old" 44x SPD DDR driver, it has to be enabled via the CONFIG_PROG_SDRAM_TLB define. Signed-off-by: Stefan Roese <sr@denx.de>
* | | UC101: fix compiler warningsWolfgang Denk2007-03-07-9/+9
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* | | HMI1001: fix build error, cleanup compiler warnings.Wolfgang Denk2007-03-07-9/+10
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* | | Restructure POST directory to support of other CPUs, boards, etc.Wolfgang Denk2007-03-06-45/+7719
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* | | Fix HOSTARCH handling.Wolfgang Denk2007-03-06-5/+1
| | | | | | | | | | | | Patch by Mike Frysinger, Mar 05 2007
* | | [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setupStefan Roese2007-03-06-17/+26
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-10-30 18:43:38 +0000