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* MLK-9735 new config for 19x19 ARM2 board NAND bootAllen Xu2014-10-23-0/+1
| | | | | | supported NAND boot on 19x19 ARM2 board. Signed-off-by: Allen Xu <b45815@freescale.com>
* MLK-9714 imx: imximage tool: Fixed the bootdata.size calculationYe.Li2014-10-22-1/+1
| | | | | | | | The bootdata.size should contain the IVT offset part, but the calculation for bootdata.size in imximage tool does not. This will cause some data at the end of image not be loaded into memory. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9706 imx: mx6sx19x19arm2: Fix ENET card MAX7322 reset issueYe.Li2014-10-20-5/+5
| | | | | | | | | | | The MAX7322 will fail to work on 19x19 arm2 revB board. This failure is caused by the MAX7322 reset pin is not released when calling the setup_fec function. The MAX7322 reset pin is same as PHY reset pin. This patch fixes the issue by moving the PHY reset from setup_iomux_fec1 to setup_fec. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9705 imx: mx6sxsabreauto: add MAX7310 support to reset peripheralsYe.Li2014-10-20-0/+46
| | | | | | | | | The MAX7310 uses I2C3 bus. At system initialization, enable the driver to: 1. Reset CPU_PER_RST_B signal 2. Set the steering for ENET 3. Enable the LVDS display Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9705 imx: mx6sx: Set the pad setting SION for I2C3 pinsYe.Li2014-10-20-2/+2
| | | | | | When set the pinmux to I2C functionality, the SION is required to enabled. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9676 imx: mx6sx 19x19arm2: Fix ethernet phy reset issueYe.Li2014-10-11-2/+2
| | | | | | | The PHY reset on 19x19 arm2 board is GPIO6_18, not GPIO4_22. This causes the ethernet phy failed to work. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9652 Android: imx6sxsabreauto: Add android features supportYe.Li2014-10-09-0/+170
| | | | | | Add android fastboot, recovery and booti support for mx6sx sabreauto board. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9668 imx: mx6sxsabreauto: Fix bmode valueYe.Li2014-10-09-3/+3
| | | | | | Set the correct bmode value for booting from SDA/SDB/QSPI1/NAND Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9665-2 mx6sx: define CONFIG_SPI_FLASH_BARPeng Fan2014-10-09-0/+3
| | | | | | | | | | | | define CONFIG_SPI_FLASH_BAR in mx6sx_arm2.h mx6sxsabreauto.h to enable access to flash array higher than 16MB. CONFIG_SPI_FLASH_BAR is also set in mx6sxsabresd.h for RevB board. Actually, if QSPI flash size <= 16MB, setting CONFIG_SPI_FLASH_BAR has not effect. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-9665-1 QuadSPI: Support flash bigger than 16MBPeng Fan2014-10-09-1/+50
| | | | | | | | | | | | By introducing CONFIG_SPI_FLASH_BAR and add related command in LUT to enable fsl_qspi.c can handle flash size bigger that 16M. Because uboot does not support 32bits address access, this means bank address should be used to access bigger flash. It is hard to let qspi driver dynamically set LUT, so BRRD BRWR RDEAR and WREAR are all supported. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-9636 QuadSPI: add 4k erase supportPeng Fan2014-10-08-1/+13
| | | | | | | | OPCODE_BE_4K is supported. To qspi flashes which support 4k sector erase, spi framework will use OPCODE_BE_4K command. Thus add this support to let uboot can erase such qspi flashes. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-9640 ARM: imx6sx: enable ldo-bypass on mx6sxsabresd boardRobin Gong2014-09-30-16/+109
| | | | | | enable ldo-bypass check on all mx6sxsabresd boards. Signed-off-by: Robin Gong <b38343@freescale.com>
* MLK-9646 imx: mx6sxsabreauto: Change DDR size to 2GYe.Li2014-09-29-1/+1
| | | | | | | | The mx6sx sabreauto boards uses 2G DDR3. Modify the configuration PHYS_SDRAM_SIZE to this size. Signed-off-by: Ye.Li <B37916@freescale.com> Acked-by: Jason Liu
* ENGR00333317 imx: mx6sxsabreauto: Add BSP support for AI boardYe.Li2014-09-26-0/+1589
| | | | | | | | | | | | | | | | Create mx6sx sabreauto BSP file and configurations. The devices below have been supported: 1. SD/MMC/eMMC on SDA/SDB (base board) sockets 2. USB OTG port and USB HOST port (base board) 3. NAND flash 4. QuadSPI flash on QSPI1 5. I2C 6. PMIC PFUZE100 7. Onboard ethernet chip on ENET2 8. Splash screen on LVDS Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00333299: Add support for i.MX6SX 14x14 lpddr2 arm2 boardNitin Garg2014-09-25-0/+302
| | | | | | | Add support for i.MX6SX 14x14 lpddr2 arm2 board, same as 17x17 arm2 except lpddr2 instead of ddr3. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* sf: probe: Fix quad bit set pathPoddar, Sourav2014-09-25-10/+10
| | | | | | | | | | Currently, flash quad bit is set in "spi_flash_validate_params" and later at the end in the same api, we write 0 to status register for few flashes, thereby overriding the quad bit set. This fix moves the quad bit setting outside this api in "spi_flash_probe_slave" Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* ENGR00332535 imx: mx6sx: Remove WEIM plugin work around for TO 1.2 and higherYe.Li2014-09-23-1/+7
| | | | | | | | ROM fixes the WEIM plugin issue in TO 1.2. The work around for hacking WEIM base address to ROM variable is not needed. To avoid hacking useful data, remove the work around for TO 1.2 and higher revisions. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331269 arm: mx6: select OSC as uart's clk parentAnson Huang2014-09-18-0/+9
| | | | | | | | As M4 is sourcing UART clk from OSC, to make UART work when M4 is enabled, need to select OSC as clk parent, 24M OSC is enough for debug UART in uboot. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00331706-5 imx: mx6: Enable 24Mhz OSC for GPTYe.Li2014-09-18-0/+1
| | | | | | | Set the CONFIG_MXC_GPT_HCLK configuration in mx6_common.h, so that enable the 24Mhz OSC GPT on all MX6 platforms. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331706-4 imx: mx6sl: Set the preclk clock source to OSC 24MhzYe.Li2014-09-18-0/+16
| | | | | | | For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the preclk setting with kernel. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331706-3 imx: mx6: Change the get_ipg_per_clk for OSC 24Mhz sourceYe.Li2014-09-18-0/+4
| | | | | | | For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix the get_ipg_per_clk function to support it. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331706-2 imx: mx6sl: Add perclk_clk_sel bit define in CCMYe.Li2014-09-18-0/+2
| | | | | | | The MX6SL has the perclk_clk_sel to select the perclk source. Add its define in CCM Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331706-1 imx: gpt: Add 24Mhz OSC clock source support for GPTYe.Li2014-09-18-10/+66
| | | | | | | | | | | | | | | | Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set, the GPT will use 24Mhz OSC as clock source. Otherwise, the GPT will use 32Khz OSC as clock source. Since only the GPT on iMX6 series provide the clock source option for 24Mhz OSC. For other series(MX5), if the configuration is set, the perclk will be selected as clock source. MX6Q/D Rev 1.0 and MX6SL can't use the 24Mhz OSC clock source option, so select the perclk for them. For MX6SL, we will set the OSC 24Mhz to perclk in CCM, so eventually the clock comes from OSC 24Mhz. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00327364 iMX6: Ensure that the bandgap self-bias circuit is disabled ↵Ranjani Vaidyanathan2014-09-10-0/+24
| | | | | | | | | | | | after boot. The self-bias circuit is used by the bandgap during startup. Once the bandgap has stabilized, the self-bias circuit should be disabled for best noise performance of analog blocks. Also this bit should be disabled before the chip enters STOP mode or when ever the regular bandgap is disabled. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00330792 imx: mx6: Merge anatop registers to CCM structureYe.Li2014-09-10-216/+160
| | | | | | | | | | THe anatop registers structure is duplicated with CCM structure at PLL fields. Since we are suggested not to use the name "anatop" any longer, merge the anatop registers to the CCM structure "mxc_ccm_reg" and use CCM to replace anatop. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00329484-2 ARM:MX6: Clear Align bit in SCTLRPeng Fan2014-09-05-0/+3
| | | | | | | | | | This problem is found when debugging QuadSPI. When "A" bit is enabled, unaligned access will cause data abort exception. Actually, we do not want this exception. So clear the align bit for MX6 SOCs. Tested this code with android team colleague and did not find problem. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00329484-1 QuadSPI:Unaligned access crash ubootPeng Fan2014-09-05-5/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To fsl_qspi_write_data and fsl_qspi_ip_read, pointer txbuf and rxbuf are not guaranteed that they are 4 Bytes aligned. Also, it it not a good idea to cast type 'u8 *' to 'u32 *', except we are sure that pointer type 'u8 *' is 4 Bytes aligned and cast it to 'u32 *' will not pass memory boundary. The problem is found when using fsl_qspi_write_data to write registers in flash devices. The err msg: data abort pc : [<87822f44>] lr : [<87822f38>] sp : bf5512c8 ip : 0000001c fp : bf856608 r10: 87868904 r9 : bf551efc r8 : 200f048c r7 : 00000002 r6 : bf551336 r5 : bf552a70 r4 : 00000001 r3 : 00000000 r2 : 00000060 r1 : 8783b520 r0 : 8783b520 Flags: nZCv IRQs on FIQs off Mode SVC_32 Resetting CPU ... The asm code which cause data abort is: 87822f30: e5964000 ldr r4, [r6] From the dump msg, r6 is not 4 Bytes aligned, and data abort exception. So, Use mempcy but not unsafe type casting. In this patch, max_write_size is assigned using txfifo to avoid possible errors in future. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00328278-1: Fix i.MX6DQ/DL arm2 LPDDR2 boards mem sizeNitin Garg2014-09-04-11/+11
| | | | | | | Couple of issues in commit 21a2eb5f. The RAM size is wrong and max number of DCD is 220. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00323255 Fixed QSPI randomly access timeout issueAllen Xu2014-08-29-16/+22
| | | | | | | | | | | | | | | | The QSPI clock rate was set without disabling the clock gate, the randomly glitch may mess up the clock and there will be no clock output, when kernel boot up the QSPI access will fail. To debug this issueon i.MX6SX SDB, changed the u-boot bootscript to 'sf probe; reset' to keep rebooting, the issue can be reproduced in 20 mins, set clock out register in CCM and measured TP86, found there is no clock ouput. To fix this bug, disable clock gate before changing clock rate. NOTICE: QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, need to disable both of them. Signed-off-by: Allen Xu <b45815@freescale.com>
* ENGR00329631: imx6: fix kernel suspend reboot if keep watchdog aliveRobin Gong2014-09-02-0/+5
| | | | | | | WDZST bit is write-once only bit. So we need take care the setting in kernel ,otherwise, kernel setting will never be enabled. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00328278: Add support for i.MX6DQ/DL arm2 LPDDR2 boardsNitin Garg2014-08-28-8/+989
| | | | | | Add support for i.MX6DQ/DL arm2 LPDDR2 boards. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00326277-2 imx6: watchdog: use WDOG_B mode for wdog reset in ldo-bypass modeRobin Gong2014-08-26-7/+28
| | | | | | In ldo-bypass mode, we need trigger WDOG_B pin to reset pmic in ldo-bypass mode. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00326277-1: imx6: ldo_bypass: fix VDDARM voltage setting violate datasheetRobin Gong2014-08-26-11/+145
| | | | | | | | | Current only set VDDARM_IN@1.175V/VDDSOC_IN@1.175V before ldo bypass switch. So untile ldo bypass switch happened, these voltage setting is set in ldo-enable mode. But in datasheet, we need 1.15V + 125mV = 1.275V for VDDARM_IN. We need to downgrade cpufreq to 400Mhz and restore after ldo bypass mode switch. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00328312 i2c: imx: Optimize the i2c device recovery solutionFugang Duan2014-08-25-2/+25
| | | | | | | | | | | | | | | From i2c spec, if device pull down the SDA line that causes i2c bus dead, host can send out 9 clock to let device release SDA. But for some special device like pfuze100, it pull down SDA line and the solution cannot take effort. The patch just add NACK and STOP signal after 8 dummy clock, and pmic can release SDA line after the recovery. Test case catch 375 times of i2c hang, and all are recovered. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00326994 iMX6: Checking PLL2 PFD0 and PFD2 for periph_clk before resetYe.Li2014-08-15-7/+16
| | | | | | | | | | | | | u-boot v2014 upstream codes have a problem in pfd reset (s_init function) that imx6 Dual is not applied for PLL2 PFD2 reset. It is originated by using dynamical cpu type checking and introducing two cpu types: MXC_CPU_MX6Q and MXC_CPU_MX6D for iMX6 Dual/Quad platform. Fixed this problem by checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source, do not reset this PFD to avoid system hang. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00326448: mx6slevk: I2C: correct scl/sda defineRobin Gong2014-08-08-2/+2
| | | | | | | Correct the wrong setting, otherwise, i2c recovery code will use the wrong scl pin to recove, and will never recovery successfully. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00325634 iMX6DQ{DL}:SABRESD Fixed bmode booting failure for eMMCYe.Li2014-08-07-1/+1
| | | | | | | The BOOTCFG value used by bmode for SABRESD eMMC are actually for SD card. Fixed the value to correct one. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00326213 iMX6SX:19x19ARM2: Update LPDDR2 settingsYe.Li2014-08-07-34/+37
| | | | | | | | | | HWApps team updates iMX6SX 19x19 validation board LPDDR2 script. This script is JEDEC compliant. http://compass.freescale.net/livelink/livelink/open/232537085 Update the LPDDR2 settings in DCD and plugin. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00325088 video: mxsfb: Disable LCDIF correctlyLiu Ying2014-08-04-5/+9
| | | | | | | | | | | | | | | | | Let's use the i.MX common miscellaneous reset API to reset the LCDIF block so that we may eliminate a random hang issue at the arch_preboot_os() stage when we disable the LCDIF. This patch also waits for a VSYNC interrupt to guarantee the reset is done at the VSYNC edge, which somehow makes the LCDIF consume the display FIFO(?) and helps the LCDIF work normally at the kernel stage. Tested-by: Jason Liu <r64343@freescale.com> Tested-by: Sandor Yu <R01008@freescale.com> Tested-by: Ye.Li <B37916@freescale.com> Tested-by: Guo Sally <b38912@freescale.com> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00325255 pcie:enable pcie support on imx6sx sdRichard Zhu2014-07-31-14/+190
| | | | | | | | | | | | | | Enable pcie support in uboot on imx6sx sd boards - enable_pcie_clock should be call before ssp_en is set, since that ssp_en control the phy_ref clk gate, turn on it after the source of the pcie clks are stable. - add debug info - add rx_eq of gpr12 on imx6sx - there are random link down issue on imx6sx. It's pcie ep reset issue. solution:reset ep, then retry link can fix it. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00324352 Set console value to show log info for mfgtool nand downloadAllen Xu2014-07-24-0/+1
| | | | | | set console value to show download log info for mfgtool NAND download. Signed-off-by: Allen Xu <b45815@freescale.com>
* ENGR00323465: iMX6SX ARM2: modified NAND boot rootfs mtd partition numAllen Xu2014-07-14-1/+1
| | | | | | | | Since QSPI will be disabled for NAND module(pin conflict), the mtd partition number will be count from 0, the last partition for rootfs need to be changed from 4 to 3. Signed-off-by: Allen Xu <b45815@freescale.com>
* ENGR00323143 pcie:can't be enabled in both uboot and kernelRichard Zhu2014-07-17-1/+12
| | | | | | | | | | | | | | imx6 q/dl/solo pcie would be failed to work properly in kernel, if the pcie module is iniialized/enumerated both in uboot and linux kernel. rootcause:imx6 q/dl/solo pcie don't have the reset mechanism. it is only be RESET by the POR. So, the pcie module only be initialized/enumerated once in one POR. Set to use pcie in kernel defaultly, mask the pcie config here. Remove the mask freely, if the uboot pcie functions, rather than the kernel's, are required. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00322796 iMX6SXSABRESD: Enable Micron N25Q128 flash support for RevB boardYe.Li2014-07-17-0/+1
| | | | | | | | | The iMX6SX SABRESD RevB board uses Micron N25Q128 to replace Spansion S25FL128 on RevA board. So enable the CONFIG_SPI_FLASH_STMICRO and CONFIG_SPI_FLASH_SPANSION to support both two revisions. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00322860 iMX6SX: Add function to check M4 status before bootingYe.Li2014-07-17-1/+31
| | | | | | | Add new function "arch_auxiliary_core_check_up" to check whether M4 is already up. Therefore, avoid starting M4 again when it is running. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00321435-2 video: mxc gis: do not disable mxsfbLiu Ying2014-07-17-2/+0
| | | | | | | The mxc gis driver should not disable mxsfb, instead, mxsfb could be disabled in machine layer. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00321435-1 imx-common: cpu: Disable mxsfb when necessaryLiu Ying2014-07-17-0/+4
| | | | | | | | The kernel may break the display pipeline at boot stage and introduce various display artifacts, so let's disable mxsfb in uboot when necessary. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* MX6: Correct calculation of PLL_SYSAndre Renaud2014-07-15-1/+1
| | | | | | | | DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do the shift after the multiply to avoid rounding errors Signed-off-by: Andre Renaud <andre@bluewatersys.com> (cherry picked from commit 2eb268f6fd236a5ad9d51e7e47190d7994b3920f)
* mx6: soc: Update the comments of set_ldo_voltage()Fabio Estevam2014-07-15-3/+2
| | | | | | | | | | | | | | | Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces set_ldo_voltage() function that can be used to set the voltages of any of the three LDO regulators controlled by the PMU_REG_CORE register. Prior to this commit there was a single set_vddsoc() which only configured the VDDSOC regulator. Update the comments to align with the new set_ldo_voltage() implementation. Acked-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> (cherry picked from commit 157f45da91b306d71dbf3a51325352dc11bf16d1)
* ENGR00321146 gis: faster auto standards detectionSandor Yu2014-07-11-1/+1
| | | | | | | | | | | | | | | | | Vadc need long time to auto standards detection, the default standard is NTSC, if vadc connect to PAL camera and no enough time to detect the video mode, driver will get wrong standard. Confirmation from chip design architecture that auto detect function is not required by rear-view camera application. Setting register vdec_stddbg standard_filte bits to 0 makes the standard detection faster, the issue duplicate decrease to 1%. Signed-off-by: Sandor Yu <R01008@freescale.com> (cherry picked from commit 06735bf6724f2dad2dcbbfc188c6a17145c7126b)
generated by cgit v1.1 at 2024-07-02 22:16:37 +0000