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* MX31: change return value of get_cpu_revStefano Babic2011-05-11-14/+19
| | | | | | | | | | Drop warnings in get_cpu_rev and changes the return value (a u32 instead of char * is returned) of the function to be coherent with other processors. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Detlev Zundel <dzu@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
* MX31: removed warning due to missing prototypeStefano Babic2011-05-11-0/+1
| | | | | | | Drop warning caused by missing prototype for mxc_hw_watchdog_reset(). Signed-off-by: Stefano Babic <sbabic@denx.de>
* gpio: imx: Fix return value on errorFabio Estevam2011-05-11-2/+3
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX31: mx31pdk: Add watchdog supportFabio Estevam2011-05-11-0/+19
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* da850evm: fix NAND WSTROBE and TA timingsBen Gardiner2011-05-11-2/+2
| | | | | | | | | | | | | | | | The current NAND timings, introduced in commit a3f88293ddd13facd734769c1664d35ab4ed681f da850evm: setup the NAND flash timings , incorrectly set WSTROBE and TA to 0. A more recent inspection of the values set by the Linux kernel indicates that these should be set to 1. Set the WSTROBE and TA field of the EMIFA cycle-count timings configuration to 1 to match the values set by linux. Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> CC: Stefano Babic <sbabic@denx.de> CC: Sandeep Paulraj <s-paulraj@ti.com> CC: Scott Wood <scottwood@freescale.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* keymile boards: move keymile specific header in subdirValentin Longchamp2011-05-10-14/+14
| | | | | | | | | | | | Collect all keymile specific common headers in include/configs/km. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Kim Phillips <kim.phillips@freescale.com> cc: Holger Brunck <holger.brunck@keymile.com>
* km/common: fix coding style issues in generic headerHolger Brunck2011-05-10-7/+7
| | | | | | | | | Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* km/common: implement setboardid commandHolger Brunck2011-05-10-0/+34
| | | | | | | | | | | Read out board id and HW key from the IVM eeprom and set these values as an environment variable. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com>
* common/hush: make get_local_var visible for other usersHolger Brunck2011-05-10-2/+2
| | | | | | | | | Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* km/common: fix initial_boot_bank for bootpackagesThomas Herzmann2011-05-10-7/+8
| | | | | | | | | | | | | | The initial_boot_bank can be set when more than one application is used in a bootpackage. But a value n <> 0 never led to booting from bank n. Instead, bank 0 was booted. This patch fixes this. Signed-off-by: Thomas Herzmann <thomas.herzmann@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* powerpc/km82xx: fix compile issue for mgcoge2neHolger Brunck2011-05-10-0/+3
| | | | | | | | | | commit 91a3c14c (ppc, mgcoge: add DIP switch detection) introduces an compile error due to an missing define in the mgcoge2ne.h. DIP switch detection is valid for both boards. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Wolfgang Denk <wd@denx.de> cc: Heiko Schocher <hs@denx.de>
* poweprc/km82xx: add board specific environment variableHolger Brunck2011-05-10-0/+5
| | | | | | | | | | | | | | On mgcoge3ne a new environment variable bobcatreset is used. So this patch adds a possibility to add board specific environment variables in general and this specific variable for mgcoge3ne. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* powerpc/km82xx: adapt CONFIG_SYSSYPCR to manualHolger Brunck2011-05-10-1/+1
| | | | | | | | | | | Reserved bit was changed according to the processors manual. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* powerpc/km82xx: add mgcoge3ne and remove mgcoge2ne supportHolger Brunck2011-05-10-42/+96
| | | | | | | | | | | | | | | | | This patch adds support for the MPC8247 based board mgcoge3ne. Additionaly mgcoge2ne board supprot was removed, because due to the mgcoge3ne, this board is obsolete and not longer maintained. The board is similar to mgcoge. The difference is that a NUMONYX flash is used and a different SDRAM (256MB). Also introduce CONFIG_KM_82XX to collect ppc82xx common settings and remove staticness from the common set_pin function. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de>
* powerpc/km82xx: rework DIP switch detectionHuber, Andreas2011-05-10-9/+84
| | | | | | | | | | | | | Introduce a struct for the BFTICU FPGA to increase the readability of the code. And the define CONFIG_SYS_BFTICU_BASE was removed because the CONFIG_SYS_FPGA_BASE is already the base value for BFTICU registers. Signed-off-by: Andreas Huber <andreas.huber@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de>
* powerpc/km82xx: rename mgcoge files to km82xxHolger Brunck2011-05-10-2/+2
| | | | | | | | | | | | | The directory and file mgcoge was renamed to km82xx. Because other keymile 82xx will follow and will use the same platform code. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* powerpc/km82xx: cleanup coding style for mgcoge.cHolger Brunck2011-05-10-148/+149
| | | | | | | | | Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* km/common: remove hdlc_enet implementationHolger Brunck2011-05-10-905/+1
| | | | | | | | | | | | | The hdlc implementation for mgcoge was initially developed, but later on not used. Remove the C files, the references in mgcoge.c and the Makefile to decrease maintenance effort. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* cramfs: make cramfs usable without a NOR flashHeiko Schocher2011-05-10-2/+12
| | | | | | | | cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* cramfs: fix bug in using CONFIG_CRAMFS_CMDLINEHeiko Schocher2011-05-10-1/+1
| | | | | | | | | | | | do not define own flash_info variable, instead use the flash_info variable defined in your flash driver. Signed-off-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsWolfgang Denk2011-05-10-248/+135
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| * MIPS: Move timer code to arch/mips/cpu/$(CPU)/Shinya Kuribayashi2011-05-10-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Current timer routines (arch/mips/lib/timer.c) are implemented assuming that MIPS32 coprocessor (CP0) resources, Counter and Compare registers in this case, are available. But this doesn't always work. We need to make sure that all MIPS-based systems don't necessarily use CP0 counter/compare registers as time keeping resources. And some MIPS variant processors might come with different hardware specs with genuine MIPS32 CP0 registers. With this change, each $(CPU)/ directory can have its own timer code. Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
| * MIPS: Introduce --gc-sections for MIPSDaniel Schwierzeck2011-05-10-40/+42
| | | | | | | | | | | | | | | | | | | | | | | | All architectures but MIPS are using --gc-sections on final linking. This patch introduces that feature for MIPS to reduce the memory and flash footprint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Thomas Lange <thomas@corelatus.se> Cc: Vlad Lungu <vlad.lungu@windriver.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
| * MIPS: Coding style cleanups on common assembly filesShinya Kuribayashi2011-05-07-107/+93
| | | | | | | | | | | | | | | | | | | | Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
| * MIPS: Remove mips_cache_lock() featureShinya Kuribayashi2011-05-07-100/+0
| | | | | | | | | | | | | | | | | | As requested in commit e1390801a3c1a2b6d12fa90be368efc19f5b9bfd ([MIPS] Request for the 'mips_cache_lock()' removal), such feature is no longer needed for current MIPS implementation of U-Boot, and no one in the tree uses it for years. Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2011-05-10-3/+1
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| * mpc83xx: restrict UTMI PHY configuration to 831x partsKim Phillips2011-04-04-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.e, to those parts that have PHY_CLK_VALID bits in their USB CONTROL registers: mpc8308 WU_INT, PHY_CLK_SEL, USB_EN, WU_INT_EN, ULPI_INT_EN mpc831x PHY_CLK_VALID, WU_INT, CLKIN_SEL, PHY_CLK_SEL, UTMI_PHY_EN, PLL_RESET, REFSEL, OTG_PORT, KEEP_OTG_ON, LSF_EN, USB_EN, ULPI_INT_EN mpc834x USB_EN, ULPI_INT1_EN (MPH only), ULPI_INT0_EN mpc837x USB_EN, ULPI_INT_EN (mpc832x, mpc8360 don't have a USB_EHCI_FSL compatible controller) this prevents non-831x parts from never completing cpu_init_f(), because the (non-existent) PHY_CLK_VALID bit never gets set. Reported-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Tested-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
* | IDE: fix compiler warningsWolfgang Denk2011-04-30-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | The changes introduced by commit 0abddf8 ``cmd_ide: enhance new feature "CONFIG_IDE_AHB"'' caused compiler warnings like cmd_ide.c: In function 'ide_init': cmd_ide.c:716: warning: assignment from incompatible pointer type Constify the respective function arguments to fix this. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | common/cmd_mdio.c: fix compile warningAnatolij Gustschin2011-04-30-2/+2
| | | | | | | | | | | | | | | | cmd_mdio.c: In function 'mdio_read_ranges': cmd_mdio.c:97: warning: comparison is always false due to limited range of data type Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Andy Fleming <afleming@freescale.com>
* | miiphy: miiphyutil.c: fix compile warningAnatolij Gustschin2011-04-30-4/+8
| | | | | | | | | | | | | | | | | | | | Fix warning introduced while recent PHY Lib changes: miiphyutil.c: In function 'miiphy_read': miiphyutil.c:304: warning: comparison is always false due to limited range of data type Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Andy Fleming <afleming@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-04-30-128/+1252
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| * | fsl-ddr: Fix mixed-case macro namesKyle Moffett2011-04-29-9/+9
| | | | | | | | | | | | | | | Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Bump up the CONFIG_SYS_BOOTM_LEN to 64M on FSL 85xx boardsKumar Gala2011-04-29-42/+42
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_BOOTMAPSZ has been 64M on these boards for some time so we should also allow the kernel image to be up to 64M decompressed. This also matches what we pass to the OS based on the ePAPR specification. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Enable eSPI support on P1022DSJiang Yutang2011-04-29-0/+18
| | | | | | | | | | | | | | | Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Enable eSPI support for p1_p2_rdbPriyanka Jain2011-04-29-2/+16
| | | | | | | | | | | | | | | | | | | | | Also added support to save env to spi flash in case of SPIBOOT. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Enable eSPI controller & SPI boot support on P2020DSJerry Huang2011-04-29-0/+29
| | | | | | | | | | | | | | | | | | Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc: eSPI and eSPI controller supportMingkai Hu2011-04-29-7/+342
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Singed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Cc: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | tsec: Fix MDIO on devices with eTSEC2Andy Fleming2011-04-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tsec driver was defining the default MDIO address as the TSEC_BASE + 0x520, but on eTSEC2 controllers, the first TSEC's registers are separated from the MDIO registers. Use the existing MDIO_BASE_ADDR, instead. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Change timebase divisor to be defined per processorKumar Gala2011-04-28-5/+19
| | | | | | | | | | | | | | | | | | | | | | | | Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because different SoCs have different divisor amounts. All the PQ3 parts are /8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001Timur Tabi2011-04-28-16/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1 are swapped. Erratum SERDES-A001 says that if bank two is kept disabled and after bank three is enabled, then the PLL for bank three won't lock properly. The work-around is to enable and then disable bank two after bank three is enabled. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORATimur Tabi2011-04-28-17/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Display SERDES 8 erratum warning if banks are not disabledTimur Tabi2011-04-28-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | The work-around for P4080 erratum SERDES-8 requires all lanes of banks two and three to be disabled (powered down) in the RCW. Display a warning message if this is not the case. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005Timur Tabi2011-04-28-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/fsl: add 'pixis_reset dump' commandTimur Tabi2011-04-28-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | Add the 'pixis_reset dump' command, which displays the contents of the PIXIS registers. This command is only available if DEBUG is defined. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/86xx: remove empty board_early_init_f()Timur Tabi2011-04-28-7/+0
| | | | | | | | | | | | | | | | | | | | | Remove an empty board_early_init_f() from the MPC8641HPCN board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Don't set FT_FSL_PCI_SETUP if CONFIG_PCI is not setMatthew McClintock2011-04-27-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A lot of boards set FT_FSL_PCI_SETUP directly in their board code and don't check to see if CONFIG_PCI is actually defined. This will cause the board compilation to fail if CONFIG_PCI is not defined. The p1022ds board is one such example. Instead of fixing every board this patch wraps FT_FSL_PCI_SETUP around CONFIG_PCI so we can remove CONFIG_PCI and boards will still build properly. Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: handle both "secX.Y" and "sec-vX.Y" propertiesKim Phillips2011-04-27-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | versioned SEC properties changed names during development, so for now search and update LIODNs for both "secX.Y" and "sec-vX.Y" based properties. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Enable ESDHC111 erratum on P2040/P3041/P5010/P5020 SoCsLei Xu2011-04-27-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The workaround for ESDHC111 should also be applied on P2040/P3041/P5010/P5020 SoCs. Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020Roy Zang2011-04-27-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)Kumar Gala2011-04-27-10/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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