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* ENGR00310794 iMX6 Fix potential plugin bug which wrecks bootROM registerrel_imx_3.10.31_1.1.0_alphaimx_v2013.04_3.10.31_1.1.0_alphaYe.Li2014-04-28-0/+2
| | | | | | | | | | | The R5 register used plugin code is not saved on stack. If this register is also used in boot ROM, this may cause to destroy the R5 value. Currently, it is a potential problem because the ROM does not use R5 before its calling plug-in. But this is the compiler behavior and not be guaranteed. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 3a0d342db505bb014e59a275fdddacdc907ea7f9)
* ENGR00310792 iMX6SX Change plugin hack address for booting from EIMNORYe.Li2014-04-28-2/+4
| | | | | | | | | | | In “include/asm/arch/mx6_plugin.s” the codes commented by “CONFIG_SYS_BOOT_EIMNOR” is the workaround code, and is used to resolve the WEIM plug in boot issue. But the address is updated to "0x900b5c" on PELE ROM, so u-boot plugin code should update accordingly. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit b79672fd60d35cd74fb0e883eab652bb48b3f4cf)
* ENGR00309792 iMX6SX:SABRESD Disable the RDC temporarilyYe.Li2014-04-28-1/+1
| | | | | | | | Disable RDC in u-boot till kernel implements it. Otherwise, crash may happen in kernel. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 4c519a74a4c7684f229c3205d6a3cbb728d9cbed)
* ENGR00309789 iMX6SX Fix QSPI detect problem in updating and booting m4 imageYe.Li2014-04-28-4/+4
| | | | | | | | | Since the M4 image position is changed to 0x78000000 the QSPI2_B1 flash. The "sf probe" command used in M4 updating and booting script should be changed to "sf probe 1:0". Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 31d984a7984b996160c8438de6d87e1f316473f3)
* ENGR00310132 change imx6sx arm2 qspi u-boot argsAllen Xu2014-04-25-1/+1
| | | | | | change the qspi u-boot to set the mmcdev args in default setting. Signed-off-by: Allen Xu <b45815@freescale.com>
* ENGR00308230 iMX6SX: Remove an build warningYe.Li2014-04-14-0/+2
| | | | | | | | | | Got the warning below, which is caused by having "imx_reset_pfd" call removed for iMX6SX. warning: 'imx_reset_pfd' defined but not used [-Wunused-function] static void imx_reset_pfd(void) Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00308084 iMX6SX:SABRESD Support M4 fast boot at early stageYe.Li2014-04-14-10/+26
| | | | | | | | | | | | | | | | Support M4 boot in 50 ms, kick start M4 at "board_early_init_f" stage where u-boot passes ARM and architecture initialization. Add a configuration "CONFIG_SYS_AUXCORE_FASTUP" for this feature enablement. And a build config "mx6sxsabresd_m4fastup". Adjust the default M4 image address to 0x78000000 represented by "CONFIG_SYS_AUXCORE_BOOTDATA". When M4 fast boot is enabled, RDC must be enabled together and the QSPI driver must turn off. Because M4 is running on QSPI flash in XIP. Setup this relationship by configurations. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00308036 iMX6SX:SABRESD Add RDC settings to MX6SX SABRESD BSPYe.Li2014-04-14-0/+14
| | | | | | | | | | | According to the SRS, in the M4 CAN demo, the GPIO group1 will be shared between A9 and M4. At A9 side, the pins 0, 1, 2, 3 are used. M4 also uses one pin in its application. To synchronize the registers setttings of GPIO1, must enable RDC and RDC semaphore on the GPIO1. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00307874 GPIO: Modify driver mxc_gpio to support RDC SemaphoresYe.Li2014-04-14-0/+50
| | | | | | | | | | | | For GPIO group which shared by multiple masters, it may set in RDC to shared and semaphore required. Before access the GPIO register, the GPIO driver must get the RDC semaphore, and release the semaphore after the GPIO register access. When CONFIG_MXC_RDC is set, the features related to RDC semaphores is enabled in mxc_gpio driver. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00307866 iMX6SX: Add RDC mappings of masters and peripheralsYe.Li2014-04-14-0/+171
| | | | | | | Add the definitions for the RDC mappings on iMX6SX and include this file to "imx-rdc.h" Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00307866 RDC: Add an iMX platform driver for RDC-SEMAYe.Li2014-04-14-0/+355
| | | | | | | | | | | | | | The RDC driver provides interfaces for setting peripherals and masters at BSP initialization, before using the peripherals driver. Another interfaces for lock/unlock RDC semaphore and permission check. The driver assumes boot CPU which runs u-boot is in Domain 0 (default setting on boot). Users should not set it to other domains. The peripherals ID and masters ID may change on different chip, each should provide definitions of the IDs and be included in "imx-rdc.h". Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00307806 iMX6SX:ARM2 Add NAND, SPI-NOR and EIMNOR boot supportYe.Li2014-04-10-71/+452
| | | | | | | | | | | | | | | | | | | | Add the board configurations and BSP support for boot devices NAND, SPI-NOR or EIMNOR. Since the pins conflicts of the devices on ARM2, only support boot features on limited reworked boards as below: NAND Boot: mx6sx_17x17_arm2_nand SPI-NOR Boot: mx6sx_19x19_ddr3_arm2_spinor and mx6sx_17x17_arm2_spinor EIM-NOR Boot: mx6sx_19x19_ddr3_arm2_eimnor The conflicts: QSPI --- NAND pin conflict QSPI --- SPI-NOR u-boot driver conflict SPI-NOR --- SD2 pin conflict WEIM-NOR --- NAND and QSPI pin conflict Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00307803 iMX6SX: Remove PFD reset to support boot with BT_FREQ=1Ye.Li2014-04-10-0/+2
| | | | | | | | | | The PFD reset in U-boot is used to work around a ROM issue existing on old imx6 TO.This will cause the DDR access failed when BT_FREQ=1 because the PLL2 PFD0 is for MMDC clock. Since MX6SX does not have such issue, remove the work around to support boot with BT_FREQ=1. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00306276-3: MX6: Enable ARM errata workaround 794072 and 761320Nitin Garg2014-04-02-0/+2
| | | | | | | Since MX6 is Cortex-A9 r2p10, enable software workaround for errata 794072 and 761320. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00306276-2: ARM: Add workaround for Cortex-A9 errata 761320Nitin Garg2014-04-02-0/+6
| | | | | | | | Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00306276-1: ARM: Add workaround for Cortex-A9 errata 794072Nitin Garg2014-04-02-1/+2
| | | | | | | | A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00306443 [MX6SX] Update the gc400t QoS valueLoren HUANG2014-04-01-0/+9
| | | | | | | | | Per SoC team recommandation, update the gc400t QoS value to write 2 and Read 8. It can improve gpu performance in most case. 3d fill: 165->172Mpixel/s 2d fill: 190->228Mpixel/s Signed-off-by: Loren HUANG <b02279@freescale.com>
* ENGR00303345 iMX6SX: Add M4 boot support by commandYe.Li2014-03-31-0/+75
| | | | | | | | | | Use "bootaux 0x70000000" to boot the M4 from QSPI 0x70000000. The first two word at 0x70000000 must be the stack and pc for the iMX6SX. Add two scripts in environment to boot M4 "m4boot" and update M4 image from SD card "update_m4_from_sd" Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00303345 CMD: Add new command "bootaux" to boot auxiliary coreYe.Li2014-03-31-0/+59
| | | | | | | | | | | To boot a auxiliary core in asymmetric multicore system, introduce the new command "bootaux" to do it. Example of boot auxliary core from 0x70000000 where stores the boot head information that should be parsed by each core. "bootaux 0x70000000" Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00305287 iMX6SX:ARM2 Add support for 19x19 LPDDR2 ARM2 boardYe.Li2014-03-26-4/+147
| | | | | | | | | Add imximage_lpddr2.cfg for DDR controller settings of LPDDR2. Change the folder and files name of "mx6sx_19x19_ddr3_arm2" to "mx6sx_19x19_arm2" to be shared by LPDDR2 ARM2 board and DDR3 ARM2 board. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00304841 ARM: imx: add debug monitor supportAnson Huang2014-03-24-0/+33
| | | | | | | | | | Debug monitor will print out last failed AXI access info when system reboot is caused by AXI access failure, only works when debug monitor is enabled. Enable this module on i.MX6SX. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00304164 iMX6SX:Sabresd Add Android features supportYe.Li2014-03-19-3/+195
| | | | | | | Add BSP codes to mx6sxsabresd to support android uboot features: fastboot, booti and recovery Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00302525 QuadSPI: Update driver to support 4 flash chips on each QSPI.Ye.Li2014-03-10-131/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | Add two configurations "CONFIG_QSPI_BASE" and "CONFIG_QSPI_MEMMAP_BASE" for QSPI registers base and AHB memory base. So the driver is independent from QSPI2. Use "bus" and "cs" parameters to denote 4 flash chip connected on one QuadSPI: SFA1: bus 0, cs 0 SFA2: bus 0, cs 1 SFB1: bus 1, cs 0 SFB2: bus 1, cs 1 Currently in uboot, the SPI flash framework does not have way to notify the flash size to the driver. It brings a problem for QSPI driver to set the memory map space of each chip. In this patch, we fix the mem map space of each chip to 64MB(total is 256MB). So for flash larger than 64MB, driver only support low 64MB. Because u-boot SPI flash framework only supports 24bits address (16MB), the 64MB limitation in driver is ok to work in u-boot. Clean up the spi_xfer and spi read. Divide read to "IP read" and "AHB read". In current implementation, the IPCR is still filled even reading from AHB memory. This causes QSPI to read from flash twice, one to IP buffer, the other to the AHB buffer. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00302525 QuadSPI: Update QSPI clock API to support two QSPI controllersYe.Li2014-03-10-19/+39
| | | | | | | | Modify the QSPI clock enablement with a parameter of QPSI ID. Update the BSP of MX6SX 17x17 ARM2, 19x19 ARM2 and SabreSD to adapt the change. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00300980 ARM:imx6sx-sdb:fec: fix phy autonegation cost long time issueFugang Duan2014-03-06-11/+11
| | | | | | | | | | | | | | | | On imx6sx-sdb platform, when ethernet connect to TP-LINK TL-SF1008+ switch, phy do autonegation cost long time (about 5 seconds), and then fix to 10Mbps full duplex mode, which causes two problems: - Need user to wait long time before tftp load kernel. - 10Mbps mode lead load kernel time too long. The root cause is phy init is not right, the right flow: Enable phy power -> reset phy -> supply clock to phy. After the fix, imx6sx-sdb can work fine with the switch. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00301435 iMX6SX: Add SABRE-SDB board supportYe.Li2014-03-06-0/+1408
| | | | | | | Adding BSP for iMX6SoloX SDB board, enable I2C1, I2C2, ENET, USB OTG1 & OTG2, SD2, SD3, SD4, Serial, QSPI2 and PMIC. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00301993 imx6sx: change fdt_addr to 83000000 for mfgtoolsFrank Li2014-03-06-1/+1
| | | | | | | | | mfgtools download dt file to 83000000 mfgtools download initramfs file to 83800000 because initramfs size is big and variable, dt file may overwrited by initramfs if use 84000000 Signed-off-by: Frank Li <Frank.Li@freescale.com>
* ENGR00301683 FEC: Modify enet driver TX polling bitYe.Li2014-03-05-6/+2
| | | | | | | | | | | | Change to check READY bit in BD, not check the TDAR. On iMX6SX, FEC will clear the TDAR prior than the READY bit of last BD. Since fec driver only prepare two BD for transmit, this cause the BD send failed at the third packet. On iMX6SX, we disabled DCACHE to workaround for this issue. Now change to enable the DCACHE. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00301440 iMX6SX: Update 17x17 and 19X19 arm2 board BSPYe.Li2014-03-05-43/+268
| | | | | | | | | | 1. Enable FEC ENET 2. Add USB Host support for OTG1. OTG2 has pin conflicts with PWM and WDOG So disable it. 3. Add Read/write support for USDHC2(SDA) and USDHC4(eMMC) ports on 17x17. 4. Put Env variables to QSPI flash when boots from QSPI Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00301441-2 iMX6SX/SL: Modify SOC to support two ENETYe.Li2014-03-05-9/+144
| | | | | | | | | | | | | | | | | | | | | iMX6SX has different enet system clocks with iMX6SL, and has two ENET controllers. So update clocks and soc APIs accordingly to support this features. 1. Modify the clock API "enable_fec_clock" to enable enet system clock for each enet controller. 2. Enet RGMII TX clock source may come from external or internal PLL. By default, use the external phy CLK_25M output as TX clock source. Add a configuration "CONFIG_FEC_CLOCK_FROM_ANATOP" for using internal PLL 3. Add clock API "fec_set_rate" to set the RGMII clocks from internal PLL. 4. Modify the MAC address function "imx_get_mac_from_fuse" to get either ENET MAC address. 5. Add clock API "enable_fec_25m_clock" to enable ENET 25Mhz reference clock. 6. Modify 17x17 arm2 BSP and imx6slevk BSP to fit the new APIs. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00301441 ENET:FEC Update fec_mxc driver for iMX6SXYe.Li2014-03-05-1/+9
| | | | | | | | | | | 1. iMX6SX enet rx have 64 bytes alignment limitation for DMA transfer. For i.MX6SX platform, need to add below define in config file: #define CONFIG_FEC_DMA_MINALIGN 64 2. FEC mdio clock source is ipg_clock_s, correct the clock source. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00301442 USB: Uniform USB base address name for all imx6 seriesYe.Li2014-03-05-18/+3
| | | | | | | | Discard the USB name "USBO2H" and "USBOH3". Because the base addresses are same for all imx6 series, uniform the name for ease reading and saving changes. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00301443 iMX6SX: Update pad valueYe.Li2014-03-05-1/+5
| | | | | | | The value of pad "SPEED" field is changed on iMX6SX. Value "00" is for 50Mhz. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00301444 SD/MMC: Update fsl_esdhc driver for iMX6SXYe.Li2014-03-05-0/+14
| | | | | | | | The reset value of "uSDHCx_INT_STATUS_EN" register is changed to 0 on iMX6SX. So the fsl_esdhc driver must update to set the register, otherwise no state can be detected. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00301260 iMX6SX: Add support for 19x19 DDR3 validation boardNitin Garg2014-03-04-319/+1159
| | | | | | | | Add support for the MX6SX:19x19 ARM2 board. Created a common config file for imx6sx 17x17 and 19x19 boards. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00301803 qspi: fix build issueAllen Xu2014-03-04-20/+19
| | | | | | | 1. remove unnecessary code to fix compile warning 2. enable_qspi_clk should be designed for mx6sx only. Signed-off-by: Allen Xu <b45815@freescale.com>
* ENGR00301262-4 iMX6SX: Add support for QSPI bootAllen Xu2014-02-27-0/+1
| | | | | | | | add support for QSPI boot, verified on QSPI2. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Allen Xu <b45815@freescale.com>
* ENGR00301262-3 configs: mx6sx_17x17_arm2_: enable the QuadspiAllen Xu2014-02-27-2/+5
| | | | | | | | Also enable the SPI and SPI FLASH macros, as well as SF test Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Allen Xu <b45815@freescale.com>
* ENGR00301262-2 qspi: add Freescale QuadSPI supportAllen Xu2014-02-27-1/+830
| | | | | | | | | | enabled qspi read/write/erase functions and passed 3 byte mode tests. Acked-by: Shawn Guo Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Allen Xu <b45815@freescale.com>
* ENGR00301262-1 ARM: imx6sx: init for the QuadSPIAllen Xu2014-02-27-5/+72
| | | | | | | | enable the clock, and set the proper PADs for the quadspi. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Allen Xu <b45815@freescale.com>
* ENGR00300374 video: ipu: wait for DP SF end irq when disabling sync BG flowLiu Ying2014-02-26-22/+22
| | | | | | | | | | Instead of waiting for DC triple buffer to be cleared, this patch changes to wait for a relevant DP sync flow end irq when disabling sync BG flows. In this way, we align the implement to the FSL internal IPUv3 driver. After applying this patch, the uboot hang up issue at the arch_preboot_os stage on the MX6DL platforms is not observed any more. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00299848 ARM:imx6 Change static environment SD/MMC storage to dynamicYe.Li2014-02-25-25/+351
| | | | | | | | | | | | | | | | | | imx6 boards (sabresd, sabreauto, arm2 and slevk) have multiple SD/MMC ports to boot. But current uboot hard code the SD/MMC port for environment variables storage. So if customer changes a port without modifying the configuration "CONFIG_SYS_MMC_ENV_DEV", error will issue at saving and loading environment. Implement a mechanism to detect SD/MMC port from SRC SMBR register, and override the default "mmc_get_env_devno". The "board_late_mmc_env_init" is used to set "mmcdev" when booting from SD/MMC port. Finally after booting from SD/MMC, the environment storage device and "mmcdev" are both set to current SD/MMC port. Customers don't need to re-build the image if booting from different SD/MMC port. This patch also adds SD1 and SD3 support to imx6slevk BSP, and adds support for sabreauto SD1 slot on base board. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00299356 ARM:imx6 Fix USDHC driver bug in PIO modeYe.Li2014-02-18-15/+10
| | | | | | | | | | | | | | When configure the USDHC driver to PIO mode by defining "CONFIG_SYS_FSL_ESDHC_USE_PIO", the SD/MMC read and write will fail. Two bugs in the driver to cause the issue: 1. The read buffer was invalidated after reading from DATAPORT register, which should be only applied to DMA mode. The valid data in cache was overwritten by physical memory. 2. The watermarks are not set in PIO mode, will cause according state not be set. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00298503-3: Add iMX6sx 17x17 validation board QSPI2 bootNitin Garg2014-02-17-1/+4
| | | | | | | | Adding support to boot i.MX6SoloX 17x17 validation board from QuadSPI2 Micron flash. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00298503-2: Add iMX6sx 17x17 validation board supportNitin Garg2014-02-17-0/+1115
| | | | | | | | | | | Adding support for i.MX6SoloX 17x17 DDR3 validation board support. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00298503-1: Remove SATA and IPU clk function for iMX6SXNitin Garg2014-02-17-0/+4
| | | | | | | Since SATA and IPU doesn't exists on iMX6SX, remove those clk functions. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00298503: Add iMX6sx SoC supportNitin Garg2014-02-12-18/+2093
| | | | | | | | | | Adding clks, pinmux, memory map, etc for iMX6SoloX. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00296077 ARM:imx6sl: reset can NOT work on TO1.2Ye.Li2014-01-22-1/+4
| | | | | | | | | Boot ROM fix the "glitchless mux" issue on TO1.2 which will mask MMDC_CH0_MASK in CCM_CCDR, it will cause different behavior of reset, need to clear this MMDC_CHx_MASK field to make sure all the i.MX6 series SOCs have same behavior of reset. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00295560 ARM:imx6sl:evk Add SPI NOR flash boot and access supportYe.Li2014-01-17-4/+63
| | | | | | | | | | Add BSP codes to support SPI NOR flash read, write and erase by using "sf" command. In addition, add a new configuration "mx6slevk_spinor" for building the uboot that can be booted from SPI NOR flash and stored the environments variables in it. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00294905 ARM:imx6:sabreauto Add USB HOST BSP supportYe.Li2014-01-17-15/+144
| | | | | | | | | | | | Sabreauto board has pin conflict (pin EIM_D18) between NOR flash and i2c3. To enable the USB host, the i2c3 must be used to operate the max7310 IO expander to output the VBUS power. As SPINOR is enabled at default, it is impossible to use USB host at same time. Thus, remove the SYS_USE_SPINOR from sabreauto configurations to disable SPINOR. Signed-off-by: Ye.Li <B37916@freescale.com>
generated by cgit v1.1 at 2024-11-21 13:19:26 +0000