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* Tegra30: mmc: Add Tegra30 SDMMC compatible entry to fdtdec & driverTom Warren2013-03-14-1/+3
| | | | | | | | | Tegra30 SD/MMC controller differs enough from Tegra20 that it needs its own entry in the compat_names/compat_id tables and in the Tegra MMC driver. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* mmc: Tegra: Add SD bus power/voltage function and MMC pad init call.Tom Warren2013-03-14-8/+55
| | | | | | | | | | | | | | Tegra30 requires the SD Bus Voltage & Power bits be set in the SD Power Control register. Tegra20 works w/o them set, but do it anyway for those SoCs as it's part of the SD spec. Also call a common board pad init routine (pad_init_mmc) in mmc_reset(), used by Tegra30 only for now. Note that Tegra20 SD/MMC HW differs enough from Tegra20 that a new compatible entry is used in the fdt compat_names/id tables. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra30: MMC: Add SD bus power-rail and SDMMC pad init routinesTom Warren2013-03-14-1/+81
| | | | | | | T30 requires specific SDMMC pad programming, and bus power-rail bringup. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: MMC: Added/update SDMMC registers/base addresses for T20/T30Tom Warren2013-03-14-6/+29
| | | | | | | | Removed SDMMC base addresses from tegra.h since they're no longer used. Added additional vendor-specific SD/MMC registers and bus power defines. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra30: fdt: Add SDMMC (sdhci) nodes for T30 boards (Cardhu for now)Tom Warren2013-03-14-0/+47
| | | | | | | Took these values directly from the kernel dts files. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra30: Cardhu: Add pad config tables/code based on pinmux codeTom Warren2013-03-14-5/+285
| | | | | | | | | | | | | | | | Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, only SDIO1CFG is changed as per the TRM to work with the SD-card slot on Cardhu. Thanks to StephenW for the suggestion/original idea. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra114: pinmux: Update pinmux tables & code, fix a bug w/SDMMC3 initTom Warren2013-03-14-377/+449
| | | | | | | | | | | | | Use the latest tables & code from our internal U-Boot repo. The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup table were off by a few indices, causing the pinmux init code to write bad data to the PINMUX_AUX_ regs. This also enabled the lock bit, which made it impossible to reconfig the pads correctly for SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N, USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra30: Cardhu: Remove unneeded cardhu.c.mmc fileTom Warren2013-03-14-151/+0
| | | | | | | | This was an older debug/developmental file that got added accidentally. Not needed/used in any Cardhu build. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra114: fdt: Sync DT nodes with kernel DT files (GPIO, tegra_car)Tom Warren2013-03-14-1/+18
| | | | | | | Minor edit to tegra_car node, add gpio node. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: Remove unused CONFIG_SYS_CPU_OSC_FREQUENCY defineTom Warren2013-03-14-5/+3
| | | | | | | This wasn't used anywhere in any Tegra build. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: Add twarren as maintainer for Tegra30 and Tegra114 SoCsTom Warren2013-03-14-0/+2
| | | | | Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: implement WAR for Tegra114 CPU reset vectorStephen Warren2013-03-14-4/+32
| | | | | | | | | | | | | A Tegra114 HW bug prevents the main CPU vector from being modified under certain circumstances. Tegra114 A01P and later with a patched boot ROM set the CPU reset vector to 0x4003fffc (end of IRAM). This allows placing an arbitrary jump instruction at that location, in order to redirect to the desired reset vector location. Modify Tegra114's start_cpu() to make use of this feature. This allows CPUs with the patched boot ROM to boot. Based-on-work-by: Jimmy Zhang <jimmzhang@nvidia.com>. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra30: fdt: Sync DT nodes with kernel DT files (I2C, SPI, GPIO, clock)Tom Warren2013-03-14-34/+61
| | | | | | | Minor edits to clock, apbdma and SPI, make I2C match kernel DT, and add gpio Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: fdt: Remove memreserve line from Cardhu/Seaboard DT filesTom Warren2013-03-14-2/+0
| | | | | | | Not used, and wrong in Cardhu's case Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: MMC: Add DT support to MMC driver for all T20 boardsTom Warren2013-03-14-208/+173
| | | | | | | | | | | | tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc. Tested on Seaboard, fully functional. Tamonten boards (medcom-wide, plutux, and tec) use a different/new dtsi file w/common settings. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT filesTom Warren2013-03-14-12/+109
| | | | | | | | | | Linux dts files were used for those boards that didn't already have sdhci info populated. Tamonten has their own dtsi file with common sdhci nodes (sourced from Linux). Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: fdt: tamonten: Add common tamonten.dtsi file from linuxTom Warren2013-03-14-3/+492
| | | | | | | | | Tamonten boards (medcom-wide, plutux, and tec) use a different/new dtsi file w/common settings. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: fdt: Change /include/ to #include for C preprocessorTom Warren2013-03-14-16/+17
| | | | | | | | | dts Makefile has the arch & board include paths added to DTS_CPPFLAGS. This allows the use of '#include "xyz"' in the dts/dtsi file which helps the C preprocessor find common dtsi include files. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra114: I2C: Enable I2C driver on Dalmore E1611 eval boardTom Warren2013-03-14-0/+12
| | | | | | | | Tested all 5 'buses', i2c probe enumerates device addresses on bus 0, 1 and 2. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
* Tegra114: fdt: Update DT files with I2C info for T114/DalmoreTom Warren2013-03-14-0/+89
| | | | | | | | | | | T114, like T30, does not have a separate/different DVC (power I2C) controller like T20 - all 5 I2C controllers are identical, but I2C5 is used to designate the controller intended for power control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: I2C: Add T114 clock support to tegra_i2c driverTom Warren2013-03-14-5/+45
| | | | | | | | | | | | | T114 has a slightly different I2C clock, with a new (extra) divisor in standard/fast mode and HS mode. Tested on my Dalmore, and the I2C clock is 100KHz +/- 3Hz on my Saleae Logic analyzer. Added a new entry in compat_names for T114 I2C since it differs from the previous Tegra SoCs. A flag is set when T114 I2C HW is found so new features like the extra clock divisor can be used. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
* Tegra114: I2C: Take DVFS out of reset to allow I2C5 (PWR_I2C) to workTom Warren2013-03-14-0/+1
| | | | | | | | | I2C driver can now probe dev 0 (PWR_I2C, where the PMU, etc. lives). This is needed so that the SDIO slot power can be brought up for the MMC driver, so it has to precede those commits. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: usb: move [start|stop]_port into ehci_hcd_[init|stop]Lucas Stach2013-03-14-87/+51
| | | | | | | | | | The ehci_hcd entry points were just calling into the Tegra USB functions. Now that they are in the same file we can just move over the implementation. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: move implementation into right directoryLucas Stach2013-03-14-560/+536
| | | | | | | | | | | | | | | | This moves the Tegra USB implementation into the drivers/usb/host directory. Note that this merges the old /arch/arm/cpu/armv7/tegra20/usb.c file into ehci-tegra.c. No code changes, just moving stuff around. v2: While at it also move some defines and the usb.h header file to make usb driver usable for Tegra30. NOTE: A lot more work is required to properly init the PHYs and PLL_U on Tegra30, this is just to make porting easier and it does no harm here. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: various small cleanupsLucas Stach2013-03-14-15/+1
| | | | | | | | | Remove unneeded headers, function prototype and stale comment, that doesn't match the actual codebase anymore. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: move controller init into start_portLucas Stach2013-03-14-28/+29
| | | | | | | | | | | There is no need to init a USB controller before the upper layers indicate that they are actually going to use it. board_usb_init now only parses the device tree and sets up the common pll. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: remove unneeded function parameterLucas Stach2013-03-14-4/+2
| | | | | | | | Just a dead parameter, never actually used. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: make controller init functions more self containedLucas Stach2013-03-14-12/+12
| | | | | | | | | | | | | There is no need to pass around all those parameters. The init functions are able to easily extract all the needed setup info on their own. This allows to move out the controller init into ehci_hcd_init later on, without having to save away global state for later use and thus bloating the file global state. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: set USB_PORTS_MAX to correct valueLucas Stach2013-03-14-1/+1
| | | | | | | | Both Tegra20 and Tegra30 have a max of 3 USB controllers. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Refactor linker-generated arraysAlbert ARIBAUD2013-03-12-351/+380
| | | | | | | | | | | | | | | | | | | | | | | | Refactor linker-generated array code so that symbols which were previously linker-generated are now compiler- generated. This causes relocation records of type R_ARM_ABS32 to become R_ARM_RELATIVE, which makes code which uses LGA able to run before relocation as well as after. Note: this affects more than ARM targets, as linker- lists span possibly all target architectures, notably PowerPC. Conflicts: arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds arch/arm/cpu/armv7/omap-common/u-boot-spl.lds board/ait/cam_enc_4xx/u-boot-spl.lds board/davinci/da8xxevm/u-boot-spl-da850evm.lds board/davinci/da8xxevm/u-boot-spl-hawk.lds board/vpac270/u-boot-spl.lds Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* arm: make __bss_start and __bss_end__ compiler-generatedAlbert ARIBAUD2013-03-12-32/+122
| | | | | | | | | | | | | Turn __bss_start and __bss_end__ from linker-generated to compiler-generated symbols, causing relocations for these symbols to change type, from R_ARM_ABS32 to R_ARM_RELATIVE. This should have no functional impact, as it affects references to __bss_start and __bss_end__ only before relocation, and no such references are done. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Remove linker lists (LGAs) from SPL linker scriptsAlbert ARIBAUD2013-03-12-42/+164
| | | | | | | | | | | | Many SPL linker scripts needlessly include linker lists (aka LGAs). Remove them whenever possible; keep it only in the seven am335x_evm variants (am335x_evm, am335x_evm_uart[1-5], am335x_evm_spiboot), where there is actual content in output section .u_boot_list. This commit keeps all u-boot.bin and u-boot-spl.bin in ARM targets byte-identical. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* arm: omap: map u_boot_lists section to .sramAlbert ARIBAUD2013-03-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Output section .u_boot_list was left unmapped in u-boot-spl.lds for omap-common, causing the location counter to roll back to bteween .rodata and .data, making __image_copy_end and _end symbols wrong. Mapping output section .u_boot_list to memory .sram fixes these symbols' mapping. This modifies the SPL binary but has no functional impact, as __image_copy_end and _end are never used in SPLs and u_boot_list is empty for all 29 boards affected (omap4_sdp4430 eco5pk igep0030 am335x_evm_uart3 omap3_beagle am3517_crane igep0032 mt_ventoux pcm051 am3517_evm omap3_evm_quick_mmc am335x_evm_uart2 am335x_evm_spiboot am335x_evm_uart1 omap3_evm igep0030_nand omap3_overo igep0020 am335x_evm omap4_panda omap5_evm am335x_evm_uart4 devkit8000 tricorder mcx twister omap3_evm_quick_nand am335x_evm_uart5 igep0020_nand). Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-12-62/+79
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| * ARM: sam9x5: fix ethernet pins in MII modeJesse Gilles2013-03-12-8/+8
| | | | | | | | | | | | | | Fix pin setting in MII mode Signed-off-by: Jesse Gilles <jgilles@multitech.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * ARM: at91sam9x5: Using CPU string directlyBo Shen2013-03-12-13/+7
| | | | | | | | | | | | | | As the CPU name is not configurable, using CPU string directly Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * ARM: at91: change nand flash tableBo Shen2013-03-12-40/+41
| | | | | | | | | | | | | | | | | | | | Change nand flash partition table according to www.at91.com/linux4sam more information: http://www.at91.com/linux4sam/bin/view/Linux4SAM/GettingStarted#Linux4SAM_NandFlash_demo_Memory Signed-off-by: Bo Shen <voice.shen@atmel.com> [minor commit message changes] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/configs: add bootz to configurationNicolas Ferre2013-03-12-0/+6
| | | | | | | | | | | | | | | | | | Support to boot zImage Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> [Add bootz for at91rm9200, at91sam9263, at91sam9rl] Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/configs: add libfdt to configurationNicolas Ferre2013-03-12-0/+8
| | | | | | | | | | | | | | | | | | support to boot device tree Linux kernel Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> [Add libftd for at91rm9200, at91sam9263, at91sam9rl] Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * ARM: atmel: add at91sam9g20ek_2mmc nand boot supportBo Shen2013-02-19-1/+9
| | | | | | | | | | | | | | | | | | | | Add at91sam9g20_2mmc nand boot support. on this board, there is no dataflash, so disable it change one commet for at91sam9g20ek board Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge u-boot/master into u-boot-ti/masterTom Rini2013-03-11-2275/+6801
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In master we had already taken a patch to fix the davinci GPIO code for CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these conflicts manually and comment the #else/#endif lines for clarity. Conflicts: arch/arm/include/asm/arch-davinci/gpio.h drivers/gpio/da8xx_gpio.c Signed-off-by: Tom Rini <trini@ti.com>
| * | x86: Enable CONFIG_OF_CONTROL on corebootSimon Glass2013-03-04-0/+6
| | | | | | | | | | | | | | | | | | | | | Make use of a device tree on coreboot boards, and set the default to link. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Adjust link device tree include fileSimon Glass2013-03-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This is currently set to coreboot.dtsi, but we cannot support this on old device tree compilers (dtc <= 1.3), so adjust to use ARCH_CPU_DTS to let the Makefile preprocessor sort this out. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add error checking to x86 relocation codeSimon Glass2013-03-04-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This does not actually change normal behaviour, but adds a check that should detect corruption of relocation data (e.g. by using BSS data prior to relocation). Also add additional debugging output when enabled. During this investigation, two situations have been seen: 1. calculate_relocation_address(): uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start; turns into 111166f: b8 83 c4 17 01 mov $0x117c483,%eax whih is beyond the end of bss: 0117b484 g .bss 00000000 __bss_end Somehow the __bss_end here is 255 bytes ahead. 2. do_elf_reloc_fixups(): uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start; Here the __text_start is 0 in the file: 1111d9f: bb a0 e0 13 01 mov $0x113e0a0,%ebx 1111da4: 81 ef 00 00 00 00 sub $0x0,%edi As it happens, both of these are in pre-relocation code. For these reasons we silent check and ignore bad relocations. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Support relocation of FDT on start-upSimon Glass2013-03-04-2/+46
| | | | | | | | | | | | | | | | | | | | | With CONFIG_OF_CONTROL we may have an FDT in the BSS region. Relocate it up with the rest of U-Boot to keep the rest of memory free. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Rearrange the output input to remove BSSSimon Glass2013-03-04-7/+12
| | | | | | | | | | | | | | | | | | | | | At present BSS data is including in the image, which wastes binary space. Remove it by rearranging the sections so that BSS is last. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add an __end symbol to signal the end of the U-Boot binarySimon Glass2013-03-04-1/+4
| | | | | | | | | | | | | | | | | | | | | With this symbol we can easy append something (e.g. an FDT) to the U-Boot binary and access it from within U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Permit bootstage and timer data to be used prior to relocationSimon Glass2013-03-04-18/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to access the timer before U-Boot has relocated so that we can fully support bootstage. Add new global_data members to support this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add basic cache operationsSimon Glass2013-03-04-0/+23
| | | | | | | | | | | | | | | | | | | | | At present most x86 cache operations are undefined. Add a basic implementation for these. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add function to get top of usable ramSimon Glass2013-03-04-24/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory layout calculations are done in calculate_relocation_address(), and coreboot has its own version of this function. But in fact all we really need is to set the top of usable RAM, and then the base version will work as is. So instead of allowing the whole calculate_relocation_address() function to be replaced, create board_get_usable_ram_top() which can be used by a board to specify the top of the area where U-Boot relocations to. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-26 09:05:04 +0000