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* ENGR00217505-7 uboot: gpmi: update the mtd->ecc_stats when reading page failedHuang Shijie2012-08-20-3/+8
| | | | | | | | | | | | If tell the real correcting infomation to the upper layer of MTD, the torture thread of UBIFS will do the torture test in a very often frequency. This will eat up all the reservation blocks of the UBIFS. So tell the real correcting infomation only when the failure occured, or the corrected times nearly reached the ECC threshold. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00217505-6 uboot: gpmi: set default value for busy_timeoutHuang Shijie2012-08-20-0/+5
| | | | | | | Set 0x500 to the busy_timeout in HW_GPMI_TIMING1. If we do not set this busy_timeout, the gpmi may become unstable. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00217505-5 uboot: gpmi: update the ecc_strength codeHuang Shijie2012-08-20-66/+160
| | | | | | | Rewrite the code for calculate the ecc strength. Use the same code as in the gpmi driver. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00217505-4 uboot: gpmi: replace the gpmi_nfc_reset_block()Huang Shijie2012-08-20-77/+96
| | | | | | Use the latest gpmi_reset_block(), and remove the old gpmi_nfc_reset_block(). Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00217505-3 uboot: gpmi: use the community's nand chip databaseHuang Shijie2012-08-20-108/+19
| | | | | | Abandon our nand chip database, use the community's database. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00217505-2 uboot: mtd: update nand_get_flash_type()Huang Shijie2012-08-20-33/+325
| | | | | | | update nand_get_flash_type() to the latest code. Also add the support of ONFI nand. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00217505-1 uboot: MX6Q-ARD: add a NAND boot configHuang Shijie2012-08-20-0/+272
| | | | | | add a new config for NAND boot in the mx6q-ard board. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00220486 Modify ODT values for Solo AIAlejandro Sierra2012-08-20-4/+4
| | | | | | | | | | | | | | | | | | Modify ODT values for Solo AI. Some Solo boards did not passed the "mtest" from uboot using the previous configuration. Old configuration: MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00000007) MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00000007) MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00000007) MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00000007) New configuration: MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00011117) Signed-off-by: Alejandro Sierra <b18039@freescale.com>
* ENGR00220161: imx6sl: Add MX6SL EVK SupportRobby Cai2012-08-14-0/+2567
| | | | | | | | | Add mx6sl evk board support - copied from ARM2 board support - added a new board revision - removed unused boot device detection Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00220164 pfuze:rise VDDARM_IN to 1.425V and work around pfuze1.0Robin Gong2012-08-13-0/+45
| | | | | | | | | 1.Considering pfuze tolerance and IR drop and board ripple, need rise from 1.375V to 1.425V. Only for Sabresd. 2.workaround pfuze1.0 ER1, set all buck regulator except SW1C to PWM mode. now for mx6sl_arm2 and mx6_sabresd. Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00220076 fix the fastboot usb re-connect issueLiGang2012-08-10-0/+8
| | | | | | | in fastboot mode, if usb cable re-connectted, the fastboot feature will fail. This issue is caused by logic control oversight. Signed-off-by: LiGang <b41990@freescale.com>
* ENGR00219854-1 Enable fastboot feature on mx6q-arm2 boardLiGang2012-08-09-7/+54
| | | | | | | | 1. enable fastboot feature on mx6q-arm2 board 2. enlarge fastboot buffer to 320MB 3. correct some usb descriptors Signed-off-by: LiGang <b41990@freescale.com>
* ENGR00219636 MX6 UBOOT : Enlarge command line buffer sizeEric Sun2012-08-07-11/+12
| | | | | | | | | | | | | | | | | | There is a problem that a too long command line parameter in U-Boot console will actually be truncated and not properly truncated to the kernel. The root cause is that the command line in the U-Boot console is read into a buffer --- console_buffer[CONFIG_SYS_CBSIZE]. Currently the CONFIG_SYS_CBSIZE is set as 256. Command line parameter larger than it will not be recorded. On the other hand, max length of boot parameter of linux kernel is set to 1024, which means it can accept parameter size as large as 1024. So we need to align these 2 values. Enlarge CONFIG_SYS_CBSIZE to 1024 as well. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00218915-2 MX6 SabreSD:Use new 8bit bmp boot logoLiu Ying2012-08-03-5/+5
| | | | | | | | This patch changes to use new 8bit 600x400 bmp boot logo. As this boot logo has black background and white words, the user experience will be better. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00218915-1 FSL common:Add new boot logoLiu Ying2012-08-03-1/+30159
| | | | | | | This patch adds new boot 8bit 600x400 bmp logo who has black background and white words. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00218972 MX6 Secure Boot, Change to dynamic HAB data authenticationEric Sun2012-08-01-24/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original secure boot implementation make a consumption that u-boot.bin will not exceed 0x2F000. With this consumption, the hab data is hard coded in linker script file to relative address 0x2F000 without causing any problem. But when this consumption don't hold, the hard coded way will cause memory region overlap and break build. So we need to change to a dynamic way of allocating hab_data. The new implementation put hab data at the next 0x1000 alignment after u-boot data and text section, instead of hard coded to 0x2F000. Similar changes is made to uImage authentication implementation. Changes in U-Boot includes: - in u-boot.lds file, change "__hab_data" to dynamic align to 0x1000 - change authenticate_image implementation, originally the uImage parameters are hard coded, now they are retrived from the "load_addr" and the image_hdr The new secure image layout: U-Boot +-------------------+ DDR_START | | | U-Boot Image | | | +-------------------+ DDR_START + UBOOT_SIZE | PADDING | +-------------------+ align to 0x1000 | CSF Data | - +-------------------+ +-- CSF + Pad, Size : 0x2000 | PADDING | - +-------------------+ uImage +-------------------+ DDR_START | | | uImage | | | +-------------------+ DDR_START + UIMAGE_SIZE | PADDING | +-------------------+ align to 0x1000 | IVT | ---- Size : 0x20 +-------------------+ | CSF Data | - +-------------------+ +-- CSF + Pad, Size : 0x2000 | PADDING | - +-------------------+ Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00218583-5 MX6DL SabreSD Android:Add splashimage uboot varLiu Ying2012-07-31-1/+4
| | | | | | | | This patch adds splashimage related variables to board configure file so that splashimage can work without touching the uboot variables. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00218583-4 MX6Q SabreSD Android:Add splashimage uboot varLiu Ying2012-07-31-2/+4
| | | | | | | | This patch adds splashimage related variables to board configure file so that splashimage can work without touching the uboot variables. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00218583-3 MX6DL SabreSD:Enable splashimage by defaultLiu Ying2012-07-31-0/+1
| | | | | | | This patch adds CONFIG_SPLASH_SCREEN definition to board config file to enable splashimage by default. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00218583-2 MX6Q SabreSD:Enable splashimage by defaultLiu Ying2012-07-31-0/+1
| | | | | | | This patch adds CONFIG_SPLASH_SCREEN definition to board config file to enable splashimage by default. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00218583-1 MX6Q/DL SabreSD:Support LVDS1 splashimageLiu Ying2012-07-31-0/+9
| | | | | | | This patch configures iomux gpr3 register to enable LVDS1 via IPU1 DI1 if user chooses to use it. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00218805 imx6: print the silicon revision correctlyJason Liu2012-07-30-11/+4
| | | | | | | | | | | | | | The silicon revision is not printed correctly, on ARM2 and sabrelite board, the log is just as the following: CPU: Freescale i.MX6 family TO0.0 at 792 MHz We need print the silicon revision correctly as: CPU: Freescale i.MX6 family TO1.2 at 792 MHz with i.mx6q TO1.2 chip Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00218465 Android: mx6sl-arm2: fix fastboot crash issueLiGang2012-07-30-8/+19
| | | | | | | | Fix fastboot crash issue on fastmx6sl-arm2 board. Enlarge fastboot buffer size to 320MB for mx6 arm2 board, mx6 sabresd board, thus fastboot could flash system.img up to 320MB Signed-off-by: LiGang <b41990@freescale.com>
* ENGR00217401 common: fix build warningXinyu Chen2012-07-26-11/+21
| | | | | | | | | Fix the build warning in uboot build. Fix bug of incorrect dereference to periph2 clock pre divider. Fix incorrect type of maxpackage size assign, even it's not used at all in fastboot. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00218282 MX6Q: fix linker error when more configure enabled.Zhang Jiejing2012-07-25-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fix the linker error when enable more function(like CONFIG_NAND, CONFIG_SPASHSCREEN,etc) in uboot ARM2 board, and a possable linker error for other MX6 boards: /home/lambert/share/SATA2/R13.3/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/ bin/arm-eabi-ld: section .bss [27831000 -> 278666e7] overlaps section .rodata [2782387c -> 278609eb] /home/lambert/share/SATA2/R13.3/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/ bin/arm-eabi-ld: section .rodata.str1.1 [278609ec -> 27867803] overlaps section .bss [27831000 -> 278666e7] One issue here is: A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. Another issue is: The secure boot feature require __hab_data section in uboot linker script, but it's have a hard coding magic number, but if we enable more code, cause .text section bigger, it will cross the line, so it report the first linker error. This commit disable SECURE_BOOT feature by default for android, and comments if user want to use this feature, it needs change the .lds by there configure. Also, enlarge the magic number that this feature needs to cover if more code is build in. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00218067 mx6sl LDO_BYPASS: enable LDO BYPASS in mx6sl by defaultRobin Gong2012-07-24-1/+1
| | | | | | | To validate LDO bypass function fully, enable CONFIG_MX6_INTER_LDO_BYPASS on u-boot and kernel, only for mx6sl. Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00217764 MX6 Secure Boot : Fix NAND BOOT Failure due to secure patchEric Sun2012-07-23-10/+20
| | | | | | | | | | | | | | | | | | With the secure boot patch. MX6 NAND Boot is not functional. The root cause is that, the original secure boot patch fills "0xFF' to spacing regions, due to a issue in ROM code, read pages of all "0xff" will be treated as a critical error. Thus prevent the U-Boot from booting normally. The fix adjust image copy size in IVT so that when secure boot is not enabled, no unuseful data is copied by ROM code. Also the secure boot option is default disabled. The end user won't enable it unless they know what they are doing. These prevent the ROM code from copied pages of "0xff" data, and fix the issue. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00217381-02: show sd/mmc clk freq for mmcinfoRyan QIAN2012-07-19-1/+2
| | | | | | | It prints sd clk freq for cmd of mmcinfo, then it is much easier to tell which mode sd/mmc card is running at. Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00217381-01: mx6sl add sd1 and sd2 to support SD3.0Ryan QIAN2012-07-19-2/+2
| | | | | | enable SD3.0 support on SD1 and SD2 on mx6sl arm2 cpu board. Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00217114-2 MX6 U-Boot, Secure Boot, one code base for MX6Q/DL/SLEric Sun2012-07-13-5/+6
| | | | | | | Move the uImage authentication to an earlier phase, in this way prevent DDR content changed by OS load code, causing authentication failure. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00217114-1 MX6 U-Boot, Secure Boot, one code base for MX6Q/DL/SLEric Sun2012-07-13-171/+206
| | | | | | | | Move the secure boot related implementation code from mx6q_arm2.c to mx6/generic.c. In this way the HAB feature can be shared by all MX6 platforms Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00216852 MX6SL ARM2, UBoot : Apply V0.93 LPDDR2 ScriptEric Sun2012-07-13-17/+20
| | | | | | | | IC Validation team release new LPDDR2 script V0.93 in the following link, "http://compass.freescale.net/livelink/livelink?func=ll&objId=226733834/" Make changes to align to it Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00215197 pfuze MX6SL_ARM2: enable LDO bypass on u-bootimx-android-r13.5-alphaRobin Gong2012-07-04-0/+329
| | | | | | 1.enable I2C and I2C bus recovery support on mx6sl_arm2 2.enable LDO bypass on u-boot, by configuring 'CONFIG_MX6_INTER_LDO_BYPASS' Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00215367 MX6 Platforms, remove "nosmp" in default parametersEric Sun2012-07-03-4/+2
| | | | | | | | nosmp is added in the bootargs originally because of issues in kernel smp implementation. Now these issues are fixed and we can safely remove them Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00215633 MX6DL LPDDR2 : enable plugin mode of system bootEric Sun2012-07-03-8/+590
| | | | | | | | | | | | | | | | | | | | | For MX6DL LPDDR2 board, in order to use both the 2 channels of the memory, the "PL301_FAST2" must be set to 0x1. However this bit is not accessible using DCD. Plugin mode must be utilized for this purpose. The patch can be verified this way: Enter U-boot console > mw.l 0x80000000 0xC0 10 > mw.l 0x10000000 0xC1 10 > md.l 0x10000000 10 > md.l 0x80000000 10 Before the patch, 0x10000000 and 0x80000000 in fact point to the same memory location. So the last 2 dump will show memory content of both 0x000000C1 After the patch, 0x80000000 ponit to channel 0, 0x10000000 point to channel 1. the last 2 dump will show memory content of 0x000000C0 and 0x000000C1 respectively Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00215515 MX6: Move IPU QoS and VDOA/IPU/VPU AXI Cache config to kernelWayne Zou2012-07-02-70/+18
| | | | | | | Move IPU QoS and VDOA/IPU/VPU AXI Cache config to linux kernel in order to reduce code duplicate Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00214947 MX6 UBOOT : default enable wait mode as default parametersEric Sun2012-06-26-8/+6
| | | | | | | | For historical reasons U-Boot set "enable_wait_mode=off" in default U-Boot parameter. Now wait mode is OK for these platforms so we remove these settings. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00214866 MX6SL ARM2, UBoot : Apply V0.91 LPDDR2 ScriptEric Sun2012-06-26-463/+397
| | | | | | | | | | | Validation team released lateset LPDDR2 script V0.91, See "http://compass.freescale.net/livelink/livelin k?func=ll&objId=226435628&objAction=browse&viewType=1" This change is necessary for bus freq scaling Apply it for both DCD mode and plugin mode. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00213689 - U-Boot: EPDC Splash Screen failing for MX 6DL/SDanny Nold2012-06-14-4/+4
| | | | | | | | | | | Fix a hang and a garbage update to the E Ink panel with the following changes for both MX 6DL/S SabreSD and MX 6DL/S ARM2: - Update the address for the EPDC waveform file to 6MB offset in SD card. - Update the waveform file size to cover the default Pearl panel waveform file. Signed-off-by: Danny Nold <dannynold@freescale.com>
* ENGR00212229 [MX6SL_ARM2]uboot: 8bit MMC cards failed to boot on SD1.Ryan QIAN2012-06-08-4/+4
| | | | | | | | | | | | issue: SD1 connector on ARM2 is an MS-SD combo one which can not make good contact with DAT4~DAT7 of 8bit mmc cards. It is an hw limitation which will cause boot failure from 8bit mmc. solution: disable SD1 8bit mode on MX6SL arm2 board. Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00212571 [MX6]Change DRAM ODT setting to save powerAnson Huang2012-06-06-17/+17
| | | | | | | | | | | | | | | | We can use weak ODT setting, it will save about 50% DDR power in runtime. Now we use 0x00007 MMDC0_MPODTCTRL MMDC1_MPODTCTRL, (Ohm) Setting DDR_ODT imx_ODT Max_overclocking 0x22227 120 060 615MHz 0x11117 120 120 604MHz 0x00007 120 000 576MHz 0x00000 000 000 556MHz Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00212287 - U-Boot EPDC splash screen: Disable EPDC splash by defaultDanny Nold2012-06-04-4/+4
| | | | | | | | | | - EPDC splash screen changed to be disabled by default in the config file for MX6DL_SABRESD and MX6DL_ARM2. If left enabled, the U-Boot image will not boot correctly (hang), since some additional content on the boot device (waveform file) is required for EPDC splash to work correctly. - Fixes U-Boot break introduced with commit for ENGR00212287 Signed-off-by: Danny Nold <dannynold@freescale.com>
* ENGR00211117 - U-Boot: Add EPDC splash screen for MX 6DL/S platformsDanny Nold2012-05-30-10/+653
| | | | | | | | | - EPDC Splash support for MX6DL/S Sabre SD - EPDC Splash support for MX6DL/S ARM2 - Currently, splash screen consists of a simple black border around a white screen. Done this way to save in memory footprint. Signed-off-by: Danny Nold <dannynold@freescale.com>
* ENGR00211038 Fix the PAD_LVE implementationMahesh Mahadevan2012-05-30-2/+2
| | | | | | Fix the PAD_LVE implementation used on MX6SL. Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@freescale.com>
* ENGR00210918-2 cleanup android support, build pass all boardsZhang Jiejing2012-05-29-367/+220
| | | | | | | | | | - move recovery.h to common inlcude place. - move supported_reco_envs to soc related, not board related, - user can change this via configure header, don't needs this in every board file. - pass build for all mx5/mx6 android configs. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00210918-1 android: add mx6sl android supportZhang Jiejing2012-05-29-5/+116
| | | | | | | | | | - add android build config for mx6sl_arm2 board. - add gpio support for mx6sl - add boot image support - add android recovery support - add fastboot support, but fastboot cannot transfer file. Signed-off-by Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00209910 Add support for MX6SL mfgtools firmware supportFrank Li2012-05-21-0/+288
| | | | | | Add support for MX6SL mfgtools firmware support Signed-off-by: Frank Li <Frank.Li@freescale.com>
* ENGR00209899-2 MX6Q: cleanup: cleanup fastboot, udc warnning.Zhang Jiejing2012-05-21-5/+14
| | | | | | cleanup android fastboot and udc build warnnings. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00209899-1 mx6x: add generic gpio interface.Zhang Jiejing2012-05-21-44/+210
| | | | | | | | | | | | | | | | | | | | | | Add generic gpio interface in uboot. Seems more and more gpio operation invoke in uboot, without RAW register operation, we should use generic gpio interface. you should define the CONFIG_MXC_GPIO use generic gpio interface: gpio_request, gpio_direction_output, gpio_direction_input, gpio_set_value, gpio_get_value, etc. Test on MX6Q, MX6DL. Other MX6X should also define this config. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00210014 i.mx6 : i.mx6sl : add PAD_CTL_LVE support for pad configurationEric Sun2012-05-18-7/+14
| | | | | | | | | | | Original pad configuration don't provide enough bitfield width to hold all necessary information. For MX6Sololite, a "PAD_CTL_LVE" is needed to be configed for many pins. iomux_v3_cfg_t is re-orgnized to address this issue. PAD_CTRL is extended by 1 bit to hold the "PAD_CTL_LVE". Which is mapped to proper bit location when configure the PAD config register. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
generated by cgit v1.1 at 2024-12-18 02:17:34 +0000