summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* MX: Added Freescale Power Management DriverStefano Babic2012-04-20-0/+329
| | | | | | | | | The patch add supports for the Freescale's Power Management Controller (known as Atlas) used together with i.MX31/51 processors. It was tested with a MC13783 (MX31) and MC13892 (MX51). Signed-off-by: Stefano Babic <sbabic@denx.de>
* ENGR00179762: i.MX6: print the SOC revision correctlyJason Liu2012-04-18-4/+11
| | | | | | | | | | For example: The soc rev on i.mx6dl rev 1.0 not print correctly: CPU: Freescale i.MX 6 family 0.0V at 792 MHz This patch help u-boot print out the SOC revision correctly: CPU: Freescale i.MX6 family TO1.0 at 792 MHz Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00179013 : MX6Solo/Quad : SABREAUTO: Add Parallel NOR SupportPrabhu Sundararaj2012-04-13-11/+179
| | | | | | | | | | | | | -Added u-boot config CONFIG_CMD_WEIMNOR for MX6Solo/Quad SABREAUTO to support WEIM NOR. - CONFIG_FLASH_HEADER_OFFSET is 0x1000 for WEIM NOR. -SPI NOR and WEIM NOR has pin conflicts, either one can be enabled. - mx6q_sabreauto_config, mx6solo_sabreauto_config configured default for SPI NOR. -In order to enable the read/write commands and to boot from WEIM NOR, need to enable the CONFIG_CMD_WEIMNOR. This will disable SPI-NOR Signed-off-by: Prabhu Sundararaj <b36876@freescale.com>
* ENGR00179000 i.mx6q/dl: sabresd: Add the splash screen supportJason Liu2012-04-13-102/+17
| | | | | | | | | | | | | | | | | | | | This patch will add the splash screen support for the i.mx6q/dl splash screen support. In order to enable the splash screen, you need make sure the following env variable has been set correctly: splashimage=0x30000000 splashpos=m,m lvds_num=0 The splash screen is default OFF, to enable it, please add: on i.mx6dq sabresd platform: define CONFIG_SPLASH_SCREEN in include/configs/mx6q_sabresd.h or on i.mx6dl sabresd platform: define CONFIG_SPLASH_SCREEN in include/configs/mx6dl_sabresd.h Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00179437-2 u-boot: mx6q: iomux: code clean upimx-android-r13.2.1imx_v2009.08Jason Liu2012-04-13-16/+1
| | | | | | | Remove the dead definiton which never used by iomux-v3 framework And move the SION bit definiton to arch-mx6/iomux-v3.h for sharing Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00179437-1: u-boot: iomux: NO_PAD_I/NO_PAD_MUX not set corretlyJason Liu2012-04-13-4/+4
| | | | | | | | NO_PAD_I/NO_PAD_MUX not defined correctly, which will cause build error. And According to iomux-v3.h, the NO_PAD_I/NO_PAD_MUX should be 0 for the pins which does not have PAD/MUX config. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00179150 MX6Q_ARM2 HAB Boot : avoid uImage authentication on un-fused chipEric Sun2012-04-09-25/+81
| | | | | | | | | Before running authentication on uImage in DDR, u-boot first check if SEC_CONFIG[1] (OTP_CFG5[1]) is burned. If so, it means the chip is in secure configuration, the authentication continues; if not, the chip in not in secure configuration, just bypass the authentication Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00176537 mx6qsabreauto: i2c3_sda route settingAdrian Alonso2012-04-05-2/+24
| | | | | | | | | | * In RevB boards a steer logic circuit enables the route path of I2C3_SDA signal and is controlled by EIM_A24__GPIO_5_4 pad. * Configure GPIO_5_4 as as output and enable steer logic circuit. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* ENGR00178989: Disable secrity boot configs.Terry Lv2012-04-05-1/+3
| | | | | | | Security boot need to use fuse item. Thus it should not be enabled as default. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139223-2 [MX6Q] Secure Boot, enable HAB on ARM2 platform (Stage 2)Eric Sun2012-04-01-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | authenticate_image is called to verify uImage when excecuting "bootm", the uImage togehter with its CSF data should has been located in DDR. The new uImage layout is as the following: +------------+ 0x0 (0x10800000) \ | Header | | +------------+ 0x40 | | | | | | | | | | | | | | Image Data | | . | | . | > Stuff to be authenticated ------+ . | | | | | | | | | | | +------------+ | | | | | | | Fill Data | | | | | | | +------------+ 0x003F_DFE0 | | | IVT | | | +------------+ 0x003F_E000 / | | | | | CSF DATA | <--------------------------------------------------------+ | | +------------+ | | | Fill Data | | | +------------+ 0x0040_0000 Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00139223-1 [MX6Q] Secure Boot, enable HAB on ARM2 platform (Stage 1)Eric Sun2012-04-01-2/+221
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first stage of High Assurance Boot (HAB) is the authentication of U-boot. A CST tool is used to generate the CSF data, which include public key, certificate and instruction of authentication process. Then it is attached to the original u-boot.bin The IVT should be modified to contain a pointer to the CSF data. The original u-boot.bin is with size between 0x27000 to 0x28000. For convinence, we first extend the u-boot.bin to 0x2F000 (with fill 0xFF). Then concatenate it with the CSF data. The combined image is again extend to a fixed length (0x31000), which is used as the IVT size parameter. The new memory layout is as the following. U-Boot Image +-------------+ | Blank | |-------------| 0x400 | IVT |-----------------------+ |-------------| | | | | | | | | | | |Remaining UB | | CSF pointer | | | | | | | | | |-------------| | | | | | Fill Data | | | | | |-------------| 0x2F000 <-------------+ | | | CSF Data | | | |-------------| | | | Fill Data | | | +-------------+ 0x31000 HAB APIs are ROM implemented, the entry table is located in a fixed location in the ROM. We export them so that during the HAB we can have some information about the secure boot process. For convinience some wrapper API is implemented based on the HAB APIs. - get_hab_status : used to dump information of authentication result - authenticate_image : used by u-boot to authenticate uImage For security hardware to function, CAAM related clock (CG0[4~6]) must be open. They are default closed in the original U-boot. "hab_caam_clock_enable" and "hab_caam_clock_disable" are created to open and close these clock gates. The generation of CSF data is not in the scope of this patch. CST tool will be used for this purpose. The procedure will be introduced in another document. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00176837-4 - FEC:enable some macro define for all chipFugang Duan2012-03-31-1/+1
| | | | | | | | | | | | | - Enable below macro define for all chip. Firstly, the marcos will be used in later version for later i.MX. Secondly, fix the build error in the former i.MX series chip before i.MX6. #define PHY_MIPSCR_LINK_UP (0x1 << 10) #define PHY_MIPSCR_SPEED_MASK (0x3 << 14) #define PHY_MIPSCR_1000M (0x2 << 14) #define PHY_MIPSCR_100M (0x1 << 14) #define PHY_MIPSCR_FULL_DUPLEX (0x1 << 13) Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176834-4 - [imx]:add macro define to include chip head fileFugang Duan2012-03-31-1/+3
| | | | | | | - Different chip will include different head file, so add macro define to limit the use range. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00178558 mx6solo sabreauto: integrate DDR3 script V1.1Lily Zhang2012-03-30-95/+99
| | | | | | | | | This patch is used to integrate DDR3 script V1.1 of mx6solo sabreauto MX6DL_init_DDR3_400MHZ_32bit_sabre_1_1.inc under http://compass.freescale.net/livelink/livelink?func=ll&objid =225128962&objAction=browse&sort=name Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00178024 mx6solo sabreauto: add nosmp arm_freq=800 by defaultLily Zhang2012-03-30-2/+3
| | | | | | | Add "nosmp arm_freq=800" options for mx6solo sabreauto board by default Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00178547 i.mx6dl sabresd: add android config fileLin Fuzhen2012-03-30-0/+58
| | | | | | | add android config file; support booti fastboot command and etc. Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
* mmc: CMD7:MMC_CMD_SELECT_CARD response fixAjay Bhargav2012-03-29-1/+1
| | | | | | | | | | | | | As per JEDEC document JESD84-A441 (page 105) response for CMD7 (MMC_CMD_SELECT_CARD) response should be R1 instead of R1b. In uboot we never take MMC to disconnected state and on powerup its always ideal state which later goes to stand-by state. from document footnote: R1 while selecting from Stand-By State to Transfer State; R1b while selecting from Disconnected State to Programming State. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
* ENGR00177954 mx6solo sabreauto: remove MMDC1 settingrel_imx_3.0.15_12.03.00Lily Zhang2012-03-26-44/+39
| | | | | | | Remove MMDC1 setting from DDR script of mx6solo sabreauto if it's not used. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00177909: mx6q/mx6dl SabreSD: SPI-NOR flash not probed as expectedJason Liu2012-03-26-12/+12
| | | | | | | | | | | | SPI NOR flash(m25p32-vmw6tg) not probed and function as expected, this due to the lack of iomux pad config and incorrect CS line. This patch fix the above issue and also fix the mfg config file (For the code readable, I intent to omit the following checkpatch warning: in the iomux/mx6_pins.h WARNING: line over 80 characters) Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00177905 : i.mx6q sabresd: add fec auto discover phy configuration.Fugang Duan2012-03-26-1/+2
| | | | | | | | - i.mx6q sabresd revA ethernet phy addr is 0 (PHYADDRESS1-PHYADDRESS0:00) , but revB ethernet phy address is 0x1 (PHYADDRESS1-PHYADDRESS0:01). To avoid to change hardware, add auto discover phy address configuration. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00177783: i.mx6dl: sabresd revB: update DD3 init scriptJason Liu2012-03-23-38/+41
| | | | | | | | | Update the DDR3 script on i.mx6dl SabreSD revB board, the script got from: http://wiki.freescale.net/download/attachments/33954617/MX6DL_init_DDR3 _400MHz_64bit_1_2_For_SD_RevB.inc?version=1&modificationDate=1332495827000 Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00177657: Add mfg configs for mx6dl sabresd and mx6solo sabreautoTerry Lv2012-03-23-0/+589
| | | | | | Add mfg configs for mx6dl sabresd and mx6solo sabreauto. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00176837-4 - imx6solo sabreauto : remove Ethernet phy MICREL macro.Fugang Duan2012-03-22-1/+0
| | | | | | | - FEC detect phy OUID to check phy type, so remove MICREL macro in board config file. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176837-3 - FEC : detect phy ID to match the phy type.Fugang Duan2012-03-22-55/+95
| | | | | | | | - Add phy id macro definitions. - Add mxc_get_phy_ouid helper function. - Use phy ouid to check the phy type. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176837-2 - imx6 sabreauto : add i2c3 support for revb board.Fugang Duan2012-03-22-4/+8
| | | | | | - Add i2c3_SDA iomux config for the change of signal traces. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176837-1 - imx6 sabreauto : add net support for revb boards.Fugang Duan2012-03-22-11/+28
| | | | | | | - In imx6 sabreauto board REVB Ethernet phy adopt AR8031. Add phy init rework. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00177587 MX6Q_ARM2: add android config for this board.Zhang Jiejing2012-03-22-1/+85
| | | | | | | add android config to this board. only basic boot support. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00177244 - imx6 : Use common fsl_sys_rev to check board reversionFugang Duan2012-03-20-54/+17
| | | | | | | | | - Use fsl_sys_rev to check Sebreauto board reversion. - Add macro define for expedient print the board and chip name. mx6_chip_name() mx6_board_rev_name() Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176834-3 - i.MX6DL sabresd : DDR init script updateFugang Duan2012-03-20-10/+10
| | | | | | | | | | | Use the ddr init script “MX6DL_init_DDR3_400MHz_64bit_1.2.inc” for SD revB with Rigel mounted, and update the calibration parameters (write leveling, DQS gating, read delay, write delay), which is located at: http://compass.freescale.net/livelink/livelink?func=ll& objid=225128962&objAction=browse&sort=name Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176834-2 - i.MX6DL sabresd: board bringupFugang Duan2012-03-20-26/+627
| | | | | | | | | | | | | The serial of patches adds the initial support for mx6dl sabra sd board: - DDR3 400MHz@64bit, 1G, 256M*4 - SD/MMC basic operations - Add PIN/IOMUX support for mmx6dl sabresd. - Ethernet is ok for 100/1000Mbps. - OTP fuse Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176834-1 - [imx6] : add fsl_system_rev to check chip and board.Fugang Duan2012-03-20-1/+136
| | | | | | | | | | | | | | | - Add fsl_system_rev to distinguish chip ID and board reversion. - Add some api: mx6_chip_is_dq() mx6_chip_is_dl() mx6_chip_is_solo() mx6_chip_is_sololite() mx6_board_is_reva() mx6_board_is_revb() mx6_board_is_revc() Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00177070 android: isolate booti command to fix build.Zhang Jiejing2012-03-16-1/+7
| | | | | | | | | | fix build error invoke by this patch: commit e3303f5b59df570c1f76b043d85e42be3dc7a63f Author: Lily Zhang <r58066@freescale.com> Date: Fri Mar 9 21:16:51 2012 +0800 Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00176347-9 fec : increase wait time for phy linkFugang Duan2012-03-13-21/+7
| | | | | | | | | | | | | | - remove the excrescent code in enet_board_init function. - KSZ9021 phy auto-negotiation in mx6solo sabreauto RevA is used to establish link with the remote hub or switch. In general, the negotiation time is about 3-5 senconds But connecting to Gbps hub, the time is range from 8s to 15s. So, changing the MAX link waiting time to 20s. According to repetitious tests, solo ARD ethernet is ok in 100Mbps environment. It is not stable in 1000Mbps mode. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176347-8 cmd_bootm: remove build warningLily Zhang2012-03-13-5/+4
| | | | | | | | | | | | | Remove the following build warning: cmd_bootm.c: In function 'do_booti': cmd_bootm.c:1524: warning: unused variable 'partno' cmd_bootm.c:1520: warning: unused variable 'pte' cmd_bootm.c:1654: warning: implicit declaration of function 'do_booti_linux' cmd_bootm.c:1596: warning: 'info.start' may be used uninitialized in this function cmd_bootm.c:1502: warning: 'addr' may be used uninitialized in this function Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176347-7 bootm: remove build warningLily Zhang2012-03-13-1/+1
| | | | | | | | Remove the following build warning: bootm.c: In function 'do_booti_linux': bootm.c:147: warning: pointer targets in assignment differ in signedness Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176347-6 mx6solo sabreauto: remove build warningLily Zhang2012-03-13-2/+5
| | | | | | | | | | Remove the following build warning: mx6q_sabreauto.c: In function 'enet_board_init': mx6q_sabreauto.c:999: warning: unused variable 'reg' mx6q_sabreauto.c: At top level: mx6q_sabreauto.c:921: warning: 'phy_read' defined but not used Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176347-5 mx6solo sabreauto: set system_revLily Zhang2012-03-13-12/+59
| | | | | | | | | | | | | | | | | Add set_system_rev function. The layout of system_rev is: bit 0-7: Chip Revision ID. Read from Anatop register bit 8-11: Board Revision ID. Read from fuse OCOTP_GP1[15:8] 1: RevA Board 0: RevB board, Unknown board bit 12-19: Chip Silicon ID. Read from Anatop register 0x63: i.MX 6Dual/Quad 0x61: i.MX 6Solo/DualLite board_is_rev(system_rev,BOARD_REV_1) can be used to distinguish RevB board. board_is_rev(system_rev,BOARD_REV_2) is for RevA board. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176347-4 anatop: add support for mx6solo/dlLily Zhang2012-03-13-1/+1
| | | | | | Enable anatop command "regul" for mx6solo/DL Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176347-3 mx6solo sabreauto: add board supportLily Zhang2012-03-13-28/+162
| | | | | | | | - Add PIN/IOMUX support for mx6solo sabreauto board - Remove GPIO_9 codes because GPIO_9 is not the backlight - change system_rev as 0x610000 Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176347-2 mx6solo sabreauto: add DDR3 supportLily Zhang2012-03-13-2/+109
| | | | | | | | Add DDR3 script (400MHz@32 bit) in mx6solo sabre auto board. MX6Solo_DDR3_400MHZ_32bit.inc was delivered on Mar 7, 2012 by Fan Chongbin-B32609 Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176347-1 mx6solo sabreauto: add configuration supportLily Zhang2012-03-13-0/+329
| | | | | | | | | | | | | | | | | | | | The serial of patches adds the initial support for mx6solo sabra auto board: - DDR3 400MHz@32bit - SD/MMC basic operations - SPI-NOR basic operations - OTP fuse - clock command - Anatop regulator command - splash screen support by enabling "CONFIG_SPLASH_SCREEN" Because i.mx6solo share the same ARD board with i.mx6dq, the same board file is shared between i.mx6dq and i.mx6solo. CONFIG_MX6DL configuration is used to distinguish the difference. This patch is used to add mx6solo sabreauto configuration support. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176328 change fastboot vid to google orignalZhang Jiejing2012-03-07-5/+5
| | | | | | | Change fastboot vender id to orignal ID to avoid install USB driver. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00176235 mx6 ARD: Add splash screen supportLily Zhang2012-03-06-7/+7
| | | | | | | | | | | | | | | | | | | This patch adds splash screen support for MX6 ARD. Changes: - Configure GPIO_3 as I2C3_SCL - Change MAX7310 I2C address as 0x30 - Enable LVDS power Usage: 1. To enable splash screen by default, define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h 2. Config U-boot with followed command:() setenv splashimage '0x30000000' #Set splash position as Center setenv splashpos 'm,m' #Set LVDS via LVDS bridge 0 setenv lvds_num 0 Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00176186 mx6dq ARD: add MFG tool supportLily Zhang2012-03-06-8/+301
| | | | | | Add MFG tool support for i.MX6DQ ARD board Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00175981-2 mx53 smd android: fix build errorLily Zhang2012-03-02-1/+1
| | | | | | | | | Fix the following build error when building mx53_smd_android config: mx53_smd_android.h:175: error: expected identifier or xx before string constant Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00175981-1 mx53 smd: add CPU 1.2GHz configurationLily Zhang2012-03-02-3/+20
| | | | | | | | | CONFIG_CPU_1_2G is used to enable 1.2GHz@1.3V. To enable 1.2GHz by default, enable CONFIG_CPU_1_2G into config file. For example, uncomment CONFIG_CPU_1_2G in mx53_smd.h or mx53_smd_android.h. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00175117 [MX6DL LPDDR2 Board] Apply Initializtion script and enable U-BootEric Sun2012-02-29-1/+627
| | | | | | | | | | | | | | | | | Apply script "Mx6DL_init_LPDDR2_400MHz_Micron_1.1.inc" in IVT, make U-boot work for the LPDDR2 Board. The Make target name for the new board is "MX6DL_ARM2_LPDDR2_CONFIG" The script is provided by Chen Wei - B26879 for a quick bring up, which don't have a corresponding compass link. It is uploaded to CR ticket page for reference. Originally for MX6DL DDR3 board, "CONFIG_MX6DL" is defined. It is used by "board/freescale/mx6q_arm2/flash_header.S" to select the correct IVT. Since MX6DL LPDDR2 board also define this macro, for distiguish purpose, another 2 macros "CONFIG_MX6DL_DDR3", "CONFIG_MX6DL_LDPPR2" are defined Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00175091 MX6Q_SABRESD: android: add recovery checkZhang Jiejing2012-02-27-39/+41
| | | | | | | | define a new macro to show which mmc bus was main storage in recovery check, only check the main storage /cache partition. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00174868 mx6dl arm2: change the default console as ttymxc3Lily Zhang2012-02-27-1/+1
| | | | | | | The default console on i.MX6DL ARM2 CPU board is ttymxc3 Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00174841 [U-Boot]Add a command to erase any pre-saved environmentEric Sun2012-02-27-30/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A "destroyenv" command is provided to erase any pre-save environment in the boot storage. The command simply add 1 to the CRC section and write it back to the storage. Per the logic of U-Boot, this means after a reset, the software will recognize the stored environment settings as "damaged" and turn to use the default one, which is defined in "default_environment" With this command, platform bring up owner can maintain a "ready-to-use" environment settings in software which others can use very conviniently. U-boot users can also use it to do a environment restore if they want. ----------------------------------- Usage Example: > destroyenv invalidate the CRC write invalidate enviroment data to storage Erasing SPI flash...Erasing SPI NOR flash 0xc0000 [0x2000 bytes] ..SUCCESS Writing to SPI flash...Writing SPI NOR flash 0xc0000 [0x2000 bytes] <- ram 0x276009b8 SUCCESS done > ----------------------------------- Signed-off-by: Eric Sun <jian.sun@freescale.com>
generated by cgit v1.1 at 2024-11-26 00:02:16 +0000