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* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-08-02-1/+7
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| * Fix breakage of 8xx boards from recent commit.Rafal Jaworowski2007-07-19-1/+7
| | | | | | | | | | | | | | This patch fixes the negative consequences for 8xx of the recent "ppc4xx: Clean up 440 exceptions handling" commit. Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* | ppc4xx: Code cleanupStefan Roese2007-08-02-1/+1
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | [ppc440SPe] Graceful recovery from machine check during PCIe configurationGrzegorz Bernacki2007-08-02-10/+58
| | | | | | | | | | | | | | | | | | | | | | During config transactions on the PCIe bus an attempt to scan for a non-existent device can lead to a machine check exception with certain peripheral devices. In order to avoid crashing in such scenarios the instrumented versions of the config cycle read routines are introduced, so the exceptions fixups framework can gracefully recover. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Rafal Jaworowski <raj@semihalf.com>
* | [ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.ARafal Jaworowski2007-08-02-3/+8
| | | | | | | | | | | | | | | | | | This brings back separate settings for PCIe bus numbers depending on chip revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa commit. 440SPe rev. A does NOT work properly with the same settings as for the rev. B (no devices are seen on the bus during enumeration). Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* | ppc4xx: Update AMCC Bamboo 440EP supportEugene OBrien2007-07-31-110/+248
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changed storage type of cfg_simulate_spd_eeprom to const Changed storage type of gpio_tab to stack storage (Cannot access global data declarations in .bss until afer code relocation) Improved SDRAM tests to catch problems where data is not uniquely addressable (e.g. incorrectly programmed SDRAM row or columns) Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules Fixed AM29LV320DT (OpCode Flash) sector map Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Update 440EPx lwmon5 board supportStefan Roese2007-07-31-27/+38
| | | | | | | | | | | | | | | | - Clear ECC status regs after ECC POST test - Set dcbz for ECC generation with caches enabled as default - Code cleanup Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Only print ECC related info when the error bis are setStefan Roese2007-07-30-14/+24
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | new FPGA image for PLU405 boardMatthias Fuchs2007-07-28-1160/+1179
| | | | | | | | | | | | new FPGA image for PLU405 board with improved CompactFlash timing Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | ppc4xx: lwmon5: Update Lime initializationAnatolij Gustschin2007-07-26-5/+73
| | | | | | | | | | | | | | | | | | Change Lime SDRAM initialization to now support 100MHz and 133MHz (if enabled). Also the framebuffer is initialized to display a blue rectangle with a white border. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: lwmon5: Support for 128 MByte NOR FLASH addedStefan Roese2007-07-24-6/+8
| | | | | | | | | | | | | | The used Intel NOR FLASH chips have internally two dies, and are now treated as two seperate chips. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix lwmon5 interrupt controller setup (polarity, trigger...)Stefan Roese2007-07-24-6/+6
| | | | | | | | | | | | | | As suggested by Hakan Eryigit, here an updated setup for the lwmon5 interrupt controller. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix bug with default GPIO output valueStefan Roese2007-07-20-2/+2
| | | | | | | | | | | | | | As spotted by Matthias Fuchs, the default output values for all GPIO1 outputs were not setup correctly. This patch fixes this issue. Signed-off-by: Stefan Roese <sr@denx.de>
* | POST: Add ECC POST for the lwmon5 boardPavel Kolesnikov2007-07-20-1/+318
| | | | | | | | | | | | | | | | | | This patch adds ECC Post test for the Lwmon5 board based on PPC440EPx to U-Boot. Signed-off-by: Pavel Kolesnikov <concord@emcraft.com> Acked-by: Yuri Tikhonov <yur@emcraft.com> Acked-by: Stefan Roese <sr@denx.de>
* | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-07-16-307/+1836
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| * Update CHANGELOGWolfgang Denk2007-07-14-0/+31
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Merge with /home/hs/Atronic/u-boot-dev-newHeiko Schocher2007-07-14-279/+188
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| | * make show_boot_progress () weak.Heiko Schocher2007-07-13-276/+173
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * [PCS440EP] - The DIAG LEDs are now blinking, if an error occurHeiko Schocher2007-07-13-4/+16
| | | | | | | | | | | | | | | | | | - fix compile error, if BUILD_DIR is used Signed-off-by: Heiko Schocher <hs@denx.de>
| * | [PCS440EP] - fix compile error, if BUILD_DIR is usedHeiko Schocher2007-07-14-1/+1
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| * Update CHANGELOG, minor coding style cleanup.Wolfgang Denk2007-07-12-6/+34
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Merge with /home/tur/git/u-boot#cm1_qp1Wolfgang Denk2007-07-12-13/+1487
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| | * CM1.QP1: Support for the Schindler CM1.QP1 board.Bartlomiej Sieka2007-07-11-13/+1487
| | | | | | | | | | | | | | | Signed-off-by: Piotr Kruszynski <ppk@semihalf.com> Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
| * | [PCS440EP] - Show on the DIAG LEDs, if the SHA1 check failedHeiko Schocher2007-07-11-14/+101
| | | | | | | | | | | | | | | | | | | | | | | | - now the Flash ST M29W040B is supported (not tested) - fix the "led" command - fix compile error, if BUILD_DIR is used Signed-off-by: Heiko Schocher <hs@denx.de>
* | | ppc4xx: Code cleanupStefan Roese2007-07-16-2/+0
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: AMCC Luan uses the new boardspecific DDR2 controller setupStefan Roese2007-07-16-1/+7
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.cStefan Roese2007-07-16-0/+34
| | | | | | | | | | | | | | | | | | | | | The new boardspecific DDR2 controller configuration is used for the Yucca board. Now the Yucca board with 440SPe Rev. A chips is also supported. Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Add new weak functions to support boardspecific DDR2 configurationStefan Roese2007-07-16-14/+44
| | | | | | | | | | | | | | | | | | | | | The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better support non default, boardspecific DDR(2) controller configuration. Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Add remove_tlb() function to remove a mem area from TLB setupStefan Roese2007-07-16-1/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new function remove_tlb() can be used to remove the TLB's used to map a specific memory region. This is especially useful for the DDR(2) setup routines which configure the SDRAM area temporarily as a cached area (for speedup on auto-calibration and ECC generation) and later need this area uncached for normal usage. Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Change receive buffer handling in the 4xx emac driverStefan Roese2007-07-12-3/+5
| | | | | | | | | | | | | | | | | | | | | This change fixes a bug in the receive buffer handling, that could lead to problems upon high network traffic (broadcasts...). Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-07-11-214/+1958
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| * | Coding style cleanup; update CHANGELOG.Wolfgang Denk2007-07-10-388/+716
| | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | Merge with /home/hs/Atronic/u-bootWolfgang Denk2007-07-09-160/+1576
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| | * [PCS440EP] get rid of CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANGHeiko Schocher2007-06-25-57/+58
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * [PCS440EP] upgrade the PCS440EP board:Heiko Schocher2007-06-22-160/+1575
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Show on the Status LEDs, some States of the board. - Get the MAC addresses from the EEProm - use PREBOOT - use the CF on the board. - check the U-Boot image in the Flash with a SHA1 checksum. - use dynamic TLB entries generation for the SDRAM Signed-off-by: Heiko Schocher <hs@denx.de>
* | | ppc4xx: Update lwmon5 default environmentStefan Roese2007-07-06-0/+2
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Update lwmon5 boardStefan Roese2007-07-06-0/+1
|/ / | | | | | | | | | | | | Add unlock=yes environment variable to default variables to unlock the CFI flash by default. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-07-06-113/+1861
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| * | Merged POST framework with the current TOT.Sergei Poselenov2007-07-05-29/+1766
| | | | | | | | | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
| * | resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPXNiklaus Giger2007-07-04-74/+8
| | | | | | | | | | | | Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
| * | ppc4xx: Update lwmon5 boardStefan Roese2007-07-04-10/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add optional ECC generation routine to preserve existing RAM values. This is needed for the Linux log-buffer support - Add optional DDR2 setup with CL=4 - GPIO50 not used anymore - Lime register setup added Signed-off-by: Stefan Roese <sr@denx.de>
* | | Code cleanup and default config update for STC GP3 SSA board.Wolfgang Denk2007-07-06-200/+200
|/ / | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge with /home/wd/git/u-boot/custodian/u-boot-testingWolfgang Denk2007-07-03-178/+1293
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| * | Fix S-ATA support.Mushtaq Khan2007-06-30-12/+12
| | | | | | | | | | | | Signed-off-by: mushtaq khan <mushtaqk_921@yahoo.co.in>
| * | Add LIST_86xx MAKEALL target for PowerPC builds.Jon Loeliger2007-05-23-1/+10
| | | | | | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * | Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECxKim Phillips2007-05-17-144/+119
| | | | | | | | | | | | | | | | | | | | | For all practical u-boot purposes, TSECs don't differ throughout the mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | Merge with /home/git/u-bootWolfgang Denk2007-05-17-355/+2789
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| * | | Minor coding style cleanup.Wolfgang Denk2007-05-15-53/+55
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| * | | Add driver for S-ATA-controller on Intel processors with Southmushtaq khan2007-05-15-3/+1106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bridge, ICH-5, ICH-6 and ICH-7. Implementation: 1. Code is divided in to two files. All functions, which are controller specific are kept in "drivers/ata_piix.c" file and functions, which are not controller specific, are kept in "common/cmd_sata.c" file. 2. Reading and Writing from the S-ATA drive is done using PIO method. 3. Driver can be configured for 48-bit addressing by defining macro CONFIG_LBA48, if this macro is not defined driver uses the 28-bit addressing. 4. S-ATA read function is hooked to the File system, commands like ext2ls and ext2load file can be used. This has been tested. 5. U-Boot command "SATA_init" is added, which initializes the S-ATA controller and identifies the S-ATA drives connected to it. 6. U-Boot command "sata" is added, which is used to read/write, print partition table and get info about the drives present. This I have implemented in same way as "ide" command is implemented in U-Boot. 7. This driver is for S-ATA in native mode. 8. This driver does not support the Native command queuing and Hot-plugging. Signed-off-by: Mushtaq Khan <mushtaq_k@procsys.com>
| * | | Fixes bug clearing the bss section for i386mushtaq khan2007-05-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, There is a bug in the code of clearing the bss section for processor i386.(File: cpu/i386/start.S) In the code, bss_start addr (starting addr of bss section) is put into the register %eax, but the code which clears the bss section refers to the addr pointed by %edi. This patch fixes this bug by putting bss_start into %edi register. Signed-off-by: Mushtaq Khan <mushtaq_k@procsys.com>
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