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* ppc4xx: Add 405 support to 4xx NAND driver ndfc.cStefan Roese2007-05-22-4/+4
| | | | | | | This patch adds support for 405 PPC's to the 4xx NAND driver ndfc.c. This is in preparation for the new AMCC 405EZ. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix problem in 405EZ OCM initializationStefan Roese2007-05-21-1/+1
| | | | | | | As spotted by Bruce Adler this patch fixes an initialization problem for the 405EZ OCM. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-05-18-838/+2907
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| * Fix compile problem cause my Microblaze mergeStefano Babic2007-05-16-1/+1
| | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * Minor Coding Style cleanup, update CHANGELOG.Wolfgang Denk2007-05-16-24/+140
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xxWolfgang Denk2007-05-16-75/+1686
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| | * mpc83xx: fix trivial error in MAKEALLKim Phillips2007-05-03-2/+2
| | | | | | | | | | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * Fix memory initialization on MPC8349E-mITXTimur Tabi2007-05-01-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Michael Benedict <MBenedict@twacs.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * mpc83xx: replace elaborate boottime verbosity with 'clocks' commandKim Phillips2007-05-01-11/+13
| | | | | | | | | | | | | | | | | | and fix CPU: to align with Board: display text. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * mpc83xx: minor fixups for 8313rdb introductionKim Phillips2007-04-25-17/+18
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| | * mpc83xx: Add MPC8313ERDB support.Scott Wood2007-04-23-0/+1088
| | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * mpc83xx: Add generic PCI setup code.Scott Wood2007-04-23-1/+197
| | | | | | | | | | | | | | | | | | | | | | | | Board code can now request the generic setup code rather than having to copy-and-paste it for themselves. Boards should be converted to use this once they're tested with it. Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * mpc83xx: Add 831x support to speed.c.Scott Wood2007-04-23-26/+42
| | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * mpc83xx: Add 831x support to global_data.hScott Wood2007-04-23-2/+4
| | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * mpc83xx: Change PVR_83xx to PVR_E300C1-3, and update checkcpu().Scott Wood2007-04-23-17/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than misleadingly define PVR_83xx as the specific type of 83xx being built for, the PVR of each core revision is defined. checkcpu() now prints the core that it detects, rather than aborting if it doesn't find what it thinks it wants. Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * mpc83xx: Recognize SPR values for MPC8311 and MPC8313.Scott Wood2007-04-23-0/+12
| | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * mpc83xx: Add register definitions for MPC831x.Scott Wood2007-04-23-7/+301
| | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * Merge git://www.denx.de/git/u-bootKim Phillips2007-04-23-5537/+40454
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| | * | Fix two bugs for MPC83xx DDR2 controller SPD InitXie Xiaobo2007-04-12-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a few bugs in the cpu/mpc83xx/spd_sdram.c the first bug is that the picos_to_clk routine introduces a huge rounding error in 83xx. the second bug is that the mode register write recovery field is tWR-1, not tWR >> 1.
| * | | Coding Style Cleanup, new CHANGELOGWolfgang Denk2007-05-16-3/+255
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| * | | Merge with /home/wd/git/u-boot/custodian/u-boot-microblazeWolfgang Denk2007-05-16-280/+735
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| | * | | add: reading special purpose registersMichal Simek2007-05-08-23/+41
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| | * | | add: Microblaze V5 exception handlingMichal Simek2007-05-08-2/+17
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| | * | | add: FSL control read and writeMichal Simek2007-05-08-72/+210
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| | * | | Merge git://www.denx.de/git/u-bootMichal Simek2007-05-08-9449/+50773
| | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: include/asm-microblaze/microblaze_intc.h include/linux/stat.h
| | * | | | new: USE_MSR_INTR supportMichal Simek2007-05-07-7/+60
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| | * | | | fix: read and write MSR - repair number of parametersMichal Simek2007-05-07-1/+1
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| | * | | | new: fsl interrupt supportMichal Simek2007-05-07-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | FSL_Has_data is connected to INTC.
| | * | | | fix: interrupt handlerMichal Simek2007-05-07-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | remove asm code
| | * | | | fix: remove asm codeMichal Simek2007-05-07-223/+17
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| | * | | | fix: clean interruptMichal Simek2007-05-07-3/+13
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| | * | | | fix: interrupt handler for multiple sourcesMichal Simek2007-05-07-10/+15
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| | * | | | new: add writing to msr registerMichal Simek2007-05-07-22/+38
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| | * | | | new: FSL and MSR support #2Michal Simek2007-05-05-1/+10
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| | * | | | new: FSL and MSR supportMichal Simek2007-05-05-0/+302
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| | * | | | [PATCH] MTD partition support, JFFS2 supportMichal Simek2007-04-24-4/+30
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| | * | | | [PATCH] SystemACE support for MicroblazeMichal Simek2007-04-21-15/+31
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| | * | | | 16bit read/write little endianMichal Simek2007-04-21-0/+37
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| | * | | | Change ML401 parameters - Xilinx BSPMichal Simek2007-04-21-13/+13
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| * | | | | Merge with /home/wd/git/u-boot/masterWolfgang Denk2007-05-15-20/+118
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| | * \ \ \ \ Merge with /home/tur/git/u-boot#motionproWolfgang Denk2007-05-15-20/+118
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| | | * | | | [Motion-PRO] Add MTD and JFFS2 support, also add default partitionPiotr Kruszynski2007-05-10-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | definition.
| | | * | | | [Motion-PRO] Add support for I2C, EEPROM and RTC.Piotr Kruszynski2007-05-08-1/+29
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| | | * | | | [Motion-PRO] Add ATA support. Add CF-booting commands to the defaultBartlomiej Sieka2007-05-08-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | environment.
| | | * | | | [Motion-PRO] Change IPB clock frequency from 50MHz to 100MHz. ThisBartlomiej Sieka2007-05-08-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | eliminates networking problems in Linux (timeouts).
| | | * | | | [Motion-PRO] Enable Flat Device Tree support and modify default environmentBartlomiej Sieka2007-05-08-19/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | to allow booting of FDT-expecting kernels.
| | | * | | | [MPC5xxx] There are networking problems on the Motion-PRO board withBartlomiej Sieka2007-05-07-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | current PHY initalization code (tftp timeouts all the time). This commit temporarily disables PHY initalization sequence to make the networking operational, until a fix is found.
| * | | | | | Get rid of duplicated file (see include/configs/sbc8560.h instead)Wolfgang Denk2007-05-07-410/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | | | | Get rid of duplicated file (see doc/README.SBC8560 instead)Wolfgang Denk2007-05-07-53/+0
| |/ / / / / | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | | | | [PATCH] Run new sequoia boards with an EBC speed of 83MHzJeffrey Mann2007-05-16-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because the Sequoia board does not boot with an EBC faster than 66MHz, the clock divider are changed after the initial boot process. This allows for maximum clocking speeds to be achieved on newer boards. Sequoia boards with 666.66 MHz processors require that the EBC divider be set to 3 in order to start the initial boot process at a slower EBC speed. After the initial boot process, the divider can be set back to 2, which will cause the boards to run at 83.333MHz. This is backward compatible with boards with 533.33 MHz processors, as these boards will already be set with an EBC divider of 2. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
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