summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* ENGR00162642: Fix bug in setting VDDSOC voltagerel_imx_2.6.38_11.11.01imx_v2009.08_11.11.01Ranjani Vaidyanathan2011-11-18-2/+2
| | | | | | Fix incorrect VDDSOC voltage setting in uboot. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00162570: MX6-Increase VDDSOC_CAP voltage to 1.2VRanjani Vaidyanathan2011-11-17-0/+7
| | | | | | | | Set the VDDSOC LDO to increase the VDDSOC cap to 1.2V. This is required for correct functioning of GPU and when the ARM LDO is set to 1.225V (when ARM core is at 1GHz). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00155891 : Fix reboot stress test failed issueRobin Gong2011-11-16-258/+371
| | | | | | | | | | | | | | If we replace DCD mode with plug-in mode in u-boot , we found DDR not stable. We should enable "Force Measurement" after the delay line parameters is configured in the plug-in code, for example: 0x63fd9088 = 0x34333936 0x63fd9090 = 0x49434942 0x63fd90F8 = 0x00000800 "Force Measurement" update all of mx53 DDR script, include mx53_smd,mx53_loco,mx53_evk,mx53_ard, mx53_pcba, at the same time, mx53_pcba will change from DCD mode to plug-in mode in flash_header.S Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00161852: remove u-boot build warnings for mx6qTerry Lv2011-11-10-5/+12
| | | | | | Remove u-boot build warnings for mx6q. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00161860 Fix build issue when enable NAND in UbootAllen Xu2011-11-10-0/+1
| | | | | | Add the MACRO define CONFIG_APBH_DMA which missed in last commit Signed-off-by: Allen Xu <allen.xu@freescale.com>
* ENGR00161846 uboot mx6q_arm2: adjust IPU axi-id0/1 Qos valueJason Chen2011-11-10-6/+6
| | | | | | | | | set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7, mx6q use AXI-id0 for IPU display channel, it should has highest priority(bypass), and AXI-id1 for other IPU channel, it has high priority. Signed-off-by: Jason Chen <b02280@freescale.com>
* ENGR00161691 Manufacturing update for Sabre-liteMahesh Mahadevan2011-11-08-1/+266
| | | | | | Add support for the manufacturing tool on MX6 Sabre-lite Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00161354 MX6Q ARM2 U_BOOT: "mmc dev 0" or "mmc dev 1" cmds will hangAnish Trivedi2011-11-04-6/+10
| | | | | | | | Ungate the clocks to SD1 and SD2 ports (on baseboard of ARM2 system) so that the above cmds do not hang waiting for cmd to complete or timeout. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00161415: mc34708: set 1p5Robby Cai2011-11-04-2/+2
| | | | | | set charging current limit to 1p5 Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00157106 uboot mx6q: adjust IPU axi-id0/1 Qos valueJason Chen2011-11-04-3/+3
| | | | | | | | | set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7, mx6q use AXI-id0 for IPU display channel, it should has highest priority(bypass), and AXI-id1 for other IPU channel, it has high priority. Signed-off-by: Jason Chen <b02280@freescale.com>
* ENGR00161317 - MX6Q: Integrate plugin and dcd DRAM init script in uboot.Fugang Duan2011-11-04-0/+300
| | | | | | | | | - Add plugin DRAM init script in flash_header.S file. - Define CONFIG_FLASH_PLUG_IN in mx6q_sabreauto.h to switch plugin mode. - DDR support 528MHz and 480MHz in plugin mode. Switch DDR clock to 480M according to define CONFIG_IPG_40M_FR_PLL3. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00161373 Move the MAC address read from fuse code to MX6 SoC fileMahesh Mahadevan2011-11-03-59/+21
| | | | | | | Move the code to read the mac address from the fuse to SoC file and out of the board file Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00161296 Update the MX6 Sabre-lite environment option in the config fileMahesh Mahadevan2011-11-03-7/+20
| | | | | | | | Allow boot to either SD card through 6q_bootscript. Define clearenv command to restore factory defaults Add upgradeu command to upgrade u-boot if required Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00161254 MX6Q: Add NAND support in UbootAllen Xu2011-11-03-1/+91
| | | | | | | | Add iomux and clock setting in Uboot code to support NAND, due to the conflict between NAND and SD, NAND function is not enabled in default configuration. Signed-off-by: Allen Xu <allen.xu@freescale.com>
* ENGR00161294 Update MX6 code to read MAC address from fusesMahesh Mahadevan2011-11-02-9/+20
| | | | | | Fix the code to read the MAC address correctly from the fuses Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00161277 Add fuse access capability for MX6 Sabre-liteMahesh Mahadevan2011-11-02-4/+15
| | | | | | Add support to read and program fuses in the MX6 Sabre-lite Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00139215 iMX61 Uboot support blow fuseRyan QIAN2011-11-02-0/+846
| | | | | | | | 1. add force option to blow operation 2. add blown value check 3. add simple validation for zeros returned by 'simple_strtoul' call Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00161126 Enable Hush parser in MX6Q Sabrelite configMahesh Mahadevan2011-11-01-0/+4
| | | | | | | Enable the Hush parser in the Sabrelite config to parse boot scripts. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00161133: Add spi-nor support for mx6qTerry Lv2011-11-01-2/+83
| | | | | | Add spi-nor support for mx6q. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00161125 Update MX6Q Sabrelite config to boot from MMC by defaultMahesh Mahadevan2011-10-31-2/+2
| | | | | | Boot from MMC by default and disable DHCP by default on MX6Q Sabrelite Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00161004 MX6Q Uboot Rename sabreauto to arm2 boardAnish Trivedi2011-10-28-32/+48
| | | | | | | | | Sabreauto is an inaccurate name for the Armadillo2 board that this code is actually meant for. So, replaced "sabreauto" in folder names, file names, configs, and code with "arm2". Created a new machine id for ARM2 board. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00139221 USDHC Add SDXC UHS-I supportAnish Trivedi2011-10-27-26/+344
| | | | | | | Modified MMC library for UHS-I command sequence Added support to USDHC driver for UHS-I Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00160514: clean up compiler warning for mx6qTerry Lv2011-10-26-2/+3
| | | | | | Clean up compiler warning. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00160399 Added support for the MX6Q Sabre-lite boardMahesh Mahadevan2011-10-25-82/+1480
| | | | | | Includes support for uSDHC read, write, FEC, SPI-NOR etc. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00160725 fastboot: fix the serial number display errorXinyu Chen2011-10-25-1/+1
| | | | | | Incorrect usb string package size assign. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00160507 Update the IOMUX implementation for MX6Mahesh Mahadevan2011-10-20-6/+5
| | | | | | | The MX6 code incorrectly uses the Hysteresis bit to decide NO_PAD_CTRL operation Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00156934: Update mx35 AIPS max dbg m3if esdctl settingsTerry Lv2011-10-18-18/+32
| | | | | | | This patch is to fix mx35 TVIN flicker issue. It will change AIPS, M3IF, MAX, DBG and esdctl settings. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00156930: Update MX35 DDR2 scriptsTerry Lv2011-10-18-81/+451
| | | | | | | | | | Update MX35 DDR2 scripts for that when enabling 256MB, the CSD1 is not stable. 1. Add CSD1 configs to support 256M RAM. 2. Add mx35 TO2 256M RAM configs. 3. Update DDR init code in lowlevel_init.S for external boot. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139279-3 MX6Q: invalidate the D-CACHEHuang Shijie2011-10-14-0/+37
| | | | | | | | | | | The USB boot mode does not invalidate the D-CACHE, so the uboot will DEAD when it tries to invalidate the random data in the cache line. The MMC boot will do the MMU init which will do the D-CACHE invalidation. So the MMC boot will ok in the boot procedure. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00139279-2 MX6Q: add mfgtool supportHuang Shijie2011-10-14-0/+269
| | | | | | add the MFGTOOL support for mx6q. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00139279-1 MX6Q: add env_embedded module for CONFIG_ENV_IS_NOWHEREHuang Shijie2011-10-14-0/+1
| | | | | | | The env_embedded module is a built-in module. So add the module when the CONFIG_ENV_IS_NOWHERE is enabled. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00159845 [MX6]lpddr2 board, put MMDC into power saving modeAnson Huang2011-10-13-2/+10
| | | | | | | | For lpddr2 board. 1. Put mmdc into power saving mode; 2. Do the necessary setting for AXI cache and IPU Qos. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00159740 Android: Fastboot: enlarge max image size to 148MBZhang Jiejing2011-10-12-5/+5
| | | | | | | enlarge max image size to 148MB from 128MB. since android become bigger. so 128M not enough. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00159696 [MX6]Enable lpddr2 boardAnson Huang2011-10-11-0/+452
| | | | | | | And new config to enable lpddr2 board with H9TKNNN4KDMPQR-NDM chip. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00158184 mx53 smd: use highest value for unknown board revision valueWayne Zou2011-09-26-1/+5
| | | | | | mx53 smd: use highest value for unknown board revision value Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00157538 remove VDIG_PLL setting in plug-in codeLily Zhang2011-09-23-20/+0
| | | | | | | | According to the datasheet, VDIG_PLL needs to be increased to 1.3v for TO2.0. This operation has been done in the low_level_init.S. Remove the duplicated code here. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00157468: Fix default environment's "mmc dev" type errorTerry Lv2011-09-23-14/+14
| | | | | | | Some semicolons are missed after "mmc dev 0". They need to be added to make default environment work. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00157419: Correct default environment's mmc device in mx6qTerry Lv2011-09-22-1/+1
| | | | | | | Default environment in mx6q uses mmc device 0. We should use mmc device 3. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155569 mc34708: change global reset time as 4s of LOCO and PCBARobin Gong2011-09-19-0/+22
| | | | | | reduce the time of global reset to 4s in the boards of loco and pcba Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00156670-2 MMC: Fixed some bugs in common codeAnish Trivedi2011-09-13-2/+2
| | | | | | | | | | | | | Need to send RCA when sending CMD13. Cannot use print_size function when displaying card capacity because it expects a 32 bit integer as input, while mmc->capacity is a 64 bit integer. There is loss of information leading to incorrect capacities being displayed for "mmcinfo" cmd. Changed it to simply print the entire 64 bit integer, which is the number of bytes. Signed-off-by: Tony Lin <tony.lin@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00156670-1 ESDHC/USDHC: Remove delay before each cmd and some bug fixesAnish Trivedi2011-09-13-8/+13
| | | | | | | | | | | | Removed delay of 10 ms before each command. There should not be a need to have this delay after the ENGR00156405 patch that polls until card is not busy anymore before proceeding to next cmd. Added poll on reset bits of controller after the bits are set to wait until they clear before proceeding further. Signed-off-by: Tony Lin <tony.lin@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00156405 ESDHC: Add workaround for auto-clock gate errata ENGcm03648Anish Trivedi2011-09-13-2/+34
| | | | | | | | | | | | The errata, not applicable to USDHC, causes ESDHC to shut off clock to the card when auto-clock gating is enabled for commands with busy signalling and no data phase. The card might require the clock to exit the busy state, so the workaround is to disable the auto-clock gate bits in SYSCTL register for such commands. The workaround also entails polling on DAT0 bit in the PRSSTAT register to learn when busy state is complete. Auto-clock gating is re-enabled at the end of busy state. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00156389: turn off child clocks before reconfigure perclk_rootTerry Lv2011-09-13-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | In addition to ensuring that PERCLK remains at least 2.5 times slower than the AHB clock, certain steps need to be followed to ensure robust operation of PERCLK when reconfiguring the PERCLK clock source. To properly configure the PERCLK clock source, the following steps are required: 1.In the CCGR registers, gate the clocks to all PERCLK-dependent modules. 2.Select the desired input clock for the PERCLK root clock (to be either source from the peripherals main source clock or the lp_apm clock source). Refer to the CMCBR register, perclk_lp_apm_sel bit. 3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers to the desired setting. Refer to the CBCDR register for details. 4.In the CCGR registers, enable the desired clocks for the PERCLK-dependent module clocks. Certain steps are required to reconfigure perclk_root. If don't follow these steps, GPT timer may stop and the kernel stops at " "Calibrating delay loop". Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00156304 eMMC: Need to update partition config after changing boot partitionAnish Trivedi2011-09-08-32/+33
| | | | | | | | | | | | | | | | After enabling boot partition on an eMMC using "mmc bootpart" command, the partition configuration variable that is supposed to track this value on the eMMC is not updated. This leads to stale and possibly inaccurate boot partition number being printed when "mmcinfo" command is used, thereby confusing the user. The fix is to update the part_config variable of mmc struct with the new value that was just written to the eMMC. Also removed condition that restricted boot_bus_width programming (for fastboot) to eMMC with DDR support only. Now, even non-DDR capable eMMCs can be programmed for fastboot (in SDR mode). Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00156098 mx53_smd/mx53_loco: DA9053 I2C SDA stuck low issue on bootupWayne Zou2011-09-06-2/+204
| | | | | | | | | | | | | | | | For DA9053 I2C SDA stuck low issue: the I2C block in DA9053 may not correctly receive a Power On Reset and device is in unknown state during start-up. The only way to get the chip into known state before any communication with the Chip via I2C is to dummy clock the I2C and bring it in a state where I2C can communicate. Dialog suggested to provide 9 clock on SCL. Dialog don't know the exact reason for the fault and assume it is because some random noise or spurious behaviour. This has to been done in host platform specific I2C driver during start-up when the I2C is being configured at platform level to supply with dummy 9 clock on SCL. Dialog I2C driver has no control to provide dummy 9 clock on SCL. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00156034: Fix mx53 evk build errorTerry Lv2011-09-05-1/+0
| | | | | | Fix mx53 evk build error. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139254: Enable MX6Q Uboot Splash ScreenSandor Yu2011-09-02-63/+441
| | | | | | | | | | | | | | Only support LVDS0 splash screen. Enable splash process: 1.define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h 2.Config U-boot with followed command:() setenv splashimage '0x30000000' #Set splash position as Center setenv splashpos 'm,m' #Set LVDS via LVDS bridge 0 setenv lvds_num 0 Signed-off-by: Sandor Yu <r01008@freescale.com>
* ENGR00155283: Set dpgdck0_2_en to 0 when freq is lower than 300MHzTerry Lv2011-09-01-13/+54
| | | | | | | | 1. Set dpgdck0_2_en to 0 when required freq is lower than 300Mhz. 2. When dpgdck0_2_en is 0, the formula to calculate output freq will be changed to 2 * freq * []. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155279: Change ESDCTL_0x82228080 to ESDCTL_0x82226080 for mx35Terry Lv2011-09-01-3/+4
| | | | | | | | | | In mx35, when testing TVIN, the screen will flick. We find that flickers will get better when using ESDCTL_0x82226080 against ESDCTL_0x82228080 for register SCDCTL0. The origin value ESDCTL_0x82228080 in lowlevel_init.S will be called in external boot which will reduce the bandwidth. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155739: mx53 evk mmu wrong mapped two csd slotsTerry Lv2011-09-01-10/+4
| | | | | | | mx53 evk mmu wrong mapped two csd slots. Actually evk only has one slot. Signed-off-by: Terry Lv <r65388@freescale.com>
generated by cgit v1.1 at 2024-11-21 13:01:32 +0000