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* ENGR00136075 MX53: Add SMD board supportLily Zhang2010-12-30-0/+1530
| | | | | | | | | | | | | | | | | | | | | | | Add MX53 SMD support: - Use DDR3 script for SMD board from Mike Kjar: "Rita_init_LCB_CMOS.inc" - Set the default CPU core frequency as 1GHZ. The following functions are tested on SMD board: - SD/MMC boot, read, write via SDHC1 - eMMC4.4 boot, read, write via SDHC3. - SATA boot, read, write. To support SATA boot via internal clock, please ensure the fuse "SATA_ALT_CLK_REF" was blown. - FEC - UART - clk command - iim command Signed-off-by: Liu Ying <b17645@freescale.com> Signed-off-by: Jason Chen <b02280@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137410 MX53 split board files into different foldersLily Zhang2010-12-29-337/+1444
| | | | | | Split different MX53 board files into different folder. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00136863-2: Fix mx53 CMD12 issue.Terry Lv2010-12-29-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | As in mx53 and lster socs, when using CMD12, cmdtype need to be set to ABORT, otherwise, next read command will hang. This is a software Software Restrictions in spec 29.7.8. For pre-defined multi-block read operation, i.e., The number of blocks to read has been defined by previous CMD23 for MMC, or pre-defined number of blocks in CMD53 for SDIO/SDCombo, or whatever multi-block read without abort command at card side, an abort command, either automatic or manual CMD12/CMD52, is still required by ESDHCV2 after the pre-defined number of blocks are done, to drive the internal state machine to idle mode. In this case, the card may not respond to this extra abort command and ESDHCV2 gets Response Timeout. It is recommended to manually send an abort command with RSPTYP[1:0] both bits cleared. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00136863-1: Change mmc framework architecture.Terry Lv2010-12-29-200/+137
| | | | | | | | | | Change mmc framework architecture. Mainly for code clean and restructure. Mainly merge our code with community code. Based on commit 17b4c8e9eb30e3eb305baef98eb23325e61db592. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137408: Add FAT32 supportTerry Lv2010-12-29-553/+702
| | | | | | | | Add FAT32 support. The code is got from community. Based on hash number 71aab09b2c1edd1b6e00819abd1e31c04db04f36. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137372 MX53: Switch back to use DCD and update DDR scriptsLily Zhang2010-12-28-1022/+259
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. This patch is used to switch back to use DCD for flash header instead of plug-in. This change request is due to the following reasons: 1) U-boot community doesn't accept current plug-in solution when upstreaming. 2) Plug-in isn't supported by MX53 ROM serial download mode. No effective workaround is found now. To use the same code base to support normal U-Boot and MFG tool better, adopt DCD solution firstly. 3) Current MX53 DDR scripts don't exceed the length limitation of DCD. For MX53 TO2.0 EVK/ARM2 board, raise DDR frequency to 400MHZ after VCC and VDDA voltages are raised as 1.3V. Since ARM2 CPU2 board share the same script with EVK, delete ARM2 CPU2 config files. ARM2 CPU2 board can share the same bootloader with EVK. 2. Update MX53 DDR2 scripts for TO1.0/TO2.0 EVK/ARD/ARM2 boards The script "MX53_TO2_DDR2_EVK_ARD.inc" is located under http://compass.freescale.net/livelink/livelink? func=ll&objId=221058910&objAction=browse&viewType=1 This script is published by ATX and FIL team on Dec 16th, 2010 3. Update MX53 ARM2 CPU3 DDR3 script "MX53_TO2_DDR3_CPU3.inc" under the same compass folder Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137390 UBOOT:NAND: BBT not found on MX53 boardJason Liu2010-12-27-0/+7
| | | | | | | | | | BBT table can't be found on MX53 board, which is due to that the BBT table flag has been written to the ECC area which cause the BBT flag lost. This patch also fix the BBT version not correct issue. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00137211 U-Boot MX5x: Incorrect GPL license header on filesXinyu Chen2010-12-22-7/+28
| | | | | | Correct the GPL license Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00137273 uboot: update the android default env for 2.6.35 kernelXinyu Chen2010-12-22-8/+8
| | | | | | | Change the ramdisk load address to loadaddr + 0x400000. Add gpu_memory= kernel parameter. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00137214 MX50: Turn on ZQ calib config by default and fix hang problemRobby Cai2010-12-21-28/+22
| | | | | | | | 1) Turn on ZQ calib config by default in uboot. 2) Remove one problematic statement which can cause hang issue 3) Change comment style from ; to // Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00134068 MX51 BBG:Support CLAA WVGA splashimageLiu Ying2010-12-16-19/+30384
| | | | | | | | | | | 1) IOMUX/backlight support for CLAA WVGA LCD panel. 2) Add video mode for CLAA WVGA LCD panel. 3) Support IPU di1 interface for framebuffer. 4) Enhance IPU driver. 5) Add freescale 600x400 8BPP BMP logo. Signed-off-by: Terry Lv <R65388@freescale.com> Signed-off-by: Liu Ying <b17645@freescale.com>
* ENGR00133727: uart outputs messy code when kernel starts on mx51Terry Lv2010-12-14-3/+72
| | | | | | | uart outputs messy code when kernel starts on mx51. Change uart clock to use pll2 as source clock. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00136038: Remove config CONFIG_EMMC_DDR_MODETerry Lv2010-12-10-27/+26
| | | | | | | | | 1. As we can check DDR dynamically, remove CONFIG_EMMC_DDR_MODE in mmc.c. 2. Add config CONFIG_EMMC_DDR_PORT_DETECT config for some boards that only some board support DDR. Signed-off-by: Terry Lv <r65388@freescale.com>
* MX51: Add video supportStefano Babic2010-12-10-0/+711
| | | | | | | | | | | | | | Add framebuffer driver for the MX51 processor working on the IPUv3 internal graphic processor. The port is based on the driver found in the kernel delivered by Freescale as part of i.MX BSP: [kernel 2.6.31 commit cc4fe714041805997b601fe8e5dd585d8a99297f] [agust@denx.de: some style fixes and dead code removal] Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de> (cherry picked from commit 5dda7945d18077db81eb0cfdc2f9d4525e6b77b1)
* MX51: Add IPU driver for video supportStefano Babic2010-12-10-0/+3237
| | | | | | | | | | | | | The patch is a porting of the IPU Linux driver developed by Freescale to have framebuffer functionalities in u-boot. The port is based on kernel 2.6.31 commit cc4fe714041805997b601fe8e5dd585d8a99297f, as delivered by Freescale [i.MX BSP]. Most features are dropped from the original driver and only LCD support is the goal of this porting. Signed-off-by: Stefano Babic <sbabic@denx.de> (cherry picked from commit 575001e40c9d10e63f2924649098e7c07d3985c7)
* Add linux framebuffer header include/linux/fb.hStefano Babic2010-12-10-0/+616
| | | | | | | [port of linux 2.6.34 commit 6a9ee8af344e3bd7dbd61e67037096cdf7f83289] Signed-off-by: Stefano Babic <sbabic@denx.de> (cherry picked from commit bf90ecd3c366177c55012e68d15b8aeb2c41e907)
* ENGR00136170 MX50 Add ZQ calibration revision for TO1.1Robby Cai2010-12-09-62/+138
| | | | | | | | | | | | | | | | | | | | All type of DDRs will be affected. ddr script is available here: http://compass.freescale.net/livelink/livelink/open/218722501 Two key points: 1. LPDDR2 ZQ calibration is different from mDDR/DDR2, fixed in this version(they're same before). 2. TO1.1 ZQ calibration is _NOT_ compatible with TO1.0. U-Boot default config is for TO1.1. Please switch off CONFIG_ZQ_CALIB option if compile for TO1.0. Other fixes: 1. Change drive strength to 0x00200000 for all ddr types. 2. Add missed config for IOMUXC_SW_PAD_CTL_PAD_DRAM_OPEN and IOMUXC_SW_PAD_CTL_PAD_DRAM_OPENFB. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00136081 DDR script update for MX53 TO2 ARDDinh Nguyen2010-12-08-46/+41
| | | | | | | | | Updated DDR2 script for ARD board from Mike Kjar: "mx53_init_TO2_DDR2_ARD_test.inc". Tested on TO1 and TO2 ARD. Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
* ENGR00136042 Add ZQ calib config and update script for DDR2Robby Cai2010-12-08-2/+9
| | | | | | | | script v2: http://compass.freescale.net/livelink/livelink/219931536/ Codex_DDR2_266MHz.inc.txt?func=doc.Fetch&nodeid=219931536 Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00136031 mfgtool: sync config file for mx50 rdpPeter Chen2010-12-08-0/+1
| | | | | | Some configs for mx50 rdp is missed at mfg-tool firmware config file Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00134220-3 Fix the nand bad command issueJason Liu2010-12-07-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now, uboot cmd_nand of mainline does not support 64-bit address space, which means that currently nand command can't access more than 4GB NAND address even when working on more than 4GB NAND. For example, MX51 U-Boot > nand read ${loadaddr} 100100000 1000 NAND read: device 0 offset 0x100000, size 0x1000 4096 bytes read: OK The reason for not support 64-bit address space of nand cmd is that it use ulong type for addr in file common/cmd_nand.c, but which is 32-bit width on arm gcc tool chain. So, it will stuck in infinite loop when working with 4GB NAND using nand bad command when off overflow. ulong off; //off - 32bit, typeof(nand->size) is ull; for (off = 0; off < nand->size; off += nand->erasesize) { ... } Simply break the for loop when off overflow is temp fix. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00134220-2 Need use CONFIG_SYS_NAND_MAX_CHIPSJason Liu2010-12-07-5/+5
| | | | | | | Need use CONFIG_SYS_NAND_MAX_CHIPS instead of NAND_MAX_CHIPS Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00134220-1 NAND: fix up the chip select handlingJason Liu2010-12-07-12/+26
| | | | | | | | When the NAND has multi-cs, the chip select other than cs0 is not handled correctly which will lead to NAND not function as expected Signed-off-by: Jason Liu <r64343@freescale.com>
* NAND: Update to support 64 bit device sizeSandeep Paulraj2010-12-03-31/+42
| | | | | | | | This patch adds support for NANDs greater than 2 GB. Patch is based on the MTD NAND driver in the kernel. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* ENGR00133744: Merge mx50_arm2 to mx50_rdpTerry Lv2010-12-01-2976/+1368
| | | | | | Merge mx50_arm2 to mx50_rdp. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00025557: MX50 Add ZQ calibration support for TO1.1.1.Terry Lv2010-12-01-79/+494
| | | | | | | MX50 Add ZQ calibration support for TO1.1.1. This need to be enabled by CONFIG_ZQ_CALIB. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR12345678 Change ddr write delay in the PHYRobby Cai2010-12-01-16/+16
| | | | | | | | | | Total 5 registers: 0x1400023c/244/24c/254/25c: from 0x000a1401 to 0x000a0b01 Without this patch, kernel on RDP board with Elpida DDR is not able to boot, or not stable. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00133437 MX50 Uboot support for TO 1.1.1 precodeAnish Trivedi2010-12-01-7/+45
| | | | | | | Precoding: Update DDR configuration plugin to check SI Rev and change ROM addresses as needed. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00133579 Uboot ESDHCv3 Remove workaround for DLLAnish Trivedi2010-12-01-9/+46
| | | | | | | | | | On MX50 TO 1.0, DLL did not work in slave mode, so slave override mode was used instead. Removed this workaround, except for TO 1.0. Starting with TO 1.1, the DLL in slave mode is working as expected. Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00134098-2 MX53: Add fastboot support for android.Sammy He2010-11-26-1/+75
| | | | | | Add fastboot support for mx53 EVK android. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00134098-1 MX51: Update fastboot usb init seqSammy He2010-11-26-52/+23
| | | | | | Update fastboot usb init seq, and use defined macro for coding. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00133124: Add nand support for mx50 rdpTerry Lv2010-11-18-43/+309
| | | | | | Add nand support for mx50 rdp. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00133551-2 Add fastboot driver support for android.Sammy He2010-11-19-70/+852
| | | | | | | | | | | | | | | | | | | Add fastboot driver support for android. In this commit, basic fastboot command is supported. 1) Reboot board >fastboot reboot 2) Get information of board, e.g, product name >fastboot getvar product 3) Download images in PC and flash to SD card >fastboot flash bootloader u-boot-no-padding.bin >fastboot flash kernel uImage >fastboot flash uramdisk uramdisk.img >fastboot flash system system.img >fastboot flash recovery recovery.img Certainly, SD card must have been formatted as Android user guider doc already. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00133551-1 Add freescale usb udc support for i.mx51 platform.Sammy He2010-11-18-1/+1420
| | | | | | | Add imx_udc for usb gadget on i.mx51 platform. Signed-off-by: Hu Hui <b29976@freescale.com> Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00133689 MX51: set MC13892 charge output voltage as 4.2VLily Zhang2010-11-17-3/+20
| | | | | | | | This patch is to set MC13892 charge regulator output voltage as 4.2V. It fixes a typo error for chip check and makes TO3 VCC and VDDA voltages keep sync with the spec. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00133756:UBOOT:NAND:Remove the 2G limitation from NAND driverJason Liu2010-11-16-10/+0
| | | | | | | | | | Remove the 2G limitation from NAND driver since currently kernel can support more than 2GB NAND flash now. This commit will make NAND driver rescan the whole NAND to create one BBT and store to the last 4 blocks of the larger than 2GB NAND flash. This commit will have no effect on the NAND which size is not larger than 2GB. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00133743 Change code style of fastboot code to pass review-commits.Sammy He2010-11-17-261/+237
| | | | | | | cmd_fastboot.c and fastboot.h cannot pass review-commits, this patch only change code style to fix the errors, but not fixed all warnings. Signed-off-by: Sammy He <r62914@freescale.com>
* Get common/cmd_fastboot.c and include/fastboot.h from omap uboot git.Tom Rix2010-11-16-0/+2117
| | | | | | | | | | | The code realized common Android USB fastboot protocol. The snapshot can be found of the link: http://dev.omapzoom.org/?p=bootloader/u-boot.git;a=commit; h=9c7c5d8ea2326bf8d2d0bfbe670455fb497eb053 Signed-off-by: Tom Rix <Tom.Rix@windriver.com> Signed-off-by: Moiz Sonasath <m-sonasath@ti.com>
* ENGR00132909 MX53 Uboot: Support for TO2Anish Trivedi2010-11-15-366/+478
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support new DDR script entitled "Rita_TO2_init_DDR2_CPU2_CMOS_TEST_CAL_v1.inc" for DDR2 boards including MX53 EVK, ARD, and ARM2 CPU2. These new settings did not apply to TO1. Therefore, changed the DCD for these boards to a plugin so that TO1 and TO2 can both be supported using conditional execution of new DDR settings. During bootup on TO2, DDR frequency is required to be below 400 MHz. Therefore, BOOT_CFG2[4] must be set to enable DDR at 333 MHz in ROM on all boards. Uboot determines silicon version and for TO2 boosts the VCC and VDDA voltages to 1.3V, after which the DDR frequency is also increased to 400 MHz. This requirement meant that uboot does not calibrate PLL2 anymore until the voltage is increased. Removed the calibration from lowlevel_init.S and from all mx53 include/configs files. Also required that during config_periph_clk(), only CBCMR register is touched to set source PLL. Other changes to CBCDR were removed. Switching to PLL2 bypass clk during reprogram was also removed. All these changes are required to increase DDR frequency to 400 MHz. DDR2 CPU2 board with TO1 requires the following hw cfgs: JP3 populated, and J8 set to 2-3. For DDR2 CPU2 board with TO2, both these jumpers should be depopulated. ARM2 CPU3 (with DDR3) DDR configurations were not changed. TO1 and TO2 can run well using existing DDR3 script. However, DCD was converted to plugin to align with other boards. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00133530 plug-in support mfgtools and sb_loaderFrank Li2010-11-09-18/+24
| | | | | | | mfgtools and sb_loader can download plug-in and run plug-in to initilize DRAM. Signed-off-by: Frank Li <frank.li@freescale.com>
* ENGR00133049 Support nand flash for MX28Frank Li2010-11-04-27/+242
| | | | | | | Support nand basic read/write in MX28 u-boot. Signed-off-by: Frank Li <frank.li@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00132965 add MT29F16G08ABACA NAND descriptionLily Zhang2010-10-26-0/+5
| | | | | | Add MT29F16G08ABACA NAND description Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132957 mfg-tool: should add stop usb operation for mx50 rdpPeter Chen2010-10-26-0/+7
| | | | | | | It should add stop usb operation for mx50 rdp, otherwise, the usb enumeration at kernel will be very slow Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00132886 mx50-rdp: add mx50 rdp board mfg-tool firmware defconfigPeter Chen2010-10-22-0/+240
| | | | | | Add mx50 rdp board mfg-tool firmware configration Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00132759 MX53: use 32K CLK as GPT sourceLily Zhang2010-10-19-38/+42
| | | | | | | | | | | | | MT29F16G08MAA NAND flash was failed on MX53 ARD/RevB board, but it's fine in RevA board. After check, it's found that udelay is not accurate on MX53 ARD/RevB board because GPT uses IPG peripheral clock and assume it is 50MHZ. However IPG peripheral clock is not 50MHZ in MX53 ARD/RevB board. So it causes udelay is not accurate. This patch changes GPT clk source as 32K to make udelay accurate. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132758 correct NFC_CLK definitionLily Zhang2010-10-19-5/+9
| | | | | | | | This patch is used to fix the issue caused by ENGR00132709. NFC_CLK definition should be used in cmd_clk interface. MXC_NFC_CLK should be used as internal clock name. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132727 NAND: remove REG_NFC_ONE_CYCLE callingLily Zhang2010-10-18-2/+0
| | | | | | | Remove REG_NFC_ONE_CYCLE calling from mxc_nand driver. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132709 MX53: add "clk nfc" command supportLily Zhang2010-10-18-0/+39
| | | | | | | | Add "clk nfc" command support. Limit NFC MAX clock as 34MHZ to be compatible with some old NAND flashes. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132617 MX53: add NAND supportLily Zhang2010-10-17-13/+626
| | | | | | | | | | | | | | | | | | | | | | | | | | Add NAND support for MX53 EVK and ARD. Need to use kobs-ng to flash U-Boot on MX53 TO1. Because MX51 TO1 ROM doesn't support bi swap solution and kernel enable bi swap, Must enable "ignore bad block" option when flashing U-Boot. The step is as following: echo 1 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad kobs-ng init --chip_0_device_path=/dev/mtd2 u-boot.bin echo 0 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad Since default configuration stores environment into SD card and U-Boot uses get_mmc_env_devno (Read SBMR register) to get MMC/SD slot information, you must insert SD card to bottom SD slot to get/store environment if you are using NAND boot on MX53 EVK. You must config boot dip setting well when doing NAND boot. For example, if you are using NAND 29F32G080AA NAND chip on MX53 EVK, you can set boot dips as the following for NAND boot: SW3: dip 7, 8 on; SW2: dip 3,5 on; SW1: dip 4,7,8 on. Other dips are off. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132656 MX53 ARD: Add MFG tool supportLily Zhang2010-10-15-0/+216
| | | | | | | Add default uboot defconfig for MX53 ARD MFG tool Signed-off-by: Lily Zhang <r58066@freescale.com>
generated by cgit v1.1 at 2024-12-18 15:55:08 +0000