| Commit message (Collapse) | Author | Age | Lines |
|
|
|
|
|
| |
Add splash screen code and support for epdc.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
| |
The boot mode offset has been changed in TO1.2.
Signed-off-by: Aisheng.Dong <b29396@freescale.com>
|
|
|
|
|
|
| |
Read mac address from fuse
Signed-off-by: Frank Li <frank.li@freescale.com>
|
|
|
|
|
|
| |
Add mx50 mfg firmware support
Signed-off-by: Peter Chen <peter.chen@freescale.com>
|
|
|
|
|
|
|
| |
This is caused by fec_pwr_en pin is mis-used which lead
to FEC not power on. This commit fix this issue.
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
| |
Enable DDR mode on ESDHC controller and mmc library
Enable 8-bit support in mmc library
Signed-off-by: Anish Trivedi <anish@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Currently we set mx508 memory as 128M which is not
enough for android running.
Based on hardware team's input, mDDR boards support
512MB totally, while we only mount half of them.
LPDDR2 boards support 512MB.
So we will modify mddr configuration as 256M and
LPDDR2 as 512M.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
|
|
|
|
| |
1. Reconstructure fuse. Move fuse files to common directory.
2. Read mac from fuse in fec.
3. Remove scc and srk command from fuse command.
4. Change fuse to iim.
5. Add fuse for mx53.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
|
| |
1. Adjust VDDGP voltage for 800MHZ as 1.05v.
2. Correct VDDA comments
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
|
|
|
|
|
| |
Fix error in a comment for header file
Fix ppp review about error board description
Signed-off-by: Peter Chen <peter.chen@freescale.com>
|
|
|
|
|
|
|
|
| |
Add spi_get_cfg function due to the function has been made
platform specific and moved out of spi driver.
This also fix the build break for mx53 uboot
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
|
| |
MMC init failed when boot with upper SD slot
while succesful with lower slot.
This patch will fix it.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
|
|
| |
Accoring to board identification table, the ADC data
register value range between "0xB9E79F - 0xC00000"
indicates 21.
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
|
|
|
|
|
|
| |
Removed low voltage (1.8V) from supported voltage ranges.
Changed SD2_CMD pad setting to enable SD2 r/w in uboot.
Loaded env from booted device instead of SD1 always.
Signed-off-by: Anish Trivedi <anish@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Use ROM plug-in feature to init DDR and re-config PLL1 to
800Mhz due to ROM set it to 799Mhz. Plug-in has the following benifit
from ROM team comments,
1. DCD size limitation issue, plugin can be the size of OCRAM
free space region which is 72KB.
2. Safe environment to re-configure PLL1 (without impacting SDRAM)
as the plugin runs from OCRAM. This could get around the issue
of some boards running with ARM @ 192MHz due to the incorrect
GPIO configuration for Low Power Boot.
3. Ability to have one bootloader binary for both LPDDR1 & LPDDR2 platforms.
Signed-off-by: Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
| |
Fix the build break for MX51 BBG board
Signed-off-by: Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add initial support for MX50
-Support mddr200Mhz, lpddr2266Mhz ARM2 board,
-Support boot from SD/MMC,
-Support boot from SPI-NOR,
-Support FEC, UART,
-Support SD/MMC/SPI command within UBOOT
Signed-off-by: Anish Trivedi <anish@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
| |
CSPI: make spi_get_cfg platform specific
move the spi_get_cfg out of the cspi/ecspi driver
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
| |
Updated MMC_PARTITION_SWITCH function to not return
failure for partition 0
Signed-off-by: Anish trivedi <anish@freescale.com>
|
|
|
|
|
|
| |
Add MFG tool support for MX53 EVK
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
|
|
|
|
| |
Added dynamic check for which sd slot used for boot
Signed-off-by: Anish Trivedi <anish@freescale.com>
|
|
|
|
|
|
| |
Enable boot partition in BOOT_CONFIG byte of EXT_CSD
Signed-off-by: Anish Trivedi <anish@freescale.com>
|
|
|
|
|
|
| |
Add dwc_ahsata support.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
|
| |
The old config has big env size, and the u-boot.bin will larger than 1MB,
the new one will less than 500KB
Signed-off-by: Peter Chen <b29397@freescale.com>
|
|
|
|
|
|
|
|
|
| |
Original uboot did not support sd1 and can only save environment
into sd0 even actually you're booting from sd1.
This patch adds the capability of saving environment into sd1
when you're booting from sd1.
Signed-off-by: Aisheng.Dong <b29396@freescale.com>
|
|
|
|
|
|
|
|
|
| |
Pass EVK RevB board ID to kernel by system_rev[11:8]
2 -->RevB,
1--->ARM2,
0--->RevA,
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
| |
Add support for saving env data to active mmc device.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
|
|
| |
Add mx25 splash screen support.
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Renato Frias <renato.frias@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
|
|
| |
The clock for axi_b is set to 100Mhz which will cause IPU module has
insufficient clock rate. This patch will increase axi_b clock to 200M
and keep it not change when do clk config in uboot
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
|
| |
Add DDR3 CPU board support, DDR3 clock 400Mhz
Create one config file for it since the DDR3 init
script is much different wtih DDR2.
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
|
|
|
| |
Set DDR clock to 400Mhz on MX53-EVK with DDR2 1GByte RevB
Set DDR clock to 300Mhz on MX53-EVK with DDR2 2GByte RevA1
Remove the clock dump during boot, user can use clk command to
get the clock information. Using help clk to get the command help
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The CPU_ID0 analog voltage level is obtained by reading ADC
channel 12 of the LTC2495 and the CPU_ID1 analog voltage
level is obtained by reading ADC channel 13.
The ADC data register value read from the LTC2495 is a 24 bit value.
For example, an ADC value that reads between 0xB3CF3E and 0xB9E79E
indicates a 130k ohm resistor is populated on the daughtercard,
which corresponds to ID level 20
By using CPU_ID0, CPU_ID1 to identify the board for example:
CPU_ID0 = 21, CPU_ID1 = 15, MX53-EVK with DDR2 1GByte RevB
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
| |
Add peripheral clock setup support.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
| |
Support clock operation functions.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
| |
Preserve NAND bad block indication
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
| |
As customer usually mmc to save env data.
Change default env device to mmc for bbg.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
| |
Integrate linear PMIC.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
| |
Change stmp378x to mx23evk in u-boot.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
| |
fix license declaration issue in fsl_esdhc.h.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
| |
Add mfg firmware support for imx25
Signed-off-by:Yan Wang<r65094@freescale.com>
|
|
|
|
|
|
|
| |
1. Add definition for iomem_valid_addr
2. Add definition for CONFIG_ENV_IS_IN_FLASH
Signed-off-by: Wallace Wang <r59996@freescale.com>
|
|
|
|
|
|
|
|
| |
Both EVK and ARM2 board using the same machine id.
Currently, use system_rev to diff ARM2 board. DDR freq
for ARM2 has been set to 400M, but 300M on EVK.
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
| |
Build Mfg firmware for mx35 3stack
Signed-off-by: Wallace Wang <r59996@freescale.com>
|
|
|
|
|
|
|
| |
System can not find MMC/SD card in SD
slot 1 when booting from Uboot.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
| |
mmc can't read data whose size exceeds 32M.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Update DDR init script according to compass:
http://compass.freescale.net/go/216805297
FCP 7 KB 25-Mar-2010
setmem /32 0x53fa8570 = 0x00180000 ->
setmem /32 0x53fa8570 = 0x00200000
setmem /32 0x53fa8578 = 0x00180000 ->
setmem /32 0x53fa8578 = 0x00200000
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
|
|
| |
-Update eSDHC clock setting,
-Fix the GPT timer setting,
-Fix the boot option pars,
-Remove mdelay() function call to improve the performance
Signed-off-by:Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
|
| |
1. Remove board specific code in mxc_i2c.c.
2. Remove board specific code in mxc_fec.c.
3. Move imx_spi_nor.h to include/asm-arm.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
|
|
|
| |
This change is required by kernel change ENGR00121762
(enables a single kernel image on MX5x parts using run-time phys_offset).
Load address and Entry points are set for MX53 parts(0x7xxxxxxx).
So the bootloader must add the offset 0x20000000 for MX51 parts.
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
|
|
|
|
|
| |
-update DDR script for 300MHZ support, this script got from Yaniv
-increase VDDA to 1.25V
Signed-off-by:Jason Liu <r64343@freescale.com>
|