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* ENGR00144389 mx53 QS Ripley: change VCC from 1.35V to 1.3V QS Ripley boardrel_imx_2.6.35_11.05.01imx_v2009.08_11.05.01Wayne Zou2011-06-01-2/+2
| | | | | | | Change VCC from 1.35V to 1.3V QS Ripley board Signed-off-by: Wayne Zou <b36644@freescale.com> (cherry picked from commit 13d0cc1e7598fe14fa4e6a0b0b5bbdc7aa0b98e2)
* ENGR00143302 Add mc34708 pmic support on loco/Ripley boardZou Weihua -wayne zou2011-06-01-10/+47
| | | | | | | Add mc34708 pmic support on loco/Ripley board Signed-off-by: Zou Weihua -wayne zou <b36644@freescale.com> (cherry picked from commit ecea7efd8a1683f68ad56ac420987a44dbae5c4d)
* ENGR00143570 mx53: change the default environment settingLily Zhang2011-05-20-10/+14
| | | | | | | | Change the default environment setting as sd boot for mx53 loco, mx53 smd and mx53 ard boards. Signed-off-by: Lily Zhang <r58066@freescale.com> (cherry picked from commit 8cb28bb7c7031551672b00d75a272bd31709c9d0)
* ENGR00143613 uboot: update the android ramdisk load addressXinyu Chen2011-05-20-3/+3
| | | | | | | | update the ramdisk load address due to android kernel size enlarge. the ramdisk memory load address is 5MB offset to kernel. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com> (cherry picked from commit 9b65f0a17dd75a75d69b23ad8ab51ea307783791)
* ENGR00143469 mx53 smd: pull down GPIO_9 to reset the boardLily Zhang2011-05-16-0/+15
| | | | | | | | | In mx53 smd, to type "reset" command in u-boot console can not reset the system. It hangs in ROM with unknown reason. This patch adds one workaround to configure GPIO_9 (WDT_OUTPUT_B) as GPIO and pull down it to reset DA9053 PMIC. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00143461 mx51 evk: increase VDDGP as 1.1v for 800MHZLily Zhang2011-05-16-0/+5
| | | | | | | | The default VDDGP output voltage is 1.05V in mx51 evk board According to mx51 datasheet (Rev 0.4), the VDDGP for 800MHZ should be 1.1v for 800MHZ Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00143457: Don't let ROM copy .bss sectionJason Liu2011-05-16-5/+9
| | | | | | | | | | | Don't need let ROM copy the .bss section since it will all be zeroed by u-boot at start up, thus it can speed up the boot up time. Need add CONFIG_FLASH_HEADER_OFFSET to the size since ROM will copy from the beginning of the MMC card. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00143442 uboot: support android spi boot and mfg on mx50 rd3 boardXinyu Chen2011-05-16-4/+443
| | | | | | | | | | | | Add mx50_rd3_android default config file Add basic support for UBI partition mount and UBIFS file read for recovery Add gpmi nand enable in MFG kernel commandline by uboot configure, which enable MFG tool to flash system images on NAND. The total NAND boot and NAND recovery has been disabled. They will be enabled later. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00143428 mx53 ard RevB: use internal clock for sataLily Zhang2011-05-14-0/+19
| | | | | | Switch to use SATA internal clock in mx53 ARD RevB board. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00142995 MX50: Enable uSDHC instead of eSDHC for SDR modeAnish Trivedi2011-05-10-13/+103
| | | | | | | | | | | | | | | | | | On SD3 on MX50, there is an option to choose eSDHC or uSDHC controller. By default eSDHC is selected. However, eSDHC shows some borderline timing in SDR mode at 50 MHz, whereas uSDHC shows borderline timing in DDR mode at 50 MHz. Therefore, add a compile time option to uboot for MX50 to select uSDHC in SDR mode or eSDHC in DDR mode on SD3 port. By default the compile time option, CONFIG_MX50_ENABLE_USDHC_SDR, is commented out in the include/configs/mx50_<board>.h file to select eSDHC with DDR mode enabled. Uncomment the define to select uSDHC with only SDR mode enabled. Also increased max frequency supported by ESDHC to 52 MHz instead of 50 MHz. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00143178 mx53 ARD DDR3 board: add MFG tool supportLily Zhang2011-05-10-0/+231
| | | | | | Add MFG tool support for MX53 ARD DDR3 board. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00142740 mx50 rdp: mfg support GPMI nand by command lineXinyu Chen2011-04-29-2/+2
| | | | | | | | As android make UBIFS as default file system on MX508 RDP, we must enable MFG tool to support UBIFS image update. So enable GPMI nand in default commandline to detect nand devices. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00142497 Android: MX53_SMD: check eMMC and SD recovery file.Zhang Jiejing2011-04-22-38/+42
| | | | | | | | | | Check eMMC and SD cards recovery file, if it exist, enter recovery mode. original code only check SD card, since we already change main storage to eMMC, so we check it both, since most of customer still test it under SD card, check them to avoid support effert. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00142322: mx53-smd: spi nor: can't erase 0x200000 sizeTerry Lv2011-04-20-14/+14
| | | | | | | | | | | | | Spi nor can't erase 0x200000 size. There are two issues in this CR. 1. Spi nor can't erase 0x200000 size. 2. Whole chip erase don't work. The solution will be: 1. Delay more time for WIP check. 2. Use normal erase for whole chip erase. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141885: mx50 and mx53 reboot fail when booting from spi norTerry Lv2011-04-20-2/+15
| | | | | | | mx50 reboot fail when booting from spi nor. Reconfigure eCSPI SS signal as GPIO before reset. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00142259 set UART2_RXD (GP6_11) to highRobby Cai2011-04-18-0/+10
| | | | | | | Isolate EIM signals and boot configuration signals. Without this setting, the chip's temperature will be high. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00142247 MX50: Add PD+3 routine for all DDR typesRobby Cai2011-04-16-18/+34
| | | | | | | | | | | PD+3 routine help test pass for ddr with higher freq. Tested on ARM2 board (mDDR, DDR2) RDP board (LPDDR2 from both vendors) RD3 board (LPDDR2) Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00142246 MX50 Update DDR2 script to use more optimized settingsRobby Cai2011-04-16-123/+64
| | | | | | | | | | | | | | | New DDR2 initialization script from designer includes controller changes as well as very important PHY changes that increase internal sampling window to detect DQS edge. This increase compensates for possible jitter. The script, Codex_DDR2_266MHz.inc v3, is found at http://compass.freescale.net/livelink/ livelink?func=ll&objId=218722501&objAction=browse&viewType=1 Also corrected the DDR clock. (DDR mode changed from Sync to Async) Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00141335-3: Add CONFIG_EMMC_DDR_PORT_DETECT to mx53 and mx50config filesTerry Lv2011-04-11-12/+47
| | | | | | | | | | | | Add CONFIG_EMMC_DDR_PORT_DETECT to mx53 and mx50 config files. For fastboot, please note that the bit width of card should match the dip settings. For example, if mmcinfo shows eMMC 4.4 card is 8Bit DDR, then dip settings should be 8bit DDR. Then fastboot can work. Otherwise, fastboot will fail. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141335-2: get more accurate ipg_per clock frequencyTerry Lv2011-04-11-17/+24
| | | | | | | Add perclk_lp_apm_sel check to function __get_ipg_per_clk. This will get more accute clock frequency. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141335-1: Use bypass way to set ddr dll in mx53Terry Lv2011-04-11-1/+1
| | | | | | | | Usually dll setup for eMMC4.4 DDR is required to polling SLV_LOCK status bit. However the system hangs when polling for SLV_LOCK bit. The temporary workaround is to force slave override mode to bypass it. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141556: Fix copyright issueTerry Lv2011-04-08-78/+44
| | | | | | | | | | | We're following the following rules: 1. FSL copyright should be added for freescale added and modified files. 2. FSL copyright should go after existing copyrights. 3. For Duplicate FSL copyright, Our copyright will go after that also. 4. FSL copyright should not include personal names as part. 5. For only FSL copyright, "All rights reserved" is not mattered. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141410 MX50 RD3: Set GPIO4_16 to Enable DCDC_3V15Robby Cai2011-03-31-2/+12
| | | | | | | | This is needed for FEC to work properly, since FEC3V15 is supplied by DCDC_3V15. In addition, corrected the pin name for FEC_EN. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00141363: change mx53 uart clk parent to pll2Jason Chen2011-03-31-35/+60
| | | | | | | | | | Change all mx53 platform uart clk default parent to pll2. MX53 SMD board need support LVDS and HDMI at the same time, they may use the same clock parent-pll4, so kernel need change ipu di clock parent to pll3, after that, uart clock parent need change to pll2 to avoid console mess. Signed-off-by: Jason Chen <b02280@freescale.com>
* ENGR00141157: Add m25p32 spi nor config to mx53_smd_androidTerry Lv2011-03-25-6/+18
| | | | | | Add m25p32 spi nor config to mx53_smd_android. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141129: Add m25p32 spi_nor support for mx53_smdTerry Lv2011-03-24-12/+125
| | | | | | Add m25p32 spi_nor support for mx53_smd. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141058 MX50_RDP: Android Fix typo in recoevry command linerel_imx_2.6.35_11.03.00Zhang Jiejing2011-03-23-1/+1
| | | | | | | | | A typo is in last commit, will cause android recovery not work. Add a space between two string. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00141000 MX50_RDP: add android recovery support.Zhang Jiejing2011-03-23-1/+129
| | | | | | Add android recovery related config and code. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00140537 mx53: update vddgp according to new data sheetZhou Jingyu2011-03-23-0/+33
| | | | | | mx53: update vddgp according to new data sheet Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
* ENGR00140982 MX53 Increase VDDGP to 1.25V for 1 GHzAnish Trivedi2011-03-22-6/+6
| | | | | | | | MX53 TO 2.0 requires 1.25V for VDDGP instead of 1.2V in order for the core to operate at 1 GHz. Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
* ENGR00140872 Add MX50 RD3 SupportRobby Cai2011-03-22-10/+595
| | | | | | | | Assembled With new PMIC chip - MC34708 (Ripley), and new SPI NOR - M25P32 as well. Add new config file for RD3. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00140873: MMC may wrongly regconize 2GB eMMC as high capacityTerry Lv2011-03-21-2/+4
| | | | | | | | | | | | MMC driver may wrongly regconize some 2GB eMMC as high capacity card. This patch is picked from community. A non-zero value of SEC_COUNT does not indicate that the card is sector addressed. According to the MMC specification, cards with a densitygreater than 2GiB are sector addressed. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00140824 Android: Enable fastboot support for mx50 rdpSammy He2011-03-21-4/+391
| | | | | | Enable fastboot support for mx50 rdp. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00140825: Add mx53 to2.1 chip id recognitionTerry2011-03-20-4/+19
| | | | | | Add mx53 to2.1 chip id recognition. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00140486 Add SPI NOR Flash M25P32 driverRobby Cai2011-03-18-1/+565
| | | | | | | So far, it's supposed to be on MX50 RD3 and MX53 SMD Signed-off-by: Robby Cai <R63905@freescale.com> (cherry picked from commit 0e3d67cd1a2dc30af80e5119b626d997be254991)
* ENGR00140767: Improve mx5x DDR clock functionTerry2011-03-17-47/+41
| | | | | | | | | | | | | | As now mx51 DDR frequency is derived from PLL1. We need to get DDR frequency from PLL1. Mx53 don't use PLL1 for ddr clock source, so just the precision is adjusted. Mx50 don't support clk command yet. DDR config function is modified according to mx50 spec, but not tested yet. Signed-off-by: Terry <r65388@freescale.com>
* ENGR00140750 mx53smd: set the default DDR size to 512MB for android configureXinyu Chen2011-03-17-3/+2
| | | | | | | | Decrease the default DDR size to 512MB in the default android uboot configuration file. This can align with most customers' hardware design, and help us to find more issues before release. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00140692 Update for DDR3-based MX53 SABRE Auto boardsMahesh Mahadevan2011-03-16-4/+413
| | | | | | | Added a new config file, the DDR setup is similar to the MX53 Quick Start & MX53 SABRE-Tablet ref design boards. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00140089 MX53_SMD: update command line.Zhang Jiejing2011-03-14-3/+3
| | | | | | | 1. update new style ldb per kernel update. 2. update the default boot command is from eMMC Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00138533: Fix sata write operation random failure issueTerry Lv2011-03-02-1/+3
| | | | | | | Parameter of calling to memalign is wrong. Thus need to modify it. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139747: Read fuse to distinguish between mx53 revA and revBTerry Lv2011-03-02-7/+43
| | | | | | | | | Read fuse to distinguish between mx53 revA and revB. Now SoC efuse is used for board id. Thus we now check fuse value for board rev and id. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139924 mx53 smd &loco: set bootup vdd GP to 1.2vZhou Jingyu2011-03-01-0/+6
| | | | | | set bootup vdd GP to 1.2v for mx53 smd &loco Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
* ENGR00139120: Correct CONFIG_CMD_MMC to CONFIG_CMD_IIM for iimTerry Lv2011-02-14-8/+8
| | | | | | Correct CONFIG_CMD_MMC to CONFIG_CMD_IIM for iim. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00138689 MX50 Update LPDDR2 script to use more optimized settingsAnish Trivedi2011-01-31-315/+42
| | | | | | | | | | | | | | | | New LPDDR2 initialization script from designer includes controller changes as well as very important PHY changes that increase internal sampling window to detect DQS edge. This increase compensates for possible jitter. The script, Codex_LPDDR2_266MHz.inc v7, is found at http://compass.freescale.net/livelink/ livelink?func=ll&objId=218722501&objAction=browse&viewType=1 Also removed ARM2 LPDDR2 init section since the settings for that board are the same as the RDP (EVK). Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00138635 MX50 Update mDDR script to use more optimized settingsAnish Trivedi2011-01-28-55/+55
| | | | | | | | | | | | | New mDDR (LPDDR1) initialization script from designer includes controller changes as well as very important PHY changes that increase internal sampling window to detect DQS edge. This increase compensates for possible jitter. The script, Codex_LPDDR1_200MHz.inc v4, is found at http://compass.freescale.net/livelink/ livelink?func=ll&objId=218722501&objAction=browse&viewType=1 Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00138549 Android fastboot: Support eMMC4.4 on imx53_smdrel_imx_2.6.35_11.01.00Sammy He2011-01-28-28/+64
| | | | | | | | Support eMMC4.4 storage on imx53_smd android fastboot, using environment to control it, the command is: > setenv fastboot_dev mmc1 Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00118558 MX51/MX53: change the boot command of android boards.Zhang Jiejing2011-01-27-10/+14
| | | | | | | The android uImage is greater than 3M, so we need to change the boot command. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00138534 Disable splashimage support defaultly for PDKLiu Ying2011-01-26-3/+0
| | | | | | | Disable splashimage support defaultly for MX51 BBG/MX53 SMD/ MX53 ARD platforms. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00138422-3 Android fastboot: Pass block offset to cmd_fastbootSammy He2011-01-27-28/+28
| | | | | | Pass mmc/sata block offset from fastboot driver to cmd_fastboot, not byte. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00138422-2 Add SATA storage support for android fastbootSammy He2011-01-26-106/+138
| | | | | | Add SATA storage support for android fastboot. Signed-off-by: Sammy He <r62914@freescale.com>
generated by cgit v1.1 at 2024-11-21 12:27:36 +0000