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* ENGR00138422-1 Fix usb connection failure if do sata initSammy He2011-01-26-8/+19
| | | | | | | Increase memory alignment to fix usb connection failure issue if do sata init, and support MMU disable case in imx_udc driver. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00138468-2 Enable splashimage support for several platformsLiu Ying2011-01-25-0/+3
| | | | | | | This patch enables splashimage support for MX53 SMD/ARD and MX51 BBG pdk platforms. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00138468-1 MX5 video:Disable DP/DC/DI/IDMAC before go to kernelLiu Ying2011-01-25-0/+8
| | | | | | | This patch fixes the kernel bootup random hang issue by disabling DP/DC/DI/IDMAC before we go to kernel. This is a workaround. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00138390 android recovery, enlarge uImage sizeZhang Jiejing2011-01-24-2/+2
| | | | | | Kernel image is bigger than 3M, the 0x1800 will not enough. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00138359 Change uramdisk from 6M byte offset of android fastbootSammy He2011-01-22-5/+5
| | | | | | | Change uramdisk from 6M byte offset of android fastboot due to kernel image size more than 3M now. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00138240 Disable splashimage support for PDKLiu Ying2011-01-20-3/+0
| | | | | | | Disable splashimage support for mx53 smd, mx53 ard and mx51 bbg. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00138191 disable the SPLASH SCREEN for androidXinyu Chen2011-01-19-2/+0
| | | | | | Disable for BBG and SMD Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00138148 MX53 TO2.0 EVK: change the default core as 1GHZLily Zhang2011-01-18-9/+18
| | | | | | | Change the default core frequency as 1GHZ for MX53 TO2.0 EVK board Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00138040-3 Protect splashimage related stuffs by configLiu Ying2011-01-17-3/+5
| | | | | | | This patch protects splashimge related stuffs by config option for mx51 bbg, mx53 ard and mx53 smd. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00138040-2 MX51 BBG Android:Support splashimageLiu Ying2011-01-17-0/+19
| | | | | | This patch supports splashimage for MX51 BBG Android. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00138040-1 MX53 SMD Android:Support splashimageLiu Ying2011-01-17-0/+23
| | | | | | This patch supports splashimage for MX53 SMD Android. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137552 MX53: increase VDDGP as 1.2V for 1GHZLily Zhang2011-01-15-3/+30
| | | | | | | | | The norminal voltage of VDDGP for 1GHZ is 1.2V in MX53 TO2.0 datasheet (RevD). So set the CPU frequency as 800MHZ firstly since VDDGP is 1.1V after power on. After increasing VDDGP as 1.2V, increase CPU as 1GHZ. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137894-6 MX53 SMD:Support splashimageLiu Ying2011-01-14-1/+150
| | | | | | | | | | | | | | This patch supports to use pwm wave to control backlight. The pwm rate is 20KHz and the pwm duty is 50%. Only lvds panel is supported. Use 'lvds_num' env variable to choose to use lvds0 or lvds1. However, only lvds1 is tested as the lvds cable cannot be plugged into lvds0 connector. Note that you need to add 'splashimage' env variable to set the memory address of the bmp image. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137894-5 MX53 ARD:Support splashimageLiu Ying2011-01-14-0/+230
| | | | | | | | | | | This patch supports to use pwm wave to control backlight. The pwm rate is 200Hz and the pwm duty is 50%. Use 'lvds_num' env variable to choose to use lvds0 or lvds1. Note that you need to add 'splashimage' env variable to set the memory address of the bmp image. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137894-4 IPUv3 FB: IPUv3 FB driver enhancementLiu Ying2011-01-14-7/+10
| | | | | | | | 1) Change MX51 related function names to IPUv3 related names. 2) Change MX51 related comments to IPUv3 related comments. 3) Do not set panel_info.cmap to be NULL pointer. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137894-3 IPU driver enhancementLiu Ying2011-01-14-31/+61
| | | | | | | | 1) Remove MX51 related comments in ipu drivers. 2) Add di clocks. 3) Support pixel clock being deprived from external clock. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137894-2 MX53: Add ipu base addr and ipu clockLiu Ying2011-01-13-0/+48
| | | | | | This patch adds ipu base address and ipu clock. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137894-1 Add imx pwm driver supportLiu Ying2011-01-13-0/+158
| | | | | | | This patch adds imx pwm driver support as a misc device. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137791 MX53: Update for MFG toolLily Zhang2011-01-11-9/+504
| | | | | | | | - Add MFG tool support for MX53 SMD and MX53 LOCO boards - Update mx53 ARD MFG defconfig to pass compile Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137358: Add saving environment to sata device supportTerry Lv2011-01-11-5/+190
| | | | | | Add saving environment to sata device support. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00136869: SATA device can't init and a typo in sata helpTerry2011-01-11-2/+2
| | | | | | | | | | | | | | | | | | SATA device can't init and a typo in sata help. Add delay in sata detect proceduce. Currently, I have met 3 problems for this issue. 1. Seagate HD. It needs 1000 for timeout. 2. Hitachi HD. It needs 10000 for timeout. 3. In sata env case, it needs 100000 for timeout. 10000000 for timeout is just to avoid a dead loop, And suppose this timeout should be enough for all normal case. It doesn't mean all HD need to wait this long time, If tfd is ok, the loop will be breaked immediately. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137841 splashimage:Correct horizontal display positionLiu Ying2011-01-11-1/+2
| | | | | | | | | When we use splashpos command to set the display position of a bmp image, the x value means the number of pixels from the left boundary of the screen, so we should consider the bits of every pixel when we calculate fb address offset. Signed-off-by: Liu Ying <b17645@freescale.com>
* ENGR00137767 IPUv3 video:Support splashimage with MMU disabledLiu Ying2011-01-10-2/+6
| | | | | | | | This patch corrects the fbi->screen_base value and fbi->fix.smem_start value when MMU is disabled. Reported-by: Terry Lv <r65388@freescale.com> Signed-off-by: Liu Ying <b17645@freescale.com>
* ENGR00137766 BBG splashimage:Allocate cmap for panel_infoLiu Ying2011-01-10-1/+10
| | | | | | | This patch allocates cmap for panel_info, otherwise, cmap_base in common/lcd.c will be NULL pointer. Signed-off-by: Liu Ying <b17645@freescale.com>
* ENGR00137713 MX53 Uboot SMSC Fix order in which mac addr bytes are read from IIMAnish Trivedi2011-01-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Given that an example mac addr is 00-11-22-33-44-55, it should be fused into the IIM at the following locations: 0xC24 - 00 0xC28 - 11 0xC2C - 22 0xC30 - 33 0xC34 - 44 0xC38 - 55 Then, when reading the bytes into a mac array, it should be read as follows: mac[0] - 00 mac[1] - 11 mac[2] - 22 mac[3] - 33 mac[4] - 44 mac[5] - 55 Previously, it was read into the array in reverse order. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00137603 Add mx53_smd_android config for androidSammy He2011-01-08-4/+330
| | | | | | Add mx53_smd_android config for android build. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00137604: Change PLL4 to 455MHz for mx53Terry Lv2011-01-07-6/+33
| | | | | | | Required by display to set ldb. We need to set PLL4 to 455MHz. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137642 MX53 Uboot Align DDR3 script for Loco and SMD boardsAnish Trivedi2011-01-05-4/+4
| | | | | | | | | | | | | Changed the value of one register, offset 0x88, of the ESDCTL controller to match the official script for the boards, entitled "MX53_TO2_DDR3_LCB.inc", found at http://compass.freescale.net/livelink/livelink/221435668/ MX53_TO2_DDR3_LCB.inc.txt?func=doc.Fetch&nodeid=221435668 The register value sets read delay lines. The change is minor. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00137596 MX53 Uboot SMC911X driver needs to get mac addr from IIMAnish Trivedi2011-01-05-0/+25
| | | | | | | If the MAC addr read from the controller's ADDRH and ADDRL registers is invalid, then try to read MAC address programmed in MX53's IIM. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00137497-2 MX53: Add LOCO board supportLily Zhang2010-12-30-2/+1477
| | | | | | | | | | | Add MX53 LOCO board support The following functions are tested in the board: - Micro SD boot - MMC/SD read/write. - clk command - fuse command Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137497-1 Import new mach-type header fileLily Zhang2010-12-30-33/+2387
| | | | | | | | Import new mach-type header file for MX53 LOCO board Signed-off-by: Lily Zhang <r58066@freescale.com> Acked-by: Lily Zhang <r58066@freescale.com>
* ENGR00136075 MX53: Add SMD board supportLily Zhang2010-12-30-0/+1530
| | | | | | | | | | | | | | | | | | | | | | | Add MX53 SMD support: - Use DDR3 script for SMD board from Mike Kjar: "Rita_init_LCB_CMOS.inc" - Set the default CPU core frequency as 1GHZ. The following functions are tested on SMD board: - SD/MMC boot, read, write via SDHC1 - eMMC4.4 boot, read, write via SDHC3. - SATA boot, read, write. To support SATA boot via internal clock, please ensure the fuse "SATA_ALT_CLK_REF" was blown. - FEC - UART - clk command - iim command Signed-off-by: Liu Ying <b17645@freescale.com> Signed-off-by: Jason Chen <b02280@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137410 MX53 split board files into different foldersLily Zhang2010-12-29-337/+1444
| | | | | | Split different MX53 board files into different folder. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00136863-2: Fix mx53 CMD12 issue.Terry Lv2010-12-29-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | As in mx53 and lster socs, when using CMD12, cmdtype need to be set to ABORT, otherwise, next read command will hang. This is a software Software Restrictions in spec 29.7.8. For pre-defined multi-block read operation, i.e., The number of blocks to read has been defined by previous CMD23 for MMC, or pre-defined number of blocks in CMD53 for SDIO/SDCombo, or whatever multi-block read without abort command at card side, an abort command, either automatic or manual CMD12/CMD52, is still required by ESDHCV2 after the pre-defined number of blocks are done, to drive the internal state machine to idle mode. In this case, the card may not respond to this extra abort command and ESDHCV2 gets Response Timeout. It is recommended to manually send an abort command with RSPTYP[1:0] both bits cleared. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00136863-1: Change mmc framework architecture.Terry Lv2010-12-29-200/+137
| | | | | | | | | | Change mmc framework architecture. Mainly for code clean and restructure. Mainly merge our code with community code. Based on commit 17b4c8e9eb30e3eb305baef98eb23325e61db592. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137408: Add FAT32 supportTerry Lv2010-12-29-553/+702
| | | | | | | | Add FAT32 support. The code is got from community. Based on hash number 71aab09b2c1edd1b6e00819abd1e31c04db04f36. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137372 MX53: Switch back to use DCD and update DDR scriptsLily Zhang2010-12-28-1022/+259
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. This patch is used to switch back to use DCD for flash header instead of plug-in. This change request is due to the following reasons: 1) U-boot community doesn't accept current plug-in solution when upstreaming. 2) Plug-in isn't supported by MX53 ROM serial download mode. No effective workaround is found now. To use the same code base to support normal U-Boot and MFG tool better, adopt DCD solution firstly. 3) Current MX53 DDR scripts don't exceed the length limitation of DCD. For MX53 TO2.0 EVK/ARM2 board, raise DDR frequency to 400MHZ after VCC and VDDA voltages are raised as 1.3V. Since ARM2 CPU2 board share the same script with EVK, delete ARM2 CPU2 config files. ARM2 CPU2 board can share the same bootloader with EVK. 2. Update MX53 DDR2 scripts for TO1.0/TO2.0 EVK/ARD/ARM2 boards The script "MX53_TO2_DDR2_EVK_ARD.inc" is located under http://compass.freescale.net/livelink/livelink? func=ll&objId=221058910&objAction=browse&viewType=1 This script is published by ATX and FIL team on Dec 16th, 2010 3. Update MX53 ARM2 CPU3 DDR3 script "MX53_TO2_DDR3_CPU3.inc" under the same compass folder Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137390 UBOOT:NAND: BBT not found on MX53 boardJason Liu2010-12-27-0/+7
| | | | | | | | | | BBT table can't be found on MX53 board, which is due to that the BBT table flag has been written to the ECC area which cause the BBT flag lost. This patch also fix the BBT version not correct issue. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00137211 U-Boot MX5x: Incorrect GPL license header on filesXinyu Chen2010-12-22-7/+28
| | | | | | Correct the GPL license Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00137273 uboot: update the android default env for 2.6.35 kernelXinyu Chen2010-12-22-8/+8
| | | | | | | Change the ramdisk load address to loadaddr + 0x400000. Add gpu_memory= kernel parameter. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00137214 MX50: Turn on ZQ calib config by default and fix hang problemRobby Cai2010-12-21-28/+22
| | | | | | | | 1) Turn on ZQ calib config by default in uboot. 2) Remove one problematic statement which can cause hang issue 3) Change comment style from ; to // Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00134068 MX51 BBG:Support CLAA WVGA splashimageLiu Ying2010-12-16-19/+30384
| | | | | | | | | | | 1) IOMUX/backlight support for CLAA WVGA LCD panel. 2) Add video mode for CLAA WVGA LCD panel. 3) Support IPU di1 interface for framebuffer. 4) Enhance IPU driver. 5) Add freescale 600x400 8BPP BMP logo. Signed-off-by: Terry Lv <R65388@freescale.com> Signed-off-by: Liu Ying <b17645@freescale.com>
* ENGR00133727: uart outputs messy code when kernel starts on mx51Terry Lv2010-12-14-3/+72
| | | | | | | uart outputs messy code when kernel starts on mx51. Change uart clock to use pll2 as source clock. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00136038: Remove config CONFIG_EMMC_DDR_MODETerry Lv2010-12-10-27/+26
| | | | | | | | | 1. As we can check DDR dynamically, remove CONFIG_EMMC_DDR_MODE in mmc.c. 2. Add config CONFIG_EMMC_DDR_PORT_DETECT config for some boards that only some board support DDR. Signed-off-by: Terry Lv <r65388@freescale.com>
* MX51: Add video supportStefano Babic2010-12-10-0/+711
| | | | | | | | | | | | | | Add framebuffer driver for the MX51 processor working on the IPUv3 internal graphic processor. The port is based on the driver found in the kernel delivered by Freescale as part of i.MX BSP: [kernel 2.6.31 commit cc4fe714041805997b601fe8e5dd585d8a99297f] [agust@denx.de: some style fixes and dead code removal] Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de> (cherry picked from commit 5dda7945d18077db81eb0cfdc2f9d4525e6b77b1)
* MX51: Add IPU driver for video supportStefano Babic2010-12-10-0/+3237
| | | | | | | | | | | | | The patch is a porting of the IPU Linux driver developed by Freescale to have framebuffer functionalities in u-boot. The port is based on kernel 2.6.31 commit cc4fe714041805997b601fe8e5dd585d8a99297f, as delivered by Freescale [i.MX BSP]. Most features are dropped from the original driver and only LCD support is the goal of this porting. Signed-off-by: Stefano Babic <sbabic@denx.de> (cherry picked from commit 575001e40c9d10e63f2924649098e7c07d3985c7)
* Add linux framebuffer header include/linux/fb.hStefano Babic2010-12-10-0/+616
| | | | | | | [port of linux 2.6.34 commit 6a9ee8af344e3bd7dbd61e67037096cdf7f83289] Signed-off-by: Stefano Babic <sbabic@denx.de> (cherry picked from commit bf90ecd3c366177c55012e68d15b8aeb2c41e907)
* ENGR00136170 MX50 Add ZQ calibration revision for TO1.1Robby Cai2010-12-09-62/+138
| | | | | | | | | | | | | | | | | | | | All type of DDRs will be affected. ddr script is available here: http://compass.freescale.net/livelink/livelink/open/218722501 Two key points: 1. LPDDR2 ZQ calibration is different from mDDR/DDR2, fixed in this version(they're same before). 2. TO1.1 ZQ calibration is _NOT_ compatible with TO1.0. U-Boot default config is for TO1.1. Please switch off CONFIG_ZQ_CALIB option if compile for TO1.0. Other fixes: 1. Change drive strength to 0x00200000 for all ddr types. 2. Add missed config for IOMUXC_SW_PAD_CTL_PAD_DRAM_OPEN and IOMUXC_SW_PAD_CTL_PAD_DRAM_OPENFB. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00136081 DDR script update for MX53 TO2 ARDDinh Nguyen2010-12-08-46/+41
| | | | | | | | | Updated DDR2 script for ARD board from Mike Kjar: "mx53_init_TO2_DDR2_ARD_test.inc". Tested on TO1 and TO2 ARD. Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
* ENGR00136042 Add ZQ calib config and update script for DDR2Robby Cai2010-12-08-2/+9
| | | | | | | | script v2: http://compass.freescale.net/livelink/livelink/219931536/ Codex_DDR2_266MHz.inc.txt?func=doc.Fetch&nodeid=219931536 Signed-off-by: Robby Cai <R63905@freescale.com>
generated by cgit v1.1 at 2024-11-21 16:55:07 +0000