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* 85xx: enable the auto self refresh for wake up ARPDave Liu2009-01-23-0/+6
| | | | | | | | The wake up ARP feature need use the memory to process wake up packet, we enable auto self refresh to support it. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* fsl-ddr: use the 1T timing as default configurationDave Liu2009-01-23-1/+21
| | | | | | | | | For light loaded system, we use the 1T timing to gain better memory performance, but for some heavily loaded system, you have to add the 2T timing options to board files. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* fsl-ddr: make the self refresh idle threshold configurableDave Liu2009-01-23-4/+12
| | | | | | | | | | | | | Some 85xx processors have the advanced power management feature, such as wake up ARP, that needs enable the automatic self refresh. If the DDR controller pass the SR_IT (self refresh idle threshold) idle cycles, it will automatically enter self refresh. However, anytime one transaction is issued to the DDR controller, it will reset the counter and exit self refresh state. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* fsl-ddr: clean up the ddr code for DDR3 controllerDave Liu2009-01-23-11/+16
| | | | | | | | - The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* fsl-ddr: update the bit mask for DDR3 controllerDave Liu2009-01-23-4/+8
| | | | | | | | According to the latest 8572 UM, the DDR3 controller is expanding the bit mask, and we use the extend ACTTOPRE mode when tRAS more than 19 MCLK. Signed-off-by: Dave Liu <daveliu@freescale.com>
* 85xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boardsKumar Gala2009-01-23-8/+30
| | | | | | | | | Introduce a new define to seperate out the virtual address that PCI IO space is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boardsKumar Gala2009-01-23-54/+84
| | | | | | | | | Introduce a new define to seperate out the virtual address that PCI memory is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Use CONFIG_SYS_{PCI*,RIO*}_MEM_PHYS for physical address on FSL boardsKumar Gala2009-01-23-9/+10
| | | | | | | | Use the _MEM_PHYS defines instead of _MEM_BUS for LAW and real address fields of TLBs. This is what we should have always been using from the start. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala2009-01-23-47/+55
| | | | | | | Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala2009-01-23-95/+103
| | | | | | | | Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: separate FLASH BASE virtual from physical addressKumar Gala2009-01-23-14/+16
| | | | | | | | | | Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: separate PIXIS virtual from physical addressKumar Gala2009-01-23-6/+8
| | | | | | | | | | Added a PIXIS_BASE_PHYS for use as the physical address and maintain PIXIS_BASE as the virtual address of the PIXIS fpga registers. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* Add README file for MPC8572DS boardHaiying Wang2009-01-23-0/+167
| | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* Blackfin: use common strmhz() in system outputMike Frysinger2009-01-23-6/+10
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-nand-flashWolfgang Denk2009-01-23-469/+1091
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| * nand: fixup printf modifiers to match types usedMike Frysinger2009-01-23-8/+8
| | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * nand read.jffs2 (nand_legacy) in common/cmd_nand.cSchlaegl Manfred jun2009-01-23-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | Error with CONFIG_NAND_LEGACY in common/cmd_nand.c: With current code "nand read.jffs2s" (read and skip bad blocks) is always interpreted as "nand read.jffs2" (read and fill bad blocks with 0xff). This is because ".jffs2" is tested before ".jffs2s" and only the first two characters are compared. Correction: Test for ".jffs2s" first and compare the first 7 characters. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPSWolfgang Grandegger2009-01-23-77/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and changes the default from 8 to 1 for the legacy and the new MTD NAND layer. This allows to remove all NAND_MAX_CHIPS definitions in the board config files because none of the boards use multi chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 define #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE but that's bogus and did not work anyhow. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * NAND: Fix cache and memory inconsistency issueDave Liu2009-01-23-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We load the secondary stage u-boot image from NAND to system memory by nand_load, but we did not flush d-cache to memory, nor invalidate i-cache before we jump to RAM. When the system has cache enabled and the TLB/page attribute of system memory is cacheable, it will cause issues. - 83xx family is using the d-cache lock, so all of d-cache access is cache-inhibited. so you can't see the issue. - 85xx family is using d-cache, i-cache enable, partial cache lock. you will see the issue. This patch fixes the cache issue. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * NAND: Enable nand lock, unlock featureNishanth Menon2009-01-23-83/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable nand lock, unlock and status of lock feature. Not every device and platform requires this, hence, it is under define for CONFIG_CMD_NAND_LOCK_UNLOCK Nand unlock and status operate on block boundary instead of page boundary. Details in: http://www.micron.com/products/partdetail?part=MT29C2G24MAKLAJG-6%20IT Intial solution provided by Vikram Pandita <vikram.pandita@ti.com> Includes preliminary suggestions from Scott Wood Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * NAND: move board_nand_init to nand.hMike Frysinger2009-01-23-2/+2
| | | | | | | | | | | | | | | | | | | | | | Rather than putting the function prototype for board_nand_init() in the one place where it gets called, put it into nand.h so that every place that also defines it gets the prototype. Otherwise, errors can go silently unnoticed such as using the wrong return value (void rather than int) when defining the function. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * OneNAND: Additional sync with 2.6.27Stefan Roese2009-01-23-1/+72
| | | | | | | | | | | | | | | | | | | | | | | | - Add subpage write support - Add onenand_oob_64/32 ecclayout This has been missing and without it UBI has some incompatibilies issues with the current (>= 2.6.27) Linux kernel version. vid_hdr_offset is placed differently (2048 instead of 512) without this fix. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * Add markbad functionKyungmin Park2009-01-23-0/+33
| | | | | | | | | | | | | | Add missing markbad function If not, it's hang when it entered the mtd->mark_bad(). Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
| * OneNAND: Bad block aware read/write command supportStefan Roese2009-01-23-110/+420
| | | | | | | | | | | | | | | | | | Update OneNAND command to support bad block awareness. Also change the OneNAND command style to better match the NAND version. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
| * OneNAND: Save version_id in onenand_chip structStefan Roese2009-01-23-0/+1
| | | | | | | | | | | | | | | | The version (ver_id) was not stored in the onenand_chip structure and because of this the continuous locking scheme could be enabled on some chips. Signed-off-by: Stefan Roese <sr@denx.de>
| * OneNAND: Fix compiler warningsStefan Roese2009-01-23-0/+26
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * mpc83xx: enable eLBC NAND support for MPC8315ERDB boardDave Liu2009-01-23-5/+7
| | | | | | | | Signed-off-by: Dave Liu <daveliu@freescale.com>
| * Sync with 2.6.27Kyungmin Park2009-01-23-179/+406
| | | | | | | | | | | | Sync with OneNAND kernel codes Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk2009-01-23-64/+121
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| * microblaze: Use cache functions (especially cache status)Michal Simek2009-01-23-6/+0
| | | | | | | | in systems which are configured without flash
| * microblaze: Add cache flushMichal Simek2009-01-23-3/+32
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| * microblaze: Add bootup messages to board.cMichal Simek2009-01-23-2/+31
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| * microblaze: Change microblaze-generic config fileMichal Simek2009-01-23-47/+54
| | | | | | | | Signed-off-by: Michal Simek <monstr@monstr.eu>
| * microblaze: Rename ml401 to microblaze-genericMichal Simek2009-01-23-9/+7
| | | | | | | | Signed-off-by: Michal Simek <monstr@monstr.eu>
* | Merge branch 'fixes'Haavard Skinnemoen2009-01-22-7/+2
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| * avr32: Remove second definition of virt_to_phys()Haavard Skinnemoen2008-12-17-7/+2
| | | | | | | | | | | | | | | | | | | | The second definition introduced by 65e43a1063 conflicts with the existing one. Also, convert the existing definition to use phys_addr_t. The volatile qualifier is still needed due to brain damage elsewhere. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* | Prepare v2009.01v2009.01Wolfgang Denk2009-01-21-1/+11
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Prepare 2009.01-rc3v2009.01-rc3Wolfgang Denk2009-01-18-1/+177
| | | | | | | | | | | | Update CHANGELOG Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-01-18-1/+1
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| * | fdt_resize(): fix actualsize calculations with unaligned blobsPeter Korsgaard2009-01-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code in fdt_resize() to extend the fdt size to end on a page boundary is wrong for fdt's not located at an address aligned on a page boundary. What's even worse, the code would make actualsize shrink rather than grow if (blob & 0xfff) was bigger than the amount of padding added by ALIGN(), causing fdt_add_mem_rsv to fail. Fix it by aligning end address (blob + size) to a page boundary instead. For aligned fdt's this is equivalent to what we had before. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
* | | build system: treat all Darwin's alikeMike Frysinger2009-01-18-2/+2
|/ / | | | | | | | | | | | | The x86 based version of Darwin behaves the same quirky way as the powerpc Darwin, so only check HOSTOS when setting up Darwin workarounds. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | ncb: use socklen_tMike Frysinger2009-01-16-1/+1
| | | | | | | | | | | | The recvfrom() function takes a socklen_t, not an int. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2009-01-16-1083/+657
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| * | sh: serial: use readx/writex accessorsJean-Christophe PLAGNIOL-VILLARD2009-01-16-23/+23
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: serial: coding style cleanupJean-Christophe PLAGNIOL-VILLARD2009-01-16-17/+18
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: Fix compile error on lowlevel_init fileNobuhiro Iwamatsu2009-01-16-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | lowlevel_init of SH was corrected to use the write/readXX macro. However, there was a problem that was not able to be compiled partially. This patch corrected this. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: Fix up rsk7203 target for out of tree buildKieran Bingham2009-01-16-10/+19
| | | | | | | | | | | | | | | | | | | | | Fix up rsk7203 target to build successfully using out-of-tree build. Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: use write{8,16,32} in all lowlevel_initJean-Christophe PLAGNIOL-VILLARD2009-01-16-785/+338
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: lowlevel_init coding style cleanupJean-Christophe PLAGNIOL-VILLARD2009-01-16-634/+640
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: update sh2/sh2a timer coding styleJean-Christophe PLAGNIOL-VILLARD2009-01-16-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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