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* am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and supportTom Rini2012-09-01-0/+60
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework config_ddr to make DDR3 support easier.Tom Rini2012-09-01-14/+23
| | | | | | | | In order to support DDR3 as well as DDR2, we need to perform the same init sequence, but with different values. So change config_ddr() to toggle setting pointers/etc for what DDR2 wants, and then calling. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Move some variables in emif4.c, mark them static.Tom Rini2012-09-01-4/+3
| | | | | | We need vtpreg and ddrctrl but no longer need a second ddrregs. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Correct and clean up ddr_regs structTom Rini2012-09-01-34/+20
| | | | | | | | | | | | | | The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry. Correct this by documenting a missing register that will be used at some point in the future (when write leveling is supported). Further, the cmdNcs{force,delay} fields are undocumented and we have been setting them to zero, remove. Next, setting of the 'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the ddr_data entries, so program it there. Finally, comment on how we are configuring the DATA1 registers that correspond to the DATA0 (dt0) registers defined in the struct. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Do not touch 'ratio1' fieldsTom Rini2012-09-01-35/+7
| | | | | | | | | The various ratio1 fields are not documented in any of the documentation I can find. Removing these and testing has yielded success, so remove the code that sets them and move their locations into the reserved fields. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework config_io_ctrl slightlyTom Rini2012-09-01-27/+8
| | | | | | | | | This function sets a number of related registers to the same value (the registers in question all have the same field descriptions and are related in operation). Rather than defining a struct and setting the value repeatedly, just pass in the value. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Use emif_regs struct for storing initialization valuesTom Rini2012-09-01-78/+31
| | | | | | | Rather than defining our own structs to note what to use when programming the EMIF and related re-use the emif_regs struct. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Turn a number of 'int' functions to 'void'Tom Rini2012-09-01-42/+15
| | | | | | | | A number of memory initalization functions were int and always returned 0. Further it's not feasible to be doing error checking here, so simply turn them into void functions. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Document what we're doing with ddrctrl->ddrckectrlTom Rini2012-09-01-4/+3
| | | | | | | | | - Remove the call to set ddrctrl->ddrioctrl as it's all zeros. - Comment what we're really setting in ddrctrl->ddrckectrl which is that we're operating in the normal mode where EMIF/PHY clock is controlled by the PHY. Signed-off-by: Tom Rini <trini@ti.com>
* am335x: ddr_defs: Update EMIF parametersVaibhav Bedia2012-09-01-5/+5
| | | | | | | | | | | | | | | | | EMIF parameters are calculated based on the AC timing parameters from the SDRAM datasheet and the DDR frequency. Current values for these paramters in AM335x U-Boot code, though reliable, are not fully optimal. The most optimal settings can be derived based on the guidelines published at [1]. A pre-computed set of values with the most optimum settings for AM335x EVM and BeagleBone can be found at [2]. [1] http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips [2] http://processors.wiki.ti.com/index.php/OMAP_and_Sitara_CCS_support#AM335x Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Clean up unused DDR defines, prefix more with 'DDR2'Tom Rini2012-09-01-43/+35
| | | | | | | - Remove a handful of unused defines. - Prefix more values with 'DDR2' as DDR3 will require different values. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Move the call to ddr_pll_config, make it take the frequencyTom Rini2012-09-01-3/+5
| | | | | | | | Depending on if we have DDR2 or DDR3 on the board we will need to call ddr_pll_config with a different value. This call can be delayed slightly to the point where we know which type of memory we have. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Pass to config_ddr the type of memory that is connectedTom Rini2012-09-01-20/+31
| | | | | | | | | We need to pass in the type of memory that is connected to the board. The only reliable way to do this is to know what type of board we are running on (which later will be knowable in s_init()). For now, pass in the value of DDR2. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Make config_cmd_ctrl / config_ddr_data take const structsTom Rini2012-09-01-61/+48
| | | | | | | | | Rework the EMIF4/DDR code slightly to setup the structs that config_cmd_ctrl and config_ddr_data take to be setup at compile time and mark them as const. This lets us simplify the calling path slightly as well as making it easier to deal with DDR3. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework DDR2 EMIF initalization slightlyTom Rini2012-09-01-15/+2
| | | | | | | With the previous bugfix we now don't need to set two different REF_CTRL values and instead set the final value. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Bugfix to config_sdram()Tom Rini2012-09-01-2/+1
| | | | | | | When we change SDRAM_CONFIG this triggers a refresh based on all of the parameters that we have programmed so we must do this last. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Remove extra check in enable_ddr_clocksTom Rini2012-09-01-5/+0
| | | | | | | We do not need to check for EMIF_GCLK and L3_GCLK being active. This was a hold-over from bringup and no longer required. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Convert to using <asm/emif.h> to describe the EMIFTom Rini2012-09-01-41/+15
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Remove DMM_BASE defineTom Rini2012-09-01-1/+0
| | | | | | The am33xx does not have a DMM, so don't define the base. Signed-off-by: Tom Rini <trini@ti.com>
* am335x_evm: Update config for common usageTom Rini2012-09-01-10/+60
| | | | | | | | | | - Add default commands - Add HUSH parser - Make environment, malloc areas larger - Add ATAGS and OF_LIBFDT - Add defaults to boot ramdisk and MMC, use uEnv.txt Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Enable gpio0 clockTom Rini2012-09-01-0/+4
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: igep00x0: add SPL support for IGEP-based boardsJavier Martinez Canillas2012-09-01-68/+147
| | | | | | | This patch adds SPL support for IGEP-based boards. Tested on an IGEPv2 Rev.C board with Micron NAND Flash memory. Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
* OMAP3: mem: Add Numonyx OneNAND 200MHz timing informationJavier Martinez Canillas2012-09-01-0/+29
| | | | Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
* OMAP3: igep00x0: Add config option to choose flash storage memoryJavier Martinez Canillas2012-09-01-2/+31
| | | | | | | | IGEP-based boards can have two different flash memories, a OneNAND or a NAND device. Add a configuration option for to choose which memory to use. Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
* am335x_evm: CPSW supportChandan Nath2012-09-01-1/+110
| | | | | | | | | This patch adds board-specific initialization for CPSW on TI AM335X based boards. Tested on BeagleBone. Signed-off-by: Chandan Nath <chandan.nath@ti.com> [Ilya: split board-specific part into separate patch] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* am335x_evm: read the on-board EEPROMIlya Yanok2012-09-01-2/+70
| | | | | | | | Read the on-board EEPROM during startup to detect the version of the board we are running on (as for now only BeagleBone vs EVM detection is supported). Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* am33xx: pin mux defintions for CPSW switchChandan Nath2012-09-01-0/+49
| | | | | | | | | This patch adds pin mux settings for CPSW switch found on TI AM335X based boards (MII and RGMII modes). Signed-off-by: Chandan Nath <chandan.nath@ti.com> [Ilya: split pinmux into separate patch] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* am33xx: CPSW init and definitionsChandan Nath2012-09-01-1/+23
| | | | | | | | | This patch adds platform-specific initialization for CPSW switch on TI AM33XX SoCs. Signed-off-by: Chandan Nath <chandan.nath@ti.com> [Ilya: split init out of original patch] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* cpsw: add driver for cpsw ethernet deviceCyril Chemparathy2012-09-01-0/+1043
| | | | | | | | | | | | | | | | | | | CPSW is an on-chip ethernet switch that is found on various SoCs from Texas Instruments. This patch adds a simple driver (based on the Linux driver) for this hardware module. This patch also adds support to clean and flush dcache during packet send and receive. Changes by Sandhya: Added support to clean and flush dcache during packet send/receive and added timeouts. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com> [Ilya: Cleaned cache handling, some style cleanup, some small fixes, use of internal RAM for descriptors] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* beagle: only call DSS code when #defined CONFIG_VIDEO_OMAP3Peter Meerwald2012-09-01-0/+4
| | | | Signed-off-by: Peter Meerwald <p.meerwald@bct-electronic.com>
* serial/ns16550: ns16550 has a different register layout on SOC_DA8XXMikhail Kshevetskiy2012-09-01-1/+10
| | | | | | | | | | also fix NS16550_init() as we need 16x divider Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Sughosh Ganu <urwithsughosh@gmail.com> Tested-by: Sughosh Ganu <urwithsughosh@gmail.com>
* arm/davinci/da850: add uart0 pinmuxMikhail Kshevetskiy2012-09-01-0/+7
| | | | | Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Tested-by: Sughosh Ganu <urwithsughosh@gmail.com>
* arm/davinci: fix DDR2/mDDR memory controller initialization for Omap L138Mikhail Kshevetskiy2012-09-01-7/+20
| | | | | | | | | follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of OMAP-L138 DSP+ARM Processor Technical Reference Manual Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at>
* Revert "arm: armv7: add compile option -mno-unaligned-access if available"Albert ARIBAUD2012-09-01-2/+0
| | | | | | This reverts commit 5347560f5427bcdd48a563b62180481606ac8044, which was applied only to get release 2012.07 functional on as many ARM targets as possible despite mis-aligned accesses.
* omap: am335x_evm: enable i2c1 channelSteve Sakoman2012-09-01-0/+20
| | | | | | | This patch sets up pinmux, enables fclk, and defines CONFIG_I2C_MULTI_BUS Signed-off-by: Steve Sakoman <steve@sakoman.com>
* beagle: removed unused pr_debug #definePeter Meerwald2012-09-01-2/+0
| | | | Signed-off-by: Peter Meerwald <pmeerw@pmeerw.net>
* beagle: fix termination of buddy env settingPeter Meerwald2012-09-01-1/+1
| | | | Signed-off-by: Peter Meerwald <p.meerwald@bct-electronic.com>
* beagle: make get_expansion_id(), get_board_revision(), beagle_display_init() ↵Peter Meerwald2012-09-01-3/+3
| | | | | | static Signed-off-by: Peter Meerwald <p.meerwald@bct-electronic.com>
* igep00x0: default mmcrootfstype to EXT4Javier Martinez Canillas2012-09-01-1/+1
| | | | | | | | | omap2plus_defconfig now has built-in compile support for EXT4 enabled by default now. So, we can use EXT4 as the default root file system type for MMC. Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
* igep00x0: default to OMAP-specific serial driverJavier Martinez Canillas2012-09-01-1/+1
| | | | | | | | | An OMAP specific serial driver was merged on the Linux kenel a long time ago. So, it makes sense to default the console name to OMAP ttyO instead of the generic ttyS naming. Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
* da850/omap-l138: add support for direct NOR boot modeLad, Prabhakar2012-09-01-2/+21
| | | | | | | | | | | This patch adds support for direct NOR boot mode on da850/omap-l138. Added da850evm_direct_nor entry in boards.cfg to allow to build targets. Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
* da850/omap-l138: Add support for NAND SPLLad, Prabhakar2012-09-01-0/+26
| | | | | | | | | | This patch adds configuration required for NAND SP on DA850/OMAP-L138. Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
* da850/omap-l138: Fix NAND flash timingsLad, Prabhakar2012-09-01-5/+5
| | | | | | | | | | | | | | | Though Commit id a3f88293ddd13facd734769c1664d35ab4ed681f (da850evm: setup the NAND flash timings) has configured the AEMIF timings, they are not exactly in sync with the timings used in Linux. Linux is configuring the timing register as 0x08222204, where as currently it configured to 0x00100084 in U-Boot. This issue was found out when support for NAND SPL is added in U-Boot. Without this patch U-Boot does not come up with SPL. Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
* da850/omap-l138: Add support to read u-boot image from MMC/SDLad, Prabhakar2012-09-01-0/+84
| | | | | | | | | | | | | | | DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will be in SPI flash and U-Boot image will be in MMC/SD card. SPL will do the low level initialization and then loads the u-boot image from MMC/SD card. Define CONFIG_SPL_MMC_LOAD macro in the DA850/OMAP-L138 configuration file to enable this feature. Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
* da850/omap-l138: Define SPI specific configs for SPL only when SPI is usedLad, Prabhakar2012-09-01-7/+10
| | | | | | | | | | define SPI specific configs for SPL only when CONFIG_USE_SPIFLASH config is defined Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
* arm, davinci: perform check for initializing global data and serial initLad, Prabhakar2012-09-01-6/+9
| | | | | | | | | | | initialize baudrate, flags, data and serial initialization, only when CONFIG_SPL_LIBCOMMON_SUPPORT is defined. Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com> Acked-by: Christian Riesch <christian.riesch@omicron.at>
* da850/omap-l138: Make MMC and NOR support mutually exclusiveRajashekhara, Sudhakar2012-09-01-0/+2
| | | | | | | | | | | | On Logic PD Rev.3 DA850/OMAP-L138 EVM, NOR and MMC/SD cannot work together. This patch enables the MMC/SD support only when NOR support is disabled. NOR Flash identification works even without this patch, but erase and write will have issues. Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
* da850/omap-l138: modifications for Logic PD Rev.3 AM18xx EVMRajashekhara, Sudhakar2012-09-01-1/+11
| | | | | | | | | | | | | AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for MMC and NOR to work on DA850/OMAP-L138 Rev.3 EVM. When GP0[11] is low, the SD0 interface will not work, but NOR flash will. When GP0[11] is high, SD0 will work but NOR flash will not. Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
* da850/omap-l138: Add MMC support for DA850/OMAP-L138Lad, Prabhakar2012-09-01-0/+64
| | | | | | | | | This patch adds support for MMC/SD on DA850/OMAP-L138. Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
* omap: am33xx: enable gpio supportSteve Sakoman2012-09-01-1/+75
| | | | | | | | | | | This patch uses the code in omap-common to support gpio modules 1-3 on am33xx based boards. It adds base address and register definitions, enables clocks to the modules, and enables building the common gpio code for CONFIG_AM33XX as well as CONFIG_OMAP Signed-off-by: Steve Sakoman <steve@sakoman.com>
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