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* crypto/fsl: Fix RNG instantiation failure.gaurav rana2014-12-15-1/+1
| | | | | | | | | | Corrected the order of arguments in memset in run_descriptor function. Wrong order of argumnets led to improper initialization of members of struct type result. This resulted in RNG instantiation error. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/T10xx: Fix number of portalsJeffrey Ladouceur2014-12-15-8/+8
| | | | | | | | | | | Following boards has incorrect number of portals defined. powerpc/T102xQDS powerpc/T102xRDB powerpc/T1040QDS powerpc/T104xRDB Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: inhibit qman and bman portals by defaultJeffrey Ladouceur2014-12-15-0/+267
| | | | | | | | | Not all portals might be managed and therefore visible. Set the isdr register so that the corresponding isr register won't be set. This is required when supporting power management. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net/fm: update ft_fixup_port to differentiate dual-role macShengzhou Liu2014-12-15-5/+16
| | | | | | | | | | we need to differentiate dual-role MACs into two types: MACs with 10GEC enumeration consistent with DTSEC enumeration(defined by CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Fix DDR TLB mapping leftoverYork Sun2014-12-15-4/+8
| | | | | | | | | | Commit f29f804a93e87c17670607641d120f431a3b0633 generalized the TLB mapping function, but made the DDR mapping leftover size to zero, causing the message not printed. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alexander Graf <agraf@suse.de> CC: Scott Wood <scottwood@freescale.com>
* driver/ddr/fsl: Fix MRC_CYC calculation for DDR3York Sun2014-12-15-1/+20
| | | | | | | | | | For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec. DDR4 is not affected by this change. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/p2041rdb: enable generic board configsShaohui Xie2014-12-15-0/+2
| | | | | | | | | Add following configs in header file: CONFIG_SYS_GENERIC_BOARD CONFIG_DISPLAY_BOARDINFO Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t4240rdb: Convert to use generic board codeChunhe Lan2014-12-15-0/+2
| | | | | Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/bsc913x: Convert to use generic board codeharninder rai2014-12-15-0/+6
| | | | | Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-12-11-7/+194
|\ | | | | | | | | | | | | Conflicts: board/freescale/mx6sxsabresd/mx6sxsabresd.c Signed-off-by: Tom Rini <trini@ti.com>
| * usb: ehci: do not set the LSB of Current qTD pointerMasahiro Yamada2014-11-19-1/+0
| | | | | | | | | | | | | | According to EHCI specification, the LSB of DWORD 3 of Queue Head (Current qTD Pointer) is not T-bit, but always zero. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * test: ums: Add sleep before unmount directoryLukasz Majewski2014-11-14-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change helps to run script on machines with quite long uptime. Without this the following error emerges: File: ./dat_14M.img umount: /mnt/tmp-ums-test: device is busy. (In some cases useful info about processes that use the device is found by lsof(8) or fuser(1)) TX: md5sum:083d3d22b542d3ecba61b12d17e03f9f mount: /dev/sdd6 already mounted or /mnt/tmp-ums-test busy mount: according to mtab, /dev/sdd6 is already mounted on /mnt/tmp-ums-test Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * dfu: thor: fix: Modify dfu_get_alt() function to support absolute pathsLukasz Majewski2014-11-14-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently the ext4 file system imposed passing absolute path with its file name parameter. As a result dfu_alt_info env variable has been modified to provide absolute path when ext4 file system is accessed (e.g. /uImage ext4 0 2;). Unfortunately, lthor flashing program provides plain file name (like uImage) and hence those two file names do not match anymore. Presented commit also allows lthor to write files to sub directories (like /boot/bin/uImage). Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * imx:mx6sxsabresd add board level support for usbPeng Fan2014-11-14-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode There are two usb port on mx6sxsabresd board: 1. otg port 2. host port The following are the connection between usb controller and board usb interface, host port has not ID pin set: otg1 core <---> board otg port otg2 core <---> board host port In order to make host port work, board_usb_phy_mode return USB_INIT_HOST to make host port work in HOST mode. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <B37916@freescale.com>
| * imx:mx6slevk add board level support for usbPeng Fan2014-11-14-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode There are two usb port on mx6slevk board: 1. otg port 2. host port The following are the connection between usb controller and board usb interface, host port has not ID pin set: otg1 core <---> board otg port otg2 core <---> board host port In order to make host port work, board_usb_phy_mode return USB_INIT_HOST to let host port work in host mode. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <B37916@freescale.com>
| * usb:ehci-mx6 add phy mode query functionPeng Fan2014-11-14-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | usb_phy_enable should return status bit, but not phy mode bit, thus add a new function usb_phy_mode to query the PHY for it's mode and make usb_phy_enable just return 0 but not 'phy_ctrl & USBPHY_CTRL_OTG_ID'. Include a new board weak function board_usb_phy_mode. If board code does not reimplement this function, it just call usb_phy_mode and return usb_phy_mode's return value. The reason to include such a weak function is: " SOC OTG core <--connect--> board HOST port, but no pin id for the board host port, so board can not use usb_phy_mode to return the phy mode, but define it's own rule." Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <B37916@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-12-11-221/+1904
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| * | ARM: HYP/non-sec: Fix the ARCH Timer frequency setting for sun7iXiubo Li2014-12-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Earlier commit 73a1cb27 mistakenly used CONFIG_SYS_TIMER_CLK_FREQ. It should be CONFIG_TIMER_CLK_FREQ. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> [York Sun: This is the difference between two patch versions] Reviewed-by: York Sun <yorksun@freescale.com>
| * | kconfig: ls102xa: Change the prompt messagesAlison Wang2014-12-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR boards, the prompt message "Support ls1021aqds_nor" in Kconfig is not clear. This patch changes it to "Support ls1021aqds". Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver/mtd: Fix IFC compilation warningsJaiprakash Singh2014-12-11-1/+1
| | | | | | | | | | | | | | | | | | | | | 'eccstat' array elements might be used uninitialized Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ARM: ls102xa: Setting device's stream id for SMMUs.Xiubo Li2014-12-11-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ARM: ls102xa: allow all the peripheral access permission as R/W.Xiubo Li2014-12-11-0/+335
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ls102xa: changing a few targets' configurations.Xiubo Li2014-12-11-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ls1021a: adding a secondary core boot address and kick functionsXiubo Li2014-12-11-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the LS1021A specific manner. Define the board specific smp_kick_all_cpus() functioin to boot a secondary core. Here the BRR contains control bits for enabling boot for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be released for booting or to remain in boot holdoff. All other cores remain in boot holdoff until their corresponding bit is set. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.Xiubo Li2014-12-11-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some SoCs, the system clock frequency may not equal to the ARCH Timer's frequency. This patch uses the CONFIG_TIMER_CLK_FREQ instead of CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer macor could be set separately and without interfering each other. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ARM: HYP/non-sec: add the pen address BE mode support.Xiubo Li2014-12-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some SoCs, the pen address register maybe in BE mode and the CPUs are in LE mode. This patch adds BE mode support for smp pen address. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | fsl/sleep: updated the deep sleep framework for QorIQ platformsTang Yuantian2014-12-11-56/+322
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers: usb: fsl: Check USB Erratum A007792 applicabilityNikhil Badola2014-12-11-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | Check USB Erratum A007792 applicability. If applicable, add corresponding property in the device tree via device tree fixup Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers: usb: fsl: Add USB device-tree errata frameworkNikhil Badola2014-12-11-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new framework for fsl usb erratum handling to standardize erratum checking only inside Uboot. Information to kernel is passed via a boolean property corresponding to erratum, hence eliminating need for code duplication inside kernel Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | drivers: usb: Make usb device-tree fixup code architecture independentNikhil Badola2014-12-11-104/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/" so that it works independent of architecture it is running on Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ls1021aqds: add hwconfig setting to do pin muxYao Yuan2014-12-11-3/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale LS1021AQDS share some pins, so Add the hwconfig option that allows the user to choose which the function he wants. The main pin mux IP is: eSDHC, SAI, IIC2, RGMII, CAN, SAI. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Add NAND boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR boardAlison Wang2014-12-11-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Fix SD/NAND/QSPI boot defination error for QE supportAlison Wang2014-12-11-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | The SD/NAND/QSPI boot definations are wrong for QE support, this patch is to fix this error. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls1021a: Add CONFIG_DOS_PARTITION and CONFIG_CMD_FAT supportAlison Wang2014-12-11-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | This patch will fix the bug that the partitions on the SD card could not be accessed and add the support for the FAT fs. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Add SD boot support for LS1021ATWR boardAlison Wang2014-12-11-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SD boot support for LS1021ATWR board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Chen Lu <chen.lu@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Add SD boot support for LS1021AQDS boardAlison Wang2014-12-11-1/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ls102xa: qixis: Add CONFIG_QIXIS_I2C_ACCESS macroAlison Wang2014-12-11-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Through adding CONFIG_QIXIS_I2C_ACCESS macro, QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used for both i2c and ifc access to QIXIS FPGA. This is more convenient for coding. Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | kconfig: ls1021a: add SUPPORT_SPLAlison Wang2014-12-11-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add SUPPORT_SPL feature for SD and NAND boot on LS1021AQDS and LS1021ATWR. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: spl: Add I2C linker list in generic .ldsAlison Wang2014-12-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On LS1, DDR is initialized by reading SPD through I2C interface in SPL code. For I2C, ll_entry_count() is called, and it returns the number of elements of a linker-generated array placed into subsection of .u_boot_list section specified by _list argument. So add I2C linker list in the generic .lds to fix the issue about using I2C in SPL. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | spl: Use u-boot.img instead of u-boot.binAlison Wang2014-12-11-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In SD boot, the magic number of u-boot image will be checked. For LS102xA, u-boot.bin doesn't have the magic number. So use u-boot.img which includes the magic number instead of u-boot.bin when producing u-boot-with-spl-pbl.bin. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ls102xa: pblimage: Add pblimage tool support for LS102xAAlison Wang2014-12-11-36/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For LS102xA, the size of spl/u-boot-spl.bin is variable. This patch adds the support to deal with the variable u-boot size in pblimage tool. It will be padded to 64 byte boundary. Use pblimage_check_params() to add the specific operations for ARM, such as PBI CRC and END command and the calculation of pbl_cmd_initaddr. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ls1021aqds: set the default I2C channel before DDR initChenhui Zhao2014-12-11-13/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | When resuming from deep sleep, the I2C channel may not be in the default channel. So, switch to the default channel before accessing DDR SPD. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Update PCIe dts node statusMinghuan Lian2014-12-11-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: clear EPU registers for deep sleepchenhui zhao2014-12-11-0/+143
| | | | | | | | | | | | | | | | | | | | | | | | After wakeup from deep sleep, Clear EPU registers as early as possible to prevent from possible issue. It's also safe to clear at normal boot. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: fixed a bus frequency setting errorTang Yuantian2014-12-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The bus frequency in SOC node should be clock frequency of platform. That is not true if it is devided by 2. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-10-45/+66
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| * | | arm: vf610: improve evaluation of reset sourceStefan Agner2014-12-01-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve the evaluation of the reset source. Bit description according to latest reference manual rev. 7. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | | mx6sabre_common: Use the default CONFIG_SYS_PBSIZEFabio Estevam2014-12-01-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into the console and hitting enter afterwards, causes a hang in the system because CONFIG_SYS_PBSIZE is not capable of storing the characters of the error message: "Unknown command '' - try 'help'". Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h to solve this problem. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | config_fallbacks: Add a default entry for CONFIG_SYS_PBSIZEFabio Estevam2014-12-01-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into the console and hitting enter afterwards, causes a hang in the system because CONFIG_SYS_PBSIZE is not capable of storing the characters of the error message: "Unknown command '' - try 'help'". Provide a default size for CONFIG_SYS_PBSIZE so that it can store the error message and allows the error message to be printed correctly with no hang. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
generated by cgit v1.1 at 2024-11-17 10:08:21 +0000