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* ppc4xx: Correctly setup ranges property in ebc nodeStefan Roese2008-10-21-17/+59
| | | | | | | | Previously only the NOR flash mapping was written into the ranges property of the ebc node. This patch now writes all enabled chip select areas into the ranges property. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add GDSys neo 405EP board supportDirk Eibach2008-10-21-0/+547
| | | | | Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update configs for Netstal boardsNiklaus Giger2008-10-21-275/+292
| | | | | | | | | | I reorganized my config files, putting the common stuff into netstal-common.h (got the idea by looking a amcc-common.h from Stefan). Added stuff to boot the new powerpc linux via NFS (only tested with HCU4). Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add routine to retrieve CPU numberAdam Graham2008-10-21-1/+21
| | | | | | | | | | | | Provide a weak defined routine to retrieve the CPU number for reference boards that have multiple CPU's. Default behavior is the existing single CPU print output. Reference boards with multiple CPU's need to provide a board specific routine. See board/amcc/arches/arches.c for an example. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add static support for 44x IBM SDRAM ControllerAdam Graham2008-10-21-18/+53
| | | | | | | | | | This patch add the capability to configure a PPC440 based IBM SDRAM Controller with static, compiled-in, values. PPC440 memory subsystem includes a Memory Queue core. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add AMCC Arches board support (dual 460GT)Adam Graham2008-10-21-19/+384
| | | | | | | | | | | | | | The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of /home/stefan/git/u-boot/u-bootStefan Roese2008-10-21-54307/+58233
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| * Merge 'next' branchWolfgang Denk2008-10-18-54298/+58094
| |\ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/freescale/mpc8536ds/mpc8536ds.c include/configs/mgcoge.h Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * mgcoge: add redundant environment sectorHeiko Schocher2008-10-18-0/+5
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgsuvd: update size of environmentHeiko Schocher2008-10-18-3/+1
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * Enabled the Freescale SGMII riser card on 8536DSJason Jin2008-10-18-0/+45
| | | | | | | | | | | | Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| | * Enabled the Freescale SGMII riser card on 8572DSLiu Yu2008-10-18-0/+72
| | | | | | | | | | | | | | | | | | | | | This patch based on Andy's work. Including command 'pixis_set_sgmii' support. Signed-off-by: Liu Yu <yu.liu@freescale.com>
| | * Make pixis_set_sgmii more general to support MPC85xx boards.Liu Yu2008-10-18-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pixis sgmii command depend on the FPGA support on the board, some 85xx boards support SGMII riser card but did not support this command, define CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command. Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and PIXIS_VCFGEN1_MASK in header file for both boards. Signed-off-by: Liu Yu <yu.liu@freescale.com>
| | * Add cpu/8xxx to TAGS_SUBDIRSEd Swarthout2008-10-18-0/+2
| | | | | | | | | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| | * fsl_law clear enable before changing.Ed Swarthout2008-10-18-0/+1
| | | | | | | | | | | | | | | | | | | | | Debug sessions may have left enabled laws. Changing lawbar with an unkown enabled tgtid could cause problems. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| | * mpc8572 additional end-point modeEd Swarthout2008-10-18-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mpc8572 supports all pcie controllers as end-points with cfg_host_agent=0. Include host_agent == 0 decode for end-point determination. This is not needed for the ds reference board since pcie3 will be a host in order to connect to the uli chip. Include it here as a reference for other mpc8572 boards. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| | * 85xx if NUM_CPUS>1, print cpu numberEd Swarthout2008-10-18-0/+5
| | | | | | | | | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| | * pixis do not print long help if not configuredEd Swarthout2008-10-18-0/+4
| | | | | | | | | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| | * Have u-boot pass stashing parameters into device treeAndy Fleming2008-10-18-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some cores don't support ethernet stashing at all, and some instances have errata. Adds 3 properties to gianfar nodes which support stashing. For now, just add this support to 85xx SoCs. Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * Add DDR options setting on MPC8641HPCN boardHaiying Wang2008-10-18-36/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Add ddr interleaving suppport for MPC8572DS boardHaiying Wang2008-10-18-29/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay, 2T based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. * Set memory controller interleaving mode to bank interleaving, and disable bank(chip select) interleaving mode by default, because the default on-board DDR DIMMs are 2x512MB single-rank. * Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Add debug information for DDR controller registersHaiying Wang2008-10-18-0/+13
| | | | | | | | | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Check DDR interleaving modeHaiying Wang2008-10-18-5/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | * Check DDR interleaving mode from environment by reading memctl_intlv_ctl and ba_intlv_ctl. * Print DDR interleaving mode information * Add doc/README.fsl-ddr to describe the interleaving setting Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Pass dimm parameters to populate populate controller optionsHaiying Wang2008-10-18-24/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Make DDR interleaving mode work correctlyHaiying Wang2008-10-18-12/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix some bugs: 1. Correctly set intlv_ctl in cs_config. 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled. 3. Set base_address and total memory for each ddr controller in memory controller interleaving mode. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * 85xx: Enable interrupt and setexpr commands on Freescale 85xx boardsKumar Gala2008-10-18-0/+18
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * 85xx: Improve flash remapping on MPC8572DS & MPC8536DSKumar Gala2008-10-18-14/+10
| | | | | | | | | | | | | | | | | | | | | | | | Changing the flash from cacheable to cache-inhibited was taking a significant amount of time due to the fact that we were iterating over the full 256M of flash. Instead we can just flush the L1 d-cache and invalidate the i-cache. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * 85xx: Export invalidate_{i,d}cache and add flush_dcacheKumar Gala2008-10-18-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | Added the ability for C code to invalidate the i/d-cache's and to flush the d-cache. This allows us to more efficient change mappings from cache-able to cache-inhibited. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * mgcoge, mgsuvd: extract more common codeHeiko Schocher2008-10-18-90/+56
| | | | | | | | | | | | | | | | | | | | | | | | in ft_blob_update () for both boards was an unneccessary repetition of code, which this patch moves in a common function for this boards. Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgcoge, mgsuvd: use in_*/out_* accesorsHeiko Schocher2008-10-18-4/+6
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgsuvd: fix compiler warning when using soft_i2c driverHeiko Schocher2008-10-18-10/+15
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgsuvd: fix coding styleHeiko Schocher2008-10-18-44/+33
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgcoge: Second Flash on CS5 not on CS1Heiko Schocher2008-10-18-1/+1
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * Added arch_lmb_reserve to allow arch specific memory regions protectionKumar Gala2008-10-18-42/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | Each architecture has different ways of determine what regions of memory might not be valid to get overwritten when we boot. This provides a hook to allow them to reserve any regions they care about. Currently only ppc, m68k and sparc need/use this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * mgcoge: added CONFIG_FIT to support the new u-boot image formatHeiko Schocher2008-10-18-0/+1
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-53844/+53844
| | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| | * 74xx/7xx/86xx: Rename flush_data_cache to flush_dcache to match 85xx versionKumar Gala2008-10-18-10/+10
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * Expose command table search for sub-commandsKumar Gala2008-10-18-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Sub-command can benefit from using the same table and search functions that top level commands have. Expose this functionality by refactoring find_cmd() and introducing find_cmd_tbl() that sub-command processing can call. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * mgsuvd, mgcoge: added BOOTCOUNT feature.Heiko Schocher2008-10-18-0/+4
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgcoge, mgsuvd: added support for the IVM EEprom.Heiko Schocher2008-10-18-0/+314
| | | | | | | | | | | | | | | | | | | | | | | | The EEprom contains some Manufacturerinformation, which are read from u-boot at boot time, and saved in same hush shell variables. Signed-off-by: Heiko Schocher <hs@denx.de>
| | * hush: add showvar command for hush shell.Heiko Schocher2008-10-18-8/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new command shows the local variables defined in the hush shell: => help showvar showvar - print values of all hushshell variables showvar name ... - print value of hushshell variable 'name' Also make the set_local_var() and unset_local_var () no longer static, so it is possible to define local hush shell variables at boot time. If CONFIG_HUSH_INIT_VAR is defined, u-boot calls hush_init_var (), where boardspecific code can define local hush shell variables at boottime. Signed-off-by: Heiko Schocher <hs@denx.de>
| | * I2C: adding new "i2c bus" Command to the I2C Subsystem.Heiko Schocher2008-10-18-2/+367
| | | | | | | | | | | | | | | | | | | | | With this Command it is possible to add new I2C Busses, which are behind 1 .. n I2C Muxes. Details see README. Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgcoge, mgsuvd: add board specific I2C deblocking mechanism.Heiko Schocher2008-10-18-2/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As documented in doc/I2C_Edge_Conditions, adding a board specific deblocking mechanism via CFG_I2C_INIT_BOARD for the mgcoge and mgsuvd board. This code was originally written by Keymile in association with Anatech and Atmel in 1998. The Code toggels the SCL until the SCA line goes to HIGH (max. 16 times). And after this, a start condition is sent. This is another approach to deblock the I2C Bus. The soft I2C driver actually sends 9 clocks with SDA High, and then a stop at the end, to deblock the I2C Bus. Maybe we should use the approach from Keymile as the new standard? Signed-off-by: Heiko Schocher <hs@denx.de>
| | * soft_i2c: Add CFG_I2C_INIT_BOARD optionHeiko Schocher2008-10-18-0/+11
| | | | | | | | | | | | | | | | | | | | | This patch adds the option for a boardspecific I2C deblocking mechanism for the soft i2c driver. Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgcoge, mgsuvd: add DTT (LM75) support.Heiko Schocher2008-10-18-0/+18
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * lm75: Make the LM75 MULTI_BUS compatible.Heiko Schocher2008-10-18-0/+6
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * lm75: fix Codingstyle issues.Heiko Schocher2008-10-18-123/+99
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgcoge, mgsuvd: added EEprom support.Heiko Schocher2008-10-18-0/+15
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * mgcoge, mgsuvd: add I2C support.Heiko Schocher2008-10-18-2/+91
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * soft_i2c: prevent compiler warnings if driver does not use CPU Pins.Heiko Schocher2008-10-18-37/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following warnings, when using the soft_i2c driver using no CPU pins on MPC82xx or MPC8xx systems: soft_i2c.c: In function 'send_reset': soft_i2c.c:93: warning: unused variable 'immr' soft_i2c.c: In function 'send_start': soft_i2c.c:124: warning: unused variable 'immr' soft_i2c.c: In function 'send_stop': soft_i2c.c:146: warning: unused variable 'immr' soft_i2c.c: In function 'send_ack': soft_i2c.c:171: warning: unused variable 'immr' soft_i2c.c: In function 'write_byte': soft_i2c.c:196: warning: unused variable 'immr' soft_i2c.c: In function 'read_byte': soft_i2c.c:244: warning: unused variable 'immr' Signed-off-by: Heiko Schocher <hs@denx.de>
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