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* usb_storage: fix ehci driver max transfer sizeStefan Herbrechtsmeier2012-07-18-17/+20
| | | | | | | | | | | | | | | | The commit 5dd95cf93dfffa1d19a1928990852aac9f55b9d9 'usb_storage: Fix EHCI "out of buffer pointers" with CD-ROM' introduce a bug in usb_storage as it wrongly assumes that every transfer can use 4096 bytes per qt_buffer. This is wrong if the start address of the data is not page aligned to 4096 bytes and leads to 'EHCI timed out on TD' messages because of 'out of buffer pointers' in ehci_td_buffer function. The bug appears during load of a fragmented file and read from or write to an unaligned memory address. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
* smsc95xx: align buffers to cache line sizeIlya Yanok2012-07-18-4/+9
| | | | | | | Align buffers passed to the USB code to cache line size so they can be DMAed safely. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* ehci-hcd: change debug() to printf() in case of errorsIlya Yanok2012-07-18-3/+3
| | | | | | Printing message could be useful if something goes really wrong. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* usb: check return value of submit_{control, bulk}_msgIlya Yanok2012-07-18-2/+4
| | | | | | | Return values of submit_{control,bulk}_msg() functions should be checked to detect possible error. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* usb: pass cache-aligned buffer to usb_get_descriptor()Ilya Yanok2012-07-18-2/+4
| | | | | | | usb_get_descriptor passes it's buffer argument directly to usb_control_msg() so it has to be properly aligned/padded. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* ehci-hcd: fix external buffer cache handlingIlya Yanok2012-07-18-9/+14
| | | | | | | | | | | | | | | | | | | | | | | Buffer coming from upper layers should be cacheline aligned/padded to perform safe cache operations. For now we don't do bounce buffering so getting unaligned buffer is an upper layer error. We can't check if the buffer is properly padded with current interface so just assume it is (consider changing with in the future). The following changes are done: 1. Remove useless length alignment check. We get actual transfer length not the size of the underlying buffer so it's perfectly valid for it to be unaligned. 2. Move flush_dcache_range() out of while loop or it will flush too much. 3. Don't try to fix buffer address before calling invalidate: if it's unaligned it's an error anyway so let cache subsystem cry about that. 4. Fix end buffer address to be cacheline aligned assuming upper layer reserved enough space. This is potentially dangerous operation so upper layers should be careful about that. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignmentTom Rini2012-07-18-30/+43
| | | | | | | | | | | | | | | | | | The USB spec says that 32 bytes is the minimum required alignment. However on some platforms we have a larger minimum requirement for cache coherency. In those cases, use that value rather than the USB spec minimum. We add a cpp check to <usb.h> to define USB_DMA_MINALIGN and make use of it in ehci-hcd.c and musb_core.h. We cannot use MAX() here as we are not allowed to have tests inside of align(...). Signed-off-by: Tom Rini <trini@ti.com> [marek.vasut]: introduce some crazy macro voodoo Signed-off-by: Marek Vasut <marex@denx.de> [ilya.yanok]: moved external buffer fixes to separate patch, we use {ALLOC,DEFINE}_ALIGN_BUFFER macros with alignment of USB_DMA_MINALIGN for qh_list, qh and qtd structures to make sure they are proper aligned for both controller and cache operations. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* ehci-hcd: program asynclistaddr before every transferIlya Yanok2012-07-18-5/+3
| | | | | | | | | | | | Move or_asynclistaddr programming to ehci_submit_async() function to make sure queue head is properly programmed before every transfer. This solves the problem with changing qh address. Also remove unneeded qh_list->qh_link reprogramming at the end of transfer. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* common.h: Introduce DEFINE_CACHE_ALIGN_BUFFERMarek Vasut2012-07-18-3/+18
| | | | | | | | | | | | This is the out-of-function-scope counterpart of ALLOC_CACHE_ALIGN_BUFFER. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> [ilya.yanok]: added missing <linux/compiler.h> include and {DEFINE,ALLOC}_ALIGN_BUFFER macros allowing explicit alignment specification. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* ehci-omap: Do not call dcache_off from omap_ehci_hcd_initTom Rini2012-07-18-1/+0
| | | | | | | | | This has never been completely sufficient and now happens too late to paper over the cache coherency problems with the current USB stack. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* Merge branch 'next' of git://git.denx.de/u-boot-videoWolfgang Denk2012-07-18-135/+166
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.denx.de/u-boot-video: ipu_common: Add ldb_clk for use in parenting the pixel clock ipu_common: Do not hardcode the ipu_clk frequency ipu_common: Rename MXC_CCM_BASE ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53 ipu_common: Only apply the erratum to MX51 video: Rename CONFIG_VIDEO_MX5 mx6: Allow mx6 to access the IPUv3 registers common lcd: minor coding style changes Signed-off-by: Wolfgang Denk <wd@denx.de>
| * ipu_common: Add ldb_clk for use in parenting the pixel clockEric Nelson2012-07-10-3/+12
| | | | | | | | | | | | | | Add ldb_clk for use in parenting the pixel clock. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ipu_common: Do not hardcode the ipu_clk frequencyFabio Estevam2012-07-10-1/+4
| | | | | | | | | | | | Do not hardcode the ipu_clk frequency and let the board file pass this value. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ipu_common: Rename MXC_CCM_BASEFabio Estevam2012-07-10-1/+1
| | | | | | | | | | | | Rename MXC_CCM_BASE to CCM_BASE_ADDR as this is already defined for MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53Fabio Estevam2012-07-10-1/+4
| | | | | | | | | | | | | | The registers accessed inside clk_ipu_enable/disable are not present on MX6, so make sure they only run on MX51 and MX53. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ipu_common: Only apply the erratum to MX51Fabio Estevam2012-07-10-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The following erratum : "ENGcm08316 IPU: Clarification regarding the bypass mode registers setup for display and camera interfaces" only applies to mx51, so restrict its usage for this SoC only. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * video: Rename CONFIG_VIDEO_MX5Fabio Estevam2012-07-10-5/+5
| | | | | | | | | | | | Rename CONFIG_VIDEO_MX5 as this driver can also be used on mx6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: Allow mx6 to access the IPUv3 registersFabio Estevam2012-07-10-3/+14
| | | | | | | | | | | | Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * common lcd: minor coding style changesNikita Kiryanov2012-07-10-121/+124
| | | | | | | | | | | | | | No functional changes Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* | Merge branch 'master' of git://git.denx.de/u-boot-niosWolfgang Denk2012-07-18-15/+9
|\ \ | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-nios: nios2: move gd and bd into BSS Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | nios2: move gd and bd into BSSThomas Chou2012-07-16-15/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | As suggested by Graeme Russ, move gd and bd data structrures to BSS instead of calculating the locations around the stack and heap. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Mike Frysinger <vapier@gentoo.org>
* | | FSL/eSDHC: enable the clock to detect the SD cardJerry Huang2012-07-13-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For FSL low-end processors (VVN2.2), in order to detect the SD card, we should enable PEREN, HCKEN and IPGEN to enable the clock. Otherwise, after booting the u-boot, and then inserting the SD card, the SD card can't be detected. For SDHC VVN2.3 IP, these bits are reserved, and SDCLKEN is used. And when accessing to these reserved bit, no any impact happened. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> CC: Andy Fleming <afleming@gmail.com> CC: Marek Vasut <marex@denx.de> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | SD/MMC: check the card status during erase operationJerry Huang2012-07-13-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the function 'mmc_send_status' to check the card status. only when the card is ready, driver can send the next erase command to the card, otherwise, the erase will failed: => mmc erase 0 1 MMC erase: dev # 0, block # 0, count 1 ... 1 blocks erase: OK => mmc erase 0 2 MMC erase: dev # 0, block # 0, count 2 ... mmc erase failed 1 blocks erase: ERROR => mmc erase 0 4 MMC erase: dev # 0, block # 0, count 4 ... mmc erase failed 1 blocks erase: ERROR Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> CC: Andy Fleming <afleming@gmail.com> CC: Marek Vasut <marex@denx.de> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | mmc:fix Call mmc_init() when executing mmc_get_dev()Łukasz Majewski2012-07-13-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code adds call to mmc_init(), for partition related commands (e.g. fatls, fatinfo etc.). It is safe to call mmc_init() multiple times since mmc->has_init flag prevents from multiple initialization. The FAT related code calls get_dev high level method and then uses elements from mmc->block_dev, which is uninitialized until the mmc_init (and thereof mmc_startup) is called. This problem appears on boards, which don't use mmc as the default place for envs Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | mmc: remove the hard setting for tran_speedJaehoon Chung2012-07-13-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | mmc_set_clock is set to the hard-coding. But i think good that use the tran_speed value. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | i.MX: fsl_esdhc: allow use with cache enabled.Eric Nelson2012-07-13-1/+16
|/ / | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2012-07-12-36/+51
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-i2c: mx28evk: Add I2C support mxs-i2c: Fix internal address byte order mxc_i2c: remove setting speed at each start mx6qsabrelite: add i2c support mxc_i2c: specify i2c base address in config file Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | mx28evk: Add I2C supportFabio Estevam2012-07-11-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C support. Tested by placing a 24LC16 EEPROM into the U50 slot which comes empty from factory. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * | mxs-i2c: Fix internal address byte orderTorsten Fleischer2012-07-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Large EEPROMs, e.g. 24lc32, need 2 byte to address the internal memory. These devices require that the high byte of the internal address has to be written first. The mxs_i2c driver currently writes the address' low byte first. The following patch fixes the byte order of the internal address that should be written to the I2C device. Signed-off-by: Torsten Fleischer <to-fleischer@t-online.de> CC: Marek Vasut <marex@denx.de> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | mxc_i2c: remove setting speed at each startTroy Kisky2012-07-11-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other then being very weird, this code was also wrong. For example, say I set speed to 100K. I'll read back the speed as 85937. But the speed is really 85937.5, so we I reset the speed to 85937, I'll get 73660.7. After a couple of transactions my speed is now exactly 68750 so it will remain there. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | mx6qsabrelite: add i2c supportTroy Kisky2012-07-11-0/+19
| | | | | | | | | | | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | mxc_i2c: specify i2c base address in config fileTroy Kisky2012-07-11-29/+20
| |/ | | | | | | | | | | | | | | | | The following platforms had their config files changed flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd and mx53loco. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | net: fix typo in arp clean upMike Frysinger2012-07-10-1/+1
| | | | | | | | | | | | | | | | | | | | The clean up patch missed an &, so we end up passing an int rather than a pointer to the sprintf function. arp.c: In function 'ArpReceive': arp.c:197: warning: format '%p' expects type 'void *', but argument 3 has type 'int' Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | net/sh-ether: Fix build by removing ECSIPR_BRCRXIP and otherNobuhiro Iwamatsu2012-07-10-4/+3
|/ | | | | | | | When support sh7734 of sh-ether, ECSIPR_BRCRXIP and other were removed. Therefore SH7757 and SH7724 can not build. This revise this probelem. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
* Prepare v2012.07-rc1Wolfgang Denk2012-07-10-3/+3
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Minor Coding Style cleanupWolfgang Denk2012-07-10-9/+3
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2012-07-10-216/+628
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: tegra: define fdt_load/fdt_high variables tegra: enable bootz command tegra: usb: Fix device enumeration problem of USB1 tegra: trimslice: set up serial flash pinmux tegra: add pin_mux_spi() board initialization function tegra: add GMC/GMD funcmux entry for SFLASH tegra: bootcmd: start USB only when needed tegra: bootcmd enhancements tegra: add enterrcm command tegra: enable CONFIG_ENV_VARS_UBOOT_CONFIG Add env vars describing U-Boot target board tegra: usb: fix wrong error check tegra: add ULPI on USB2 funcmux entry tegra: fix leftover CONFIG_TEGRA2_MMC & _SPI build switches tegra: Add Tamonten Evaluation Carrier support tegra: Use SD write-protect GPIO on Tamonten tegra: Implement gpio_early_init() on Tamonten tegra: Allow boards to perform early GPIO setup tegra: plutux: Add device tree support tegra: medcom: Add device tree support tegra: Rework Tamonten support beagle: add eeprom expansion board info for bct brettl4 Signed-off-by: Wolfgang Denk <wd@denx.de>
| * tegra: define fdt_load/fdt_high variablesStephen Warren2012-07-09-0/+2
| | | | | | | | | | | | | | | | | | | | These variables act like loadaddr, but for a device tree image. Defining them in the environment allows boot scripts to be identical on Tegra20 and Tegra30, which have different memory base addresses, and hence need different values for these variables. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: enable bootz commandStephen Warren2012-07-09-0/+1
| | | | | | | | | | | | | | | | bootz is just like bootm, except that it can boot a raw zImage, without requiring it to be wrapped inside a uImage. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: usb: Fix device enumeration problem of USB1Jim Lin2012-07-09-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A known hardware issue of USB1 port where bit 1 (connect status change) of PORTSC register will be set after issuing Port Reset (like "usb reset" in u-boot command line). This will be treated as an error and stops later device enumeration. Therefore we clear that bit after Port Reset in order to proceed later device enumeration. Signed-off-by: Jim Lin <jilin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: trimslice: set up serial flash pinmuxStephen Warren2012-07-09-0/+5
| | | | | | | | | | | | | | | | | | | | | | When Trimslice is booted from serial flash, the boot ROM does this, so U-Boot doesn't need to. However, booting from the SD slot for recovery purposes, the boot ROM does not set up the pinmux for serial flash. Add code to U-Boot to set this up, so that an SD-based recovery U-Boot image can upgrade the U-Boot in serial flash. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: add pin_mux_spi() board initialization functionStephen Warren2012-07-09-0/+7
| | | | | | | | | | | | | | | | Boards can override this to set up the pinmux correctly to access serial flash. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: add GMC/GMD funcmux entry for SFLASHStephen Warren2012-07-09-0/+13
| | | | | | | | | | | | | | This is used on TrimSlice. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: bootcmd: start USB only when neededStephen Warren2012-07-09-3/+11
| | | | | | | | | | | | | | | | | | | | Instead of initializing USB as soon as bootcmd is executed, defer it until the first boot device that (potentially in the case of network) uses USB is scanned. This avoids initializing USB when booting from MMC, so speeds that up. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: bootcmd enhancementsStephen Warren2012-07-09-30/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Place the list of searched boot devices, file-system types, boot file locations/prefixes, and boot script names into variables. This allows the user to override them directly (e.g. to change boot order, or select the specific values they use) without having to edit the main bootcmd and script_boot variables. The default boot order is changed from USB, MMC, DHCP to MMC, USB, DHCP. This speeds up the typical MMC boot case. People who want USB boot can now edit variable boot_targets appropriately. Also, reformat BOOTCMDS_COMMON to fit within 80 columns. Potential future enhancements might be: * Allow boards to specify which of bootcmd_mmc0/... should be defined, based on the HW they contain. * Allow boards to influence the order that the boot targets are added into the boot_targets variable. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: add enterrcm commandStephen Warren2012-07-09-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's boot ROM supports a mode whereby code may be downloaded and flash programmed over a USB connection. On dev boards, this is typically entered by holding down a "force recovery" button and resetting the CPU. However, not all boards have such a button (one example is the Compulab Trimslice), so a method to enter RCM from software is useful. This change implements the command "enterrcm" to do this, and enables it for all Tegra boards by default. Even on boards other than Trimslice, controlling this over a UART may be useful, e.g. to allow simple remote control without the need for mechanical button actuators, or hooking up relays/... to the button. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: enable CONFIG_ENV_VARS_UBOOT_CONFIGStephen Warren2012-07-09-0/+1
| | | | | | | | | | | | | | | | | | So that all Tegra boards define environment variables that describe themselves. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Add env vars describing U-Boot target boardStephen Warren2012-07-09-0/+44
| | | | | | | | | | | | | | | | | | | | | | This can be useful for generic scripts. For example, rather than hard- coding a script to ext2load tegra-harmony.dtb, it could load ${soc}-${board}.dtb and hence not need adjustments to run on multiple boards. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: usb: fix wrong error checkLucas Stach2012-07-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | loop_count runs down from 10000, so the correct condition to error out is ==0. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Tom Warren <twarren.nvidia@gmail.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: add ULPI on USB2 funcmux entryLucas Stach2012-07-09-1/+15
| | | | | | | | | | | | | | | | | | | | | | This is needed as a prerequisite for Tegra USB ULPI support within U-Boot. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-11-14 20:41:59 +0000