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* pci: move pcidelay code to new location just before PCI bus scanAnatolij Gustschin2011-10-15-13/+17
| | | | | | | | | | | | | | | | | | | | PCI cards might need some time after reset to respond. On some boards (mpc5200 or mpc8260 based) the PCI bus reset is deasserted at pci_init_board() time, so we currently can not use available "pcidelay" option for waiting before PCI bus scan since this waiting takes place before calling pci_init_board(). By moving the pcidelay code to the new location using of the "pcidelay" option is possible on mpc5200 or mpc8260 based boards, too. Since pci_hose_scan() could be called multiple times, restrict the function to wait only during its first call and to ignore pcidelay for any further call (as pointed out by Matthias). Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* net: axi_ethernet: Add driver to u-bootMichal Simek2011-10-15-0/+667
| | | | | | | | | | Add axi_ethernet driver for little-endian Microblaze. RX/TX BDs and rxframe buffer are shared among all axi_ethernet MACs. Only one MAC can work in one time. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Mike Frysinger <vapier@gentoo.org>
* net: emaclite: Fix coding styleMichal Simek2011-10-15-30/+27
| | | | | | Coding style should follow linux coding style. Signed-off-by: Michal Simek <monstr@monstr.eu>
* net: emaclite: Use PKTSIZE directlyMichal Simek2011-10-15-6/+4
| | | | | | Do not setup additional ENET_MAX_MTU macro. Signed-off-by: Michal Simek <monstr@monstr.eu>
* net: emaclite: Setup RX/TX ping pong for every instanceMichal Simek2011-10-15-55/+68
| | | | | | | Setup RX/TX ping-pong buffer for every emaclite IP separately. The next patch move initialization directly to board code. Signed-off-by: Michal Simek <monstr@monstr.eu>
* Merge branch 'master' of git://git.denx.de/u-boot-fdtWolfgang Denk2011-10-15-11/+21
|\ | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-fdt: powerpc/85xx: use fdt_create_phandle() to create the Fman firmware phandles fdt: update fdt_alloc_phandle to use fdt_get_phandle fdt: check for fdt errors in fdt_create_phandle fdt: Add a do_fixup_by_path_string() function
| * powerpc/85xx: use fdt_create_phandle() to create the Fman firmware phandlesTimur Tabi2011-10-15-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Function fdt_create_phandle() conveniently creates new phandle properties using both "linux,phandle" and "phandle", so it should be used by all code that wants to create a phandle. The Fman firmware code, which embeds an Fman firmware into the device tree, was creating the phandle properties manually. Instead, change it to use fdt_create_phandle(). Signed-off-by: Timur Tabi <timur@freescale.com>
| * fdt: update fdt_alloc_phandle to use fdt_get_phandleTimur Tabi2011-10-15-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree compiler, dtc, can use "phandle" and/or "linux,phandle" properties to specify the phandle for any node. By default, it uses both, but "linux,phandle" is deprecated. One day, we'd like to stop using "linux,phandle", but U-boot needs to support both properties equally first. fdt_alloc_phandle() generates a unique phandle, but it was only checking the "linux,phandle" properties. Instead, we use fdt_get_phandle(), which checks both properties automatically. This ensures that we support dtbs that only use "phandle". The side-effect is that fdt_alloc_phandle() now takes twice as long, since it has to check for two properties instead of one in each node that it searches. Signed-off-by: Timur Tabi <timur@freescale.com>
| * fdt: check for fdt errors in fdt_create_phandleTimur Tabi2011-10-15-3/+10
| | | | | | | | | | | | | | | | | | fdt_create_phandle() was ignoring errors from fdt_set_phandle(). If an error occurs, print an error message and return 0, which is an invalid phandle. We also need to change the return type for fdt_create_phandle() to indicate that it cannot return an error code. Signed-off-by: Timur Tabi <timur@freescale.com>
| * fdt: Add a do_fixup_by_path_string() functionChunhe Lan2011-10-15-0/+7
| | | | | | | | | | | | | | | | The do_fixup_by_path_string() will set the specified node's property to the value contained in "status". It would just be an inline wrapper for do_fixup_by_path() that calls strlen on the argument. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
* | powerpc/85xx: Drop CONFIG_VIDEO on P1_P2_RDB-PC boards to reduce sizeKumar Gala2011-10-13-16/+0
| | | | | | | | | | | | | | | | | | With older compilers (gcc-4.2.x) we run into issues that resulting image is too large. We can save a bunch of space by removing the video support. In general video support on these boards is a nice to have since it requires a PCIe add-on card. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | phylib: wait for TN2020 to achieve SERDES lane alignment at startupTimur Tabi2011-10-13-0/+33
| | | | | | | | | | | | | | | | | | | | Before the Teranetics TN2020 PHY can be used, the SERDES lanes need to be aligned, so wait for lane alignment before completing the startup sequence. Note that this process can take up to three seconds. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3Timur Tabi2011-10-13-47/+0
| | | | | | | | | | | | | | | | The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8548cds: Add 36-bit supportchenhui zhao2011-10-13-0/+57
| | | | | | | | | | Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8548cds: Code cleanup and refactoringchenhui zhao2011-10-13-97/+75
| | | | | | | | | | | | | | | | | | | | | | | | - Rework tlb and law tables. - PCI2 is not available on MPC8548CDS, so remove it. - Move the memory map to the board config file. - Rewrite the board info according to the manual. - Remove unnecessary macros and redefine some macros to align with other boards. - Fix some typos. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/p3041: fixup portal config infoHaiying Wang2011-10-13-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | P3041 has 10 qman portals, we need to configure all of them: * As there are only 4 physical cores sdest can only be 0 to 3 * We assign dqrr & frame data LIODNs for all portals so if they are utilized the proper mapping tables can be setup uniquely (PAMU stashing) * We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN assignments are tuned around an assumption of at most 5 partitions. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/p2041: fixup portal config infoHaiying Wang2011-10-13-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | P2041 has 10 qman portals, we need to configure all of them: * As there are only 4 physical cores sdest can only be 0 to 3 * We assign dqrr & frame data LIODNs for all portals so if they are utilized the proper mapping tables can be setup uniquely (PAMU stashing) * We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN assignments are tuned around an assumption of at most 5 partitions. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/p5020: fixup portal config infoHaiying Wang2011-10-13-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | P5020 has 10 qman portals, we need to configure all of them: * As there are only 2 physical cores sdest can only be 0 or 1 * We assign dqrr & frame data LIODNs for all portals so if they are utilized the proper mapping tables can be setup uniquely (PAMU stashing) * We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN assignments are tuned around an assumption of at most 5 partitions. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Added secure boot option for P2041RDB boardsKuldip Giroh2011-10-13-0/+1
|/ | | | | Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsWolfgang Denk2011-10-12-1/+2804
|\ | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mips: MIPS: Jz4740: Add qi_lb60 board support MIPS: Jz4740: Add NAND driver MIPS: Ingenic XBurst Jz4740 processor support
| * MIPS: Jz4740: Add qi_lb60 board supportXiangfu Liu2011-10-12-1/+460
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the qi_lb60 (a.k.a QI Ben NanoNote) clamshell device from Qi hardware: http://en.qi-hardware.com/wiki/Ben_NanoNote http://en.qi-hardware.com/wiki/Main_Page http://en.wikipedia.org/wiki/Qi_hardware This Jz4740-based clamshell device does not use NOR flash to boot. The initial bring-up assumes that U-Boot is directly loaded into SDRAM using USB boot tool, and starts from 0x80100000. About USB boot tool ------------------- Jz4740 is one of the XBurst processors with USB boot functionality supported. The CPU can boot from a small ROM in the LSI, initialize CPU and USB module, then wait for USB commands from the USB host. We can send 8 KB binary data to the CPU cache using USB boot tool. USB boot tool is available to the public at Ingenic website. Also there is an alternative Debian package named xburst-tools. Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Daniel <zpxu@ingenic.cn> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
| * MIPS: Jz4740: Add NAND driverXiangfu Liu2011-10-12-0/+262
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Jz4740 NAND flash controller can support: * MLC NAND as well as SLC NAND * all 8-bit/16-bit NAND flash devices * HAMMING and RS hardware ECC * automatic boot up from NAND flash devices nand_ecclayout is set up for 2GiB NAND chip mounted in Qi LB60. We'll bring up boot-from-NAND support in nand_spl/ in the future. Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Daniel <zpxu@ingenic.cn> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
| * MIPS: Ingenic XBurst Jz4740 processor supportXiangfu Liu2011-10-10-0/+2082
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Jz4740 is a multimedia application processor targeting for mobile devices like e-Dictionary, eBook, portable media player (PMP) and GPS navigator. Jz4740 is powered by Ingenic 360 MHz XBurst CPU core (JzRISC), in which RISC/SIMD/DSP hybrid instruction set architecture provides high integration, high performance and low power consumption. JzRISC incorporated in Jz4740 is the advanced and power-efficient 32-bit RISC core, compatible with MIPS32, with 16K I-Cache and 16K D-Cache, and can operate at speeds up to 400 MHz. On-chip modules such as LCD controller, embedded audio codec, multi- channel SAR-ADC, AC97/I2S controller and camera I/F offer a rich suite of peripherals for multimedia application. NAND controller (SLC/MLC), USB (host 1.1 and device 2.0), UART, I2C, SPI, etc. are also available. For more info about Ingenic XBurst Jz4740: http://en.ingenic.cn/eng/ http://www.linux-mips.org/wiki/Ingenic This patch introduces XBurst CPU support in U-Boot. It's compatible with MIPS32, but requires a bit different cache maintenance, timer routines, and boot mechanism using USB boot tool, so XBurst support can go into a separate new home, cpu/xburst/. Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Daniel <zpxu@ingenic.cn> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2011-10-12-9/+13
|\ \ | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-ppc4xx: ppc4xx: Change DDR2 CL from 4 to 5 for intip ppc4xx: Improve lm63 pwm on dlvision-10g ppc4xx: Do not stop booting on any keypress on intip
| * | ppc4xx: Change DDR2 CL from 4 to 5 for intipDirk Eibach2011-10-12-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Some intip boards don't seem to run stable with CL4, datasheets suggest that CL5 is the safe value. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Improve lm63 pwm on dlvision-10gDirk Eibach2011-10-12-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Fan PWM lookuptable was modified to start at 46 degrees celsius instead of 40 degrees celsius. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Do not stop booting on any keypress on intipDirk Eibach2011-10-12-2/+6
| |/ | | | | | | | | | | | | | | Use CONFIG_AUTOBOOT_KEYED on intip so that booting can only be stopped with well defined keypresses. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-ubiWolfgang Denk2011-10-12-8/+10
|\ \ | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-ubi: UBI: init eba tables before wl when attaching a device ubifs bad superblock bug
| * | UBI: init eba tables before wl when attaching a deviceHolger Brunck2011-10-12-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes that u-boot gets stuck when a bitflip was detected during "ubi part <ubi_device>". If a bitflip was detected UBI tries to copy the PEB to a different place. This needs that the eba table are initialized, but this was done after the wear levelling worker detects the bitflip. So changes the initialisation of these two tasks in u-boot. This is a u-boot specific patch and not needed in the linux layer, because due to commit 1b1f9a9d00447d UBI: Ensure that "background thread" operations are really executed we schedule these tasks in place and not as in linux after the inital task which schedule this new task is finished. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ubifs bad superblock bugLars Poeschel2011-10-12-2/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes an issue when ubifs reads a bad superblock. Later it tries to free memory, that was not allocated, which freezes u-boot. This is fixed by looking for a non null pointer before free. The message I got before u-boot freezes: UBI: max/mean erase counter: 53/32 UBIFS: mounted UBI device 0, volume 1, name "rootfs" UBIFS: mounted read-only UBIFS: file system size: 49140 bytes (50319360 KiB, 0 MiB, 49140 LEBs) UBIFS: journal size: 49 bytes (6838272 KiB, 0 MiB, 6678 LEBs) UBIFS: media format: w4/r0 (latest is w4/r0) UBIFS: default compressor: LZO UBIFS: reserved for root: 0 bytes (0 KiB) UBIFS error (pid 0): ubifs_read_node: bad node type (255 but expected 9) UBIFS error (pid 0): ubifs_read_node: bad node at LEB 330:13104 UBIFS error (pid 0): ubifs_iget: failed to read inode 1, error -22 Error reading superblock on volume 'ubi:rootfs'! Signed-off-by: Lars Poeschel <larsi@wh2.tu-dresden.de> Cc: Kyungmin Park <kmpark@infradead.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashWolfgang Denk2011-10-12-13/+13
|\ \ | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-nand-flash: NAND: davinci: choose correct 1-bit h/w ECC reg
| * | NAND: davinci: choose correct 1-bit h/w ECC regLaurence Withers2011-10-10-13/+13
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In nand_davinci_readecc(), select the correct NANDF<n>ECC register based on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC. This allows 1-bit hardware ECC to work with chip select other than CS2. Note this now matches the usage in nand_davinci_enable_hwecc(), which already had the correct handling, and allows refactoring to a single function encapsulating the register read. Without this fix, writing NAND pages to a chip not wired to CS2 would result in in the ECC calculation always returning FFFFFF for each 512-byte segment, and reading back a correctly written page (one with ECC intact) would always fail. With this fix, the ECC is written and verified correctly. Signed-off-by: Laurence Withers <lwithers@guralp.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk2011-10-12-17/+48
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-microblaze: microblaze: Copy bootfile from variables microblaze: Fix unaligned.h for endians microblaze: Initialize jumptable and console microblaze: Support flashes on lower addresses microblaze: Call common console_init_f initialization function
| * | microblaze: Copy bootfile from variablesMichal Simek2011-10-10-0/+4
| | | | | | | | | | | | | | | | | | Setup bootfile. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | microblaze: Fix unaligned.h for endiansMichal Simek2011-10-10-16/+1
| | | | | | | | | | | | | | | | | | | | | Also support little endian MB. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Mike Frysinger <vapier@gentoo.org>
| * | microblaze: Initialize jumptable and consoleMichal Simek2011-10-10-0/+6
| | | | | | | | | | | | | | | | | | This changes were done to get support for netconsole. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | microblaze: Support flashes on lower addressesMichal Simek2011-10-10-1/+36
| | | | | | | | | | | | Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | microblaze: Call common console_init_f initialization functionMichal Simek2011-10-10-0/+1
| |/ | | | | | | | | | | Calling console_init_f enables CTRL+C usage. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | powerpc/mpc8536ds: Save the env variables to SDcard and SPI flashXie Xiaobo2011-10-09-4/+18
| | | | | | | | | | | | | | | | | | | | | | MPC8536DS offer booting from SDcard or SPI flash. This patch defined that u-boot can save the environment variables on SDcard or SPI flash when booting from the related device. The Env parameter region and linux kernel region have overlap in SPI-Flash, So change the Env param saving address. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8536ds: Add USB support for MPC8536DSFanzc2011-10-09-0/+15
| | | | | | | | | | | | | | Add EHCI controller and USB command definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl_sata: Fix compile error when CONFIG_LBA48 is not definedTang Yuantian2011-10-09-5/+10
| | | | | | | | | | | | | | | | If CONFIG_LBA48 is not defined, the element lba48 of struct sata_dev_desc is not avaible, and can't be used. Signed-off-by: Tang Yuantian <b29983@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8536ds: Invert SDHC_WP pin polarityXie Xiaobo2011-10-09-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | MPC8536 Rev 1.0 silicon have NMG_eSDHC118 erratum, so that the SDHC write protected pin polarity does not follow the SD card standard in MPC8536 Rev 1.0 silicon. The MPC8536DS board invert the SDHC_WP pin as a workaround. However, this silicon erratum has been fixed in Rev 1.1, So need invert the SDHC_WP polarity again when use the MPC8536 Rev1.1 and greater on MPC8536DS board. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8536ds: Add eSPI support for MPC8536DSXie Xiaobo2011-10-09-4/+21
| | | | | | | | | | | | | | | | | | | | 1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8548cds: Update config filechenhui zhao2011-10-09-18/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | - Increase the size of malloc space. - Enable e1000 network card. - Show pci devices on startup. - Change the location of env address. - Use hwconfig to turn off ECC by default. [Kumar Gala] Fixed white space formating for CONFIG_EXTRA_ENV_SETTINGS Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc86xx: Disable translation for BAT setupBecky Bruce2011-10-09-79/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We really shouldn't be overwriting bat registers with translation enabled, especially when we're executing code using one of them for translating the current instruction stream. Instead, disable address translation while doing the final BAT setup. In order to do this, setup_bats has to move back to asm code, because we require translation to be enabled to have a stack for C code. The yucky thing about that is that the assembler doesn't like ULL so we have to switch to using HIGH/LOW pairs for physical addresses that are > 32 bits in length. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8641hpcn: fix SRIO BAT configBecky Bruce2011-10-09-5/+0
| | | | | | | | | | | | | | | | There were duplicate (and conflicting) defines for the BATs used to cover SRIO. Drop the bogus set. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: fix null pointer dereference when init the SGMII TBI PHYTimur Tabi2011-10-09-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function dtsec_configure_serdes() needs to know where the TBI PHY registers are in order to configure SGMII for proper SerDes operation. During SGMII initialzation, fm_eth_init_mac() passing NULL for 'phyregs' when it called init_dtsec(), because it was believed that phyregs was not used. In fact, it is used by dtsec_configure_serdes() to configure the TBI PHY registers. We also need to define the PHY registers in struct fm_mdio. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8xxx: Merge entries in DDR speed tableYork Sun2011-10-09-460/+472
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not necessary to keep multiple entries for the same setting in DDR speed tables. Merge them for smaller tables. Also restructure the tables for smaller size. Cleanup some typedefs. Enforce strict checking for speed table. If DIMM is running at higher than known speed, try to use the highest speed setting. If rank is unknown, it has to panic. Removed ODT overriding for P2020DS as it is not necessary. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | phylib: Work around bug in Teranetics PHYAndy Fleming2011-10-09-1/+20
| | | | | | | | | | | | | | | | | | | | | | The Teranetics PHY does not properly report the link state for fiber connections. The new PHY code actually checked the link, and so the FM driver would refuse to talk over a linkless PHY. But the link may actually be up, so now we always report it as up for fiber connections on the tn2020. Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/85xx: CONFIG_ENABLE_36BIT_PHYS does not depend on CONFIG_PHYS_64BITTimur Tabi2011-10-09-3/+3
| | | | | | | | | | | | | | | | | | | | The macro CONFIG_ENABLE_36BIT_PHYS is used to indicate that the given SOC is capable of 36-bit physical addresses, even if such large addresses are not used. On two boards, this macro was enabled only when building a 36-bit image. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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