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* sh: ap325rxa: Moved ap325rxa board to board/renesasNobuhiro Iwamatsu2008-10-31-1/+1
| | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Fix to the auto-update feature documentation (CONFIG_UPDATE_TFTP_MSEC_MAX)Bartlomiej Sieka2008-10-31-3/+3
| | | | Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
* 74xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cacheDave Liu2008-10-31-4/+4
| | | | | | | | | | | | | | | | | | The patch is following the commit 392438406041415fe64ab8748ec5ab5ad01d1cf7 mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache This is needed in unlock_ram_in_cache() because it is called from C and will corrupt the small data area anchor that is kept in R2. lock_ram_in_cache() is modified similarly as good coding practice, but is not called from C. Signed-off-by: Nick Spence <nick.spence@freescale.com> also, the r2 is used as global data pointer. Signed-off-by: Dave Liu <daveliu@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2008-10-30-1/+1
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| * mpc83xx pci: Round up memory size in inbound window.Scott Wood2008-10-30-1/+1
| | | | | | | | | | | | | | | | The current calculation will fail to cover all memory if its size is not a power of two. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc86xxWolfgang Denk2008-10-30-72/+4
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| * | 86xx: remove the unused definitionDave Liu2008-10-30-20/+0
| | | | | | | | | | | | Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | 86xx: remove the redundant r2 global data pointer saveDave Liu2008-10-30-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 67256678f00c09b0a7f19e862e5c1847553d31bc add the another global data pointer save, but in fact the global data pointer will be initialized in the board_init_r, so remove it such as the 85xx/83xx family. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Kumar Gala <kumar.gala@freescale.com>
| * | 86xx: remove the unused code for 86xx familyDave Liu2008-10-30-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | I believe these code was copied from 74xx family, but for 86xx, it is unused. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Kumar Gala <kumar.gala@freescale.com>
| * | 86xx: remove the second DDR LAW setting for mpc8641hpcnDave Liu2008-10-30-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | The DDR1 LAW will precedence the DDR2 LAW, so remove the second DDR LAW. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
| * | 86xx: remove the unused ddr_enable_ecc in the board fileDave Liu2008-10-30-33/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR controller of 86xx processors have the ECC data init feature, and the new DDR code is using the feature, we don't need the way with DMA to init memory again. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Kumar Gala <kumar.gala@freescale.com>
| * | 86xx: Move the clear_tlbs before MMU turn onDave Liu2008-10-30-1/+4
| |/ | | | | | | | | | | | | | | | | | | We must invalidate TLBs before MMU turn on, but currently the code is not, if there are some stale TLB entry valid in the TLBs, it will cause strange issue. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
* | mpc8313erdb: Document NAND boot.Scott Wood2008-10-29-4/+32
| | | | | | | | | | | | | | Previously, the documentation claimed that NAND boot is not supported. This is no longer true. Signed-off-by: Scott Wood <scottwood@freescale.com>
* | NAND: Properly create JFFS2 cleanmarkers.Scott Wood2008-10-29-19/+11
| | | | | | | | | | | | | | | | | | | | | | As reported by Ilko Iliev <iliev@ronetix.at>, the "nand erase clean" command is currently broken, and among other things causes all blocks to be marked bad. This implements it properly using MTD_OOB_AUTO, along with some indentation fixes. Signed-off-by: Scott Wood <scottwood@freescale.com>
* | NAND fsl elbc: Set FMR[ECCM] based on page size.Scott Wood2008-10-29-2/+14
| | | | | | | | | | | | | | Hardware expects ECCM 0 for small page and ECCM 1 for large page when booting from NAND, so use those defaults. Signed-off-by: Scott Wood <scottwood@freescale.com>
* | NAND: Add support for MPC8572DS boardHaiying Wang2008-10-29-1/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch defines 1M TLB&LAW size for NAND on MPC8572DS, assigns 0xffa00000 for CONFIG_SYS_NAND_BASE and adds other NAND supports in config file. It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image, to make room for the increased code size with NAND enabled. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Make Freescale local bus registers available for both 83xx and 85xx.Haiying Wang2008-10-29-152/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | - Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it can be shared by both 83xx and 85xx - Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards files which use lbus83xx_t. - Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that 85xx can share them. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | NAND: Align right column of the shorthelp with other commands.Scott Wood2008-10-29-1/+1
| | | | | | | | | | | | | | I accidentally broke this in when making consistent the partial alignment of the longhelp. Signed-off-by: Scott Wood <scottwood@freescale.com>
* | NAND: Reset chip on power-upKarl Beldan2008-10-29-0/+8
| | | | | | | | | | | | | | | | | | | | Some chips require a RESET after power-up (e.g. Micron MT29FxGxxxxx). The first command sent is NAND_CMD_READID. Issue a NAND_CMD_RESET in nand_scan_ident before reading the device id. Tested with an MT29F4G08AAC. Signed-off-by: Karl Beldan <karl.beldan@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | NAND: sync with 2.6.27Scott Wood2008-10-29-60/+188
|/ | | | | | | | | | | | | This brings the core NAND code up to date with the Linux kernel. Since there were several drivers in Linux as of the last update that are not in u-boot, I'm not bringing over new drivers that have been added since in the absence of an interested party. I did not update OneNAND since it was recently synced by Kyungmin Park, and I'm not sure exactly what the common ancestor is. Signed-off-by: Scott Wood <scottwood@freescale.com>
* bootm: Added CONFIG_BOOTM_{LINUX, NETBSD, RTEMS}Kumar Gala2008-10-29-0/+20
| | | | | | Added the ability to config out bootm support for Linux, NetBSD, RTEMS Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* bootm: support subcommands in linux ppc bootmKumar Gala2008-10-29-96/+175
| | | | | | Add support for 'bdt', 'cmdline', 'prep' to the linux PPC bootm. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* bootm: Add subcommandsKumar Gala2008-10-29-2/+219
| | | | | | | | | | | | | | Add the ability to break the steps of the bootm command into several subcommands: start, loados, ramdisk, fdt, bdt, cmdline, prep, go. This allows us to do things like manipulate device trees before they are passed to a booting kernel or setup memory for a secondary core in multicore situations. Not all OS types support all subcommands (currently only start, loados, ramdisk, fdt, and go are supported). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* bootm: Move to using a function pointer table for the boot os functionKumar Gala2008-10-29-37/+31
| | | | | | | | This removes a bit of code and makes it easier for the upcoming sub bootm command support to call into the proper OS specific handler. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-videoWolfgang Denk2008-10-28-85/+195
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| * lcd: Let the board code show board-specific infoHaavard Skinnemoen2008-10-27-79/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | The information displayed when CONFIG_LCD_INFO is set is inherently board-specific, so it should be done by the board code. The current code dealing with this only handles two cases, and is already a horrible mess of #ifdeffery. Yes, this duplicates some code, but it also allows boards to print more board-specific information; this used to be very difficult. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * lcd: Set lcd_is_enabled before clearing the screenHaavard Skinnemoen2008-10-25-1/+1
| | | | | | | | | | | | | | | | This allows the logo/info rendering routines to use the regular lcd_putc/lcd_puts/lcd_printf calls. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * lcd: Implement lcd_printf()Haavard Skinnemoen2008-10-25-0/+14
| | | | | | | | | | | | | | | | | | lcd_printf() has a prototype in include/lcd.h but no implementation. Fix this by borrowing the lcd_printf() implementation from the cogent board code (which appears to use its own LCD framework.) Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * atmel_lcdfb: Straighten out funky vl_sync logicHaavard Skinnemoen2008-10-25-4/+1
| | | | | | | | | | | | | | | | If the board _didn't_ request INVLINE_INVERTED, we set INVLINE_INVERTED, otherwise we don't. WTF? Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * atmel_lcdfb: Eliminate unneeded #include <asm/arch/hardware.h>Haavard Skinnemoen2008-10-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | atmel_lcdfb doesn't actually need anything from asm/arch/hardware.h. It includes a file that does, asm/arch/gpio.h, but this file doesn't include <asm/arch/hardware.h> like it's supposed to. Add the missing include to asm/arch/gpio.h and remove the workaround from the atmel_lcdfb driver. This makes the driver compile on avr32. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | i386: Renamed show_boot_progress in assembler codeGraeme Russ2008-10-28-14/+14
| | | | | | | | | | | | | | Renamed show_boot_progress in assembler init phase to show_boot_progress_asm to avoid link conflicts with C version Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | Merge branch 'denx'Andy Fleming2008-10-27-1/+922
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| * \ Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-10-27-687/+624
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| * | | ppc4xx: New board avnet fx12 minimodulGeorg Schardt2008-10-24-0/+252
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the avnet fx12 minimodul. It needs the "ppc4xx: Generic architecture for xilinx ppc405" patch from Ricardo. Signed-off-by: Georg Schardt <schardt@team-ctech.de> Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Generic architecture for xilinx ppc405(v3)Ricardo Ribalda Delgado2008-10-24-1/+663
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx ppc440 boards, this patch presents a common architecture for all the xilinx ppc405 boards. Any custom xilinx ppc405 board can be added very easily with no code duplicity. This patch also adds a simple generic board, that can be used on almost any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h This patch is prepared to work with the latest version of EDK (10.1) Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Disable DDR2 autocalibration on Kilauea for nowStefan Roese2008-10-24-0/+7
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the new autocalibration still has some problems on some Kilauea boards with 200MHz DDR2 frequency we disable the autocalibration and use the hardcoded values as done before. This seems to work reliably on all known DDR2 frequencies. After the autocalibration issue is fixed we will enable it again. Signed-off-by: Stefan Roese <sr@denx.de>
* | | 85xx: Update MPC85xx_PORDEVSR_IO_SEL maskPeter Tyser2008-10-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8572 has a 4-bit wide PORDEVSR IO_SEL field. Other MPC85xx processors have a 3-bit wide IO_SEL field but have the most significant bit is wired to 0 so this change should not affect them. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | | powerpc: fix pci window initialization to work with > 4GB DRAMBecky Bruce2008-10-27-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The existing code has a few errors that need to be fixed in order to support large RAM sizes. Fix those, and add a comment to make it clearer. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* | | pci/fsl_pci_init: Removed a bunch pointless trailing backslashes.Kumar Gala2008-10-27-7/+7
| |/ |/| | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | 86xx: Convert all fsl_pci_init users to new APIsKumar Gala2008-10-24-142/+59
| | | | | | | | | | | | | | | | | | | | | | | | Converted MPC8610HCPD, MPC8641HPCN, and SBC8641D to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com>
* | 85xx: Convert all fsl_pci_init users to new APIsKumar Gala2008-10-24-445/+200
| | | | | | | | | | | | | | | | | | | | | | | | Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS, MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* | pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-rangesKumar Gala2008-10-24-0/+20
| | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* | pci/fsl_pci_init: Add a common PCI inbound setup functionKumar Gala2008-10-24-0/+81
| | | | | | | | | | | | | | | | Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* | pci/fsl_pci_init: Enable larger address and setting inbound windows properlyKumar Gala2008-10-24-14/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * PCI Inbound window was setup incorrectly. The PCI address and system address were swapped. The PCI address should be setting piwar/piwbear and the system address should be setting pitar. * Removed masking of addresses to allow for system address to support system address & PCI address >32-bits * Set PIWBEAR & POTEAR to allow for full 64-bit PCI addresses * Respect the PCI_REGION_PREFETCH for inbound windows Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* | fdt: Added helper to set PCI dma-ranges propertyKumar Gala2008-10-24-0/+74
| | | | | | | | | | | | | | | | | | | | | | Added fdt_pci_dma_ranges() that parses the pci_region info from the struct pci_controller and populates the dma-ranges based on it. The max # of windws/dma-ranges we support is 3 since on embedded PowerPC based systems this is the max number of windows. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* | fdt: Add fdt_getprop_u32_default helpersKumar Gala2008-10-24-0/+29
| | | | | | | | | | | | | | | | | | Add helper functions to return find a node and return it's property or a default value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
* | 86xx: Enable 64-bit PCI resources on all Freescale boardsKumar Gala2008-10-24-0/+2
| | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* | 85xx: Enable 64-bit PCI resources on all Freescale boardsKumar Gala2008-10-24-0/+9
| | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* | pci: Allow for PCI addresses to be 64-bitKumar Gala2008-10-24-63/+102
| | | | | | | | | | | | | | | | | | | | PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
* | 85xx: Fix the incorrect register used for DDR erratum1Dave Liu2008-10-24-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 8572 DDR erratum1: DDR controller may enter an illegal state when operating in 32-bit bus mode with 4-beat bursts. Description: When operating with a 32-bit bus, it is recommended that DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used. This forces the DDR controller to use 4-beat bursts when communicating to the DRAMs. However, an issue exists that could lead to data corruption when the DDR controller is in 32-bit bus mode while using 4-beat bursts. Projected Impact: If the DDR controller is operating in 32-bit bus mode with 4-beat bursts, then the controller may enter into a bad state. All subsequent reads from memory is corrupted. Four-beat bursts with a 32-bit bus only is used with DDR2 memories. Therefore, this erratum does not affect DDR3 mode. Work Arounds: To work around this issue, software must set DEBUG_1[31] in DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1 and CCSRBAR offset + 0x6f00 for DDR_2). Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2 as condition, but it should be DDR_SDRAM_CFG register. Signed-off-by: Dave Liu <daveliu@freescale.com>
generated by cgit v1.1 at 2024-11-16 23:54:18 +0000