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* 85xx: Get ride of old TLB setup codeKumar Gala2008-01-17-39/+0
| | | | | | | Now that all boards have been converted, remove old config code and the config option for the new style. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert TQM85xx to new TLB setupKumar Gala2008-01-17-182/+116
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert STXGP3 & STXSSA to new TLB setupKumar Gala2008-01-17-418/+240
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert SBC8540/SBC8560/SBC8548 to new TLB setupKumar Gala2008-01-17-321/+178
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert PM854/PM856 to new TLB setupKumar Gala2008-01-17-404/+238
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert MPC8540EVAL to new TLB setupKumar Gala2008-01-17-141/+80
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert MPC8568 MDS to new TLB setupKumar Gala2008-01-17-183/+102
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert MPC8541/MPC8555/MPC8548 CDS to new TLB setupKumar Gala2008-01-17-583/+334
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert MPC8540/MPC8560 ADS to new TLB setupKumar Gala2008-01-17-433/+264
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert ATUM8548 to new TLB setupKumar Gala2008-01-17-180/+92
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert MPC8544 DS to new TLB setupKumar Gala2008-01-17-179/+101
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Reworked initial processor initKumar Gala2008-01-17-72/+115
| | | | | | | | | | | | | | | | | | | Reworked the initial processor initialzation sequence: * introduced cpu_early_init_f that is run in address space 1 (AS=1) * Moved TLB/LAW and CCSR init into cpu_early_init_f() * Reworked initial asm code to do most of the core init before TLBs The main reasons for these changes are to allow handling of 36-bit phys addresses in the future and some of the issues that will exist when we do that. There are a few caveats on what can be initialized via the LAW and TLB static tables: * TLB entry 14/15 can't be initialized via the TLB table * any LAW that covers the implicit boot window (4G-8M to 4G) must map to the code that is currently executing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Introduce new tlb APIKumar Gala2008-01-17-14/+130
| | | | | | | | | | Add a set of functions to manipulate TLB entries: * set_tlb() - write a tlb entry * invalidate_tlb() - invalidate a tlb array * disable_tlb() - disable a variable size tlb entry * init_tlbs() - setup initial tlbs based on static table Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Use proper defines for PCI addressesKumar Gala2008-01-16-77/+77
| | | | | | | | We should be using the _MEM_PHYS for LAW and TLB setup and not _MEM_BASE. While _MEM_BASE & _MEM_PHYS are normally the same, _MEM_BASE should only be used for configuring the PCI ATMU. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Remove old style of LAW initKumar Gala2008-01-16-28/+0
| | | | | | All boards are now using the new fsl_law code so we can drop the old version. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: convert remaining 85xx boards over to use new LAW init codeKumar Gala2008-01-16-210/+242
| | | | | | | Converted ATUM8548, MPC8568 MDS, MPC8540 EVAL, and TQM85xx boards over to use new LAW init code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: convert STXGP3/STXSSA over to use new LAW init codeKumar Gala2008-01-16-109/+122
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: convert PM854/PM856 over to use new LAW init codeKumar Gala2008-01-16-110/+120
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: convert SBC8540/SBC8560/SBC8548 over to use new LAW init codeKumar Gala2008-01-16-97/+122
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: convert MPC8541/MPC8555/MPC8548 CDS over to use new LAW init codeKumar Gala2008-01-16-173/+195
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: convert MPC8540/MPC8560 ADS over to use new LAW init codeKumar Gala2008-01-16-110/+120
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: convert MPC8544 DS over to use new LAW init codeKumar Gala2008-01-16-49/+45
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Move LAW init code into CKumar Gala2008-01-16-0/+169
| | | | | | | | | | | Move the initialization of the LAWs into C code and provide an API to allow modification of LAWs after init. Board code is responsible to provide a law_table and num_law_entries. We should be able to use the same code on 86xx as well. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xxWolfgang Denk2008-01-16-138/+128
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| * FSL: Generalize PIXIS reset command parsing.James Yang2008-01-16-108/+106
| | | | | | | | | | | | | | | | | | Before, the order of arguments to the pixis_reset command needed to be supplied in a hard-coded order. Generalize the command parsing to allow any order. Signed-off-by: James Yang <james.yang@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com>
| * FSL: Convert board/freescale/common/Makefile to use CONFIG_Jon Loeliger2008-01-16-25/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the board/freescale/common/Makefile to use CONFIG_* options to select which files to conditionally compile into the board/freescale/common library rather than conditionally compiling entire files. Now handles:: CONFIG_FSL_PIXIS CONFIG_FSL_DIU_FB CONFIG_PQ_MDS_PIB CONFIG_ID_EEPROM is introduced until CFG_ID_EEPROM is gone. Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * Use CONFIG_ULI526X as MPC8610HPCD default Ethernet driverRoy Zang2008-01-16-5/+2
| | | | | | | | | | | | | | | | Use driver/net/uli526x.c as MPC8610HPCD default Ethernet driver. Remove unused ethernet CONFIG_ options. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com>
* | Add support for the MPC837xERDBKim Phillips2008-01-16-0/+989
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC837xERDB board support includes: * DDR2 330MHz hardcoded (soldered on the board) * Local Bus NOR Flash * I2C, UART and RTC * eTSEC RGMII (TSEC0 - RTL8211B with MII; * TSEC1 - VSC7385 local bus, hardcoded, requires seperate firmware * load) Signed-off-by: Kevin Lam <kevin.lam@freescale.com> Signed-off-by: Joe D'Abbraccio <joe.d'abbraccio@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: add support for more system clock performance controlsKim Phillips2008-01-16-31/+67
| | | | | | | | | | | | | | | | | | | | System registers that are modified are the Arbiter Configuration Register (ACR), the System Priority Control Register (SPCR), and the System Clock Configuration Register (SCCR). Signed-off by: Michael F. Reiss <Michael.F.Reiss@freescale.com> Signed-off by: Joe D'Abbraccio <ljd015@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: fix QE ETHPRIMEs to correct 'FSL UEC0' valueKim Phillips2008-01-16-4/+4
| | | | | | | | | | | | continuation of commit b96c83d4ae475a70ef2635cd0e748174c44c8601 Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: clean up mpc8360emds.c warningsKim Phillips2008-01-16-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | mpc8360emds.c: In function 'ft_board_setup': mpc8360emds.c:327: warning: assignment makes pointer from integer without a cast mpc8360emds.c:329: warning: passing argument 2 of 'fdt_getprop' makes integer from pointer without a cast mpc8360emds.c:334: warning: passing argument 2 of 'fdt_setprop' makes integer from pointer without a cast mpc8360emds.c:341: warning: assignment makes pointer from integer without a cast mpc8360emds.c:343: warning: passing argument 2 of 'fdt_getprop' makes integer from pointer without a cast mpc8360emds.c:348: warning: passing argument 2 of 'fdt_setprop' makes integer from pointer without a cast Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: fix phy-connection-type fixup codeKim Phillips2008-01-16-9/+15
| | | | | | | | | | | | | | | | | | use tree passed to us in local blob, not global fdt. Also use fdt_path_offset to convert to relative offset, since absolute reference is needed to check for rgmii-id mode string value. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: fix mpc8313/mpc8315/mpc8349itx Makefiles for silent build (with -s)Kumar Gala2008-01-16-3/+3
| | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Changes in uboot DDR configuration for MPC8313eRDBPoonam Aggrwal2008-01-16-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These changes were identified by HighSmith Bill ,Mazzyar and Joseph for DDR configuration in u-boot code. Some are related to performance, some affect stability and some correct few basic errors in the current configuration. The changes have been tested and found to give better memory latency figures on MPC8313eRDB.LMBench figures prove it. The changes are: - CS0_CONFIG[ AP_n_EN] is changed from 1 to 0 (this may improve performance for application with many read or write to open pages). - CS0_CONFIG[ODT_WR_CFG] is currently changed from 100 to 001 (activating all the CS when only one is used may cause unwanted noise on the system) - TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 8clks (based on Tras=45ns) - TIMING_CFG_1[REFREC] changed from 21 clks to 18clks. - TIMING_CFG_2[AL] value changed from 0 setting to 1 clk to comply with the 3 ODT clk requirements) - TIMING_CFG_2[CPO] was set to a reserved value, changed to RL+3/4. - TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 6clks. - DDR_SDRAM_MODE[AL]changed from 0 to 1. - DDR_SDRAM_MODE[WRREC] changed from 1 clk to 3 clks. - DDR_SDRAM_INTERVAL[REFINT] is changed from 0x0320 to 0x0510. - DDR_SDRAM_INTERVAL[BSTOPRE] is changed from 0x64 to 0x0500. The patch is based of git://www.denx.de/git/u-boot-mpc83xx.git The last commit on this tree was 6775c68683a53c7abc778774641aac6f833a2cbf Signed-off-by: Poonam Aggrwal-b10812 <b10812@freescale.com> Cc: Bill HighSmith <Bill.Highsmith@freescale.com> Cc: Razzaz Mazyar <MRazzaz@freescale.com> Cc: Josep P J <PJ.Joseph@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Enable the isdram command on the MPC8360EMDS boardJerry Van Baren2008-01-16-0/+1
| | | | | | | | | | | | | | | | | | The isdram command prints out decoded information the "serial presence detect" (SPD) chip on the SDRAM SIMMs. This can be very helpful when debugging memory configuration problems. Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: Add the support for MPC8315ERDB boardDave Liu2008-01-16-1/+936
| | | | | | | | | | | | | | | | | | | | | | | | | | The features list: - Boot from NOR Flash - DDR2 266MHz hardcoded configuration - Local bus NOR Flash R/W operation - I2C, UART, MII and RTC - eTSEC0/1 support - PCI host Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: Add config of eTSEC emergency priority in SPCRDave Liu2008-01-16-0/+5
| | | | | | | | | | | | | | | | | | | | | | The TSEC emergency priority definition of 831x/837x is different than the definition of 834x in SPCR register. Add the other config of TSEC emergency priority into cpu_init.c Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: Remove cache config from MPC8360ERDK.hDave Liu2008-01-16-9/+0
|/ | | | | | | | | | | The MPC8360ERDK board support patch is added before the commit 2c5b48fc205c3e2752910da8f39209ed075929e5 so, miss clean up it. The patch clean up the miss cache config. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* nand: FSL UPM NAND driverAnton Vorontsov2008-01-16-0/+242
| | | | Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* OneNAND: Separate U-Boot dependent code from OneNANDKyungmin Park2008-01-16-21/+42
| | | | | | OneNAND: Separate U-Boot dependent code from OneNAND Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* LWMON5: enable hush shell as command line parserWolfgang Denk2008-01-16-0/+6
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* ADS5121: disable watchdog; enable image timestampsWolfgang Denk2008-01-15-6/+6
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* TK885D: fixes for bigger flash sector sizes on new modules;Wolfgang Denk2008-01-15-2/+7
| | | | | | | adjust default environment; disable SCC ethernet (not used on this board). Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xxWolfgang Denk2008-01-14-110/+8210
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| * ppc4xx: Update Kilauea CPLD configuration with USB PHY reset bitStefan Roese2008-01-14-7/+7
| | | | | | | | | | | | | | | | | | Now that bit 29 is the USB PHY reset bit, update the Kilauea port to remove the USB PHY reset after powerup. The CPLD will keep the USB PHY in reset (active low) until the bit is set to 1 in board_early_init_f(). Signed-off-by: Stefan Roese <sr@denx.de>
| * ARM: update mach-types.h from 2.6.24-rc7 Linux kernel treeWolfgang Denk2008-01-13-65/+8144
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * ADS5121: Fix typo in ads5121.c, adjust default environmentWolfgang Denk2008-01-13-30/+35
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * ADS5121: MAX slew rate for PATA pinsJohn Rigby2008-01-13-0/+17
| | | | | | | | Signed-off-by: John Rigby <jrigby@freescale.com>
| * Fix Makefile dependency problem with parallel builds.Wolfgang Denk2008-01-13-7/+6
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * MPC8544DS: fix board Makefile for silent build (with -s)Wolfgang Denk2008-01-13-1/+1
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
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