| Commit message (Collapse) | Author | Age | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
1. This patch is used to switch back to use DCD for flash header
instead of plug-in. This change request is due to the following
reasons:
1) U-boot community doesn't accept current plug-in solution when
upstreaming.
2) Plug-in isn't supported by MX53 ROM serial download mode.
No effective workaround is found now. To use the same code
base to support normal U-Boot and MFG tool better, adopt
DCD solution firstly.
3) Current MX53 DDR scripts don't exceed the length limitation
of DCD.
For MX53 TO2.0 EVK/ARM2 board, raise DDR frequency to 400MHZ after
VCC and VDDA voltages are raised as 1.3V.
Since ARM2 CPU2 board share the same script with EVK, delete ARM2
CPU2 config files. ARM2 CPU2 board can share the same bootloader
with EVK.
2. Update MX53 DDR2 scripts for TO1.0/TO2.0 EVK/ARD/ARM2 boards
The script "MX53_TO2_DDR2_EVK_ARD.inc" is located under
http://compass.freescale.net/livelink/livelink?
func=ll&objId=221058910&objAction=browse&viewType=1
This script is published by ATX and FIL team on Dec 16th, 2010
3. Update MX53 ARM2 CPU3 DDR3 script "MX53_TO2_DDR3_CPU3.inc"
under the same compass folder
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
|
|
|
|
|
|
|
|
| |
BBT table can't be found on MX53 board, which is due to
that the BBT table flag has been written to the ECC area
which cause the BBT flag lost.
This patch also fix the BBT version not correct issue.
Signed-off-by: Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
| |
Correct the GPL license
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
|
|
|
|
|
|
|
| |
Change the ramdisk load address to loadaddr + 0x400000.
Add gpu_memory= kernel parameter.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
|
|
|
|
|
|
|
|
| |
1) Turn on ZQ calib config by default in uboot.
2) Remove one problematic statement which can cause hang issue
3) Change comment style from ; to //
Signed-off-by: Robby Cai <R63905@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
| |
1) IOMUX/backlight support for CLAA WVGA LCD panel.
2) Add video mode for CLAA WVGA LCD panel.
3) Support IPU di1 interface for framebuffer.
4) Enhance IPU driver.
5) Add freescale 600x400 8BPP BMP logo.
Signed-off-by: Terry Lv <R65388@freescale.com>
Signed-off-by: Liu Ying <b17645@freescale.com>
|
|
|
|
|
|
|
| |
uart outputs messy code when kernel starts on mx51.
Change uart clock to use pll2 as source clock.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
|
|
|
| |
1. As we can check DDR dynamically,
remove CONFIG_EMMC_DDR_MODE in mmc.c.
2. Add config CONFIG_EMMC_DDR_PORT_DETECT
config for some boards that only some board support DDR.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add framebuffer driver for the MX51 processor
working on the IPUv3 internal graphic processor.
The port is based on the driver found in the kernel
delivered by Freescale as part of i.MX BSP:
[kernel 2.6.31 commit cc4fe714041805997b601fe8e5dd585d8a99297f]
[agust@denx.de: some style fixes and dead code removal]
Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
(cherry picked from commit 5dda7945d18077db81eb0cfdc2f9d4525e6b77b1)
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The patch is a porting of the IPU Linux driver
developed by Freescale to have framebuffer
functionalities in u-boot. The port is based on
kernel 2.6.31 commit cc4fe714041805997b601fe8e5dd585d8a99297f,
as delivered by Freescale [i.MX BSP].
Most features are dropped from the original driver and
only LCD support is the goal of this porting.
Signed-off-by: Stefano Babic <sbabic@denx.de>
(cherry picked from commit 575001e40c9d10e63f2924649098e7c07d3985c7)
|
|
|
|
|
|
|
| |
[port of linux 2.6.34 commit 6a9ee8af344e3bd7dbd61e67037096cdf7f83289]
Signed-off-by: Stefano Babic <sbabic@denx.de>
(cherry picked from commit bf90ecd3c366177c55012e68d15b8aeb2c41e907)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
All type of DDRs will be affected.
ddr script is available here:
http://compass.freescale.net/livelink/livelink/open/218722501
Two key points:
1. LPDDR2 ZQ calibration is different from mDDR/DDR2,
fixed in this version(they're same before).
2. TO1.1 ZQ calibration is _NOT_ compatible with TO1.0.
U-Boot default config is for TO1.1.
Please switch off CONFIG_ZQ_CALIB option if compile for TO1.0.
Other fixes:
1. Change drive strength to 0x00200000 for all ddr types.
2. Add missed config for IOMUXC_SW_PAD_CTL_PAD_DRAM_OPEN and
IOMUXC_SW_PAD_CTL_PAD_DRAM_OPENFB.
Signed-off-by: Robby Cai <R63905@freescale.com>
|
|
|
|
|
|
|
|
|
| |
Updated DDR2 script for ARD board from Mike Kjar:
"mx53_init_TO2_DDR2_ARD_test.inc".
Tested on TO1 and TO2 ARD.
Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
|
|
|
|
|
|
|
|
| |
script v2:
http://compass.freescale.net/livelink/livelink/219931536/
Codex_DDR2_266MHz.inc.txt?func=doc.Fetch&nodeid=219931536
Signed-off-by: Robby Cai <R63905@freescale.com>
|
|
|
|
|
|
| |
Some configs for mx50 rdp is missed at mfg-tool firmware config file
Signed-off-by: Peter Chen <peter.chen@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Now, uboot cmd_nand of mainline does not support 64-bit
address space, which means that currently nand command
can't access more than 4GB NAND address even when working on
more than 4GB NAND. For example,
MX51 U-Boot > nand read ${loadaddr} 100100000 1000
NAND read: device 0 offset 0x100000, size 0x1000
4096 bytes read: OK
The reason for not support 64-bit address space of nand cmd
is that it use ulong type for addr in file common/cmd_nand.c,
but which is 32-bit width on arm gcc tool chain.
So, it will stuck in infinite loop when working with 4GB NAND
using nand bad command when off overflow.
ulong off; //off - 32bit, typeof(nand->size) is ull;
for (off = 0; off < nand->size; off += nand->erasesize) {
...
}
Simply break the for loop when off overflow is temp fix.
Signed-off-by: Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
| |
Need use CONFIG_SYS_NAND_MAX_CHIPS instead of
NAND_MAX_CHIPS
Signed-off-by: Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
|
| |
When the NAND has multi-cs, the chip select other than
cs0 is not handled correctly which will lead to NAND not
function as expected
Signed-off-by: Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
|
| |
This patch adds support for NANDs greater than 2 GB.
Patch is based on the MTD NAND driver in the kernel.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
|
|
|
|
|
| |
Merge mx50_arm2 to mx50_rdp.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
|
| |
MX50 Add ZQ calibration support for TO1.1.1.
This need to be enabled by CONFIG_ZQ_CALIB.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
|
|
|
|
| |
Total 5 registers:
0x1400023c/244/24c/254/25c: from 0x000a1401 to 0x000a0b01
Without this patch, kernel on RDP board with Elpida DDR
is not able to boot, or not stable.
Signed-off-by: Robby Cai <R63905@freescale.com>
|
|
|
|
|
|
|
| |
Precoding: Update DDR configuration plugin to check SI Rev
and change ROM addresses as needed.
Signed-off-by: Anish Trivedi <anish@freescale.com>
|
|
|
|
|
|
|
|
|
|
| |
On MX50 TO 1.0, DLL did not work in slave mode, so
slave override mode was used instead. Removed this
workaround, except for TO 1.0. Starting with TO 1.1,
the DLL in slave mode is working as expected.
Signed-off-by: Anish Trivedi <anish@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
| |
Add fastboot support for mx53 EVK android.
Signed-off-by: Sammy He <r62914@freescale.com>
|
|
|
|
|
|
| |
Update fastboot usb init seq, and use defined macro for coding.
Signed-off-by: Sammy He <r62914@freescale.com>
|
|
|
|
|
|
| |
Add nand support for mx50 rdp.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add fastboot driver support for android. In this commit,
basic fastboot command is supported.
1) Reboot board
>fastboot reboot
2) Get information of board, e.g, product name
>fastboot getvar product
3) Download images in PC and flash to SD card
>fastboot flash bootloader u-boot-no-padding.bin
>fastboot flash kernel uImage
>fastboot flash uramdisk uramdisk.img
>fastboot flash system system.img
>fastboot flash recovery recovery.img
Certainly, SD card must have been formatted as Android user
guider doc already.
Signed-off-by: Sammy He <r62914@freescale.com>
|
|
|
|
|
|
|
| |
Add imx_udc for usb gadget on i.mx51 platform.
Signed-off-by: Hu Hui <b29976@freescale.com>
Signed-off-by: Sammy He <r62914@freescale.com>
|
|
|
|
|
|
|
|
| |
This patch is to set MC13892 charge regulator output voltage
as 4.2V. It fixes a typo error for chip check and makes TO3
VCC and VDDA voltages keep sync with the spec.
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
|
|
|
|
|
|
|
|
| |
Remove the 2G limitation from NAND driver since currently kernel
can support more than 2GB NAND flash now. This commit will make
NAND driver rescan the whole NAND to create one BBT and store to
the last 4 blocks of the larger than 2GB NAND flash. This commit
will have no effect on the NAND which size is not larger than 2GB.
Signed-off-by: Jason Liu <r64343@freescale.com>
|
|
|
|
|
|
|
| |
cmd_fastboot.c and fastboot.h cannot pass review-commits, this patch
only change code style to fix the errors, but not fixed all warnings.
Signed-off-by: Sammy He <r62914@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
| |
The code realized common Android USB fastboot protocol.
The snapshot can be found of the link:
http://dev.omapzoom.org/?p=bootloader/u-boot.git;a=commit;
h=9c7c5d8ea2326bf8d2d0bfbe670455fb497eb053
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Signed-off-by: Moiz Sonasath <m-sonasath@ti.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Support new DDR script entitled
"Rita_TO2_init_DDR2_CPU2_CMOS_TEST_CAL_v1.inc" for DDR2
boards including MX53 EVK, ARD, and ARM2 CPU2. These new settings
did not apply to TO1. Therefore, changed the DCD
for these boards to a plugin so that TO1 and TO2 can both
be supported using conditional execution of new DDR settings.
During bootup on TO2, DDR frequency is required to be below
400 MHz. Therefore, BOOT_CFG2[4] must be set to enable DDR at
333 MHz in ROM on all boards. Uboot determines silicon version
and for TO2 boosts the VCC and VDDA voltages to 1.3V, after
which the DDR frequency is also increased to 400 MHz.
This requirement meant that uboot does not calibrate PLL2
anymore until the voltage is increased. Removed the calibration
from lowlevel_init.S and from all mx53 include/configs files.
Also required that during config_periph_clk(), only CBCMR register
is touched to set source PLL. Other changes to CBCDR were removed.
Switching to PLL2 bypass clk during reprogram was also removed.
All these changes are required to increase DDR frequency to 400 MHz.
DDR2 CPU2 board with TO1 requires the following hw cfgs:
JP3 populated, and J8 set to 2-3.
For DDR2 CPU2 board with TO2, both these jumpers should be
depopulated.
ARM2 CPU3 (with DDR3) DDR configurations were not changed.
TO1 and TO2 can run well using existing DDR3 script. However,
DCD was converted to plugin to align with other boards.
Signed-off-by: Anish Trivedi <anish@freescale.com>
|
|
|
|
|
|
|
| |
mfgtools and sb_loader can download plug-in and run plug-in
to initilize DRAM.
Signed-off-by: Frank Li <frank.li@freescale.com>
|
|
|
|
|
|
|
| |
Support nand basic read/write in MX28 u-boot.
Signed-off-by: Frank Li <frank.li@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
| |
Add MT29F16G08ABACA NAND description
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
|
|
|
|
|
| |
It should add stop usb operation for mx50 rdp,
otherwise, the usb enumeration at kernel will be very slow
Signed-off-by: Peter Chen <peter.chen@freescale.com>
|
|
|
|
|
|
| |
Add mx50 rdp board mfg-tool firmware configration
Signed-off-by: Peter Chen <peter.chen@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
MT29F16G08MAA NAND flash was failed on MX53 ARD/RevB
board, but it's fine in RevA board. After check, it's
found that udelay is not accurate on MX53 ARD/RevB
board because GPT uses IPG peripheral clock and assume it
is 50MHZ. However IPG peripheral clock is not 50MHZ in
MX53 ARD/RevB board. So it causes udelay is not accurate.
This patch changes GPT clk source as 32K to make udelay
accurate.
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
|
|
|
|
|
|
| |
This patch is used to fix the issue caused by ENGR00132709.
NFC_CLK definition should be used in cmd_clk interface.
MXC_NFC_CLK should be used as internal clock name.
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
|
|
|
|
|
| |
Remove REG_NFC_ONE_CYCLE calling from mxc_nand
driver.
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
|
|
|
|
|
|
| |
Add "clk nfc" command support.
Limit NFC MAX clock as 34MHZ to be compatible with
some old NAND flashes.
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add NAND support for MX53 EVK and ARD.
Need to use kobs-ng to flash U-Boot on MX53 TO1. Because
MX51 TO1 ROM doesn't support bi swap solution and kernel
enable bi swap, Must enable "ignore bad block" option when
flashing U-Boot. The step is as following:
echo 1 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad
kobs-ng init --chip_0_device_path=/dev/mtd2 u-boot.bin
echo 0 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad
Since default configuration stores environment into SD
card and U-Boot uses get_mmc_env_devno (Read SBMR register)
to get MMC/SD slot information, you must insert SD card to
bottom SD slot to get/store environment if you are using NAND
boot on MX53 EVK.
You must config boot dip setting well when doing NAND boot.
For example, if you are using NAND 29F32G080AA NAND chip on
MX53 EVK, you can set boot dips as the following for NAND
boot: SW3: dip 7, 8 on; SW2: dip 3,5 on; SW1: dip 4,7,8 on.
Other dips are off.
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
|
|
|
|
|
| |
Add default uboot defconfig for MX53 ARD MFG
tool
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
|
|
|
|
|
| |
Use serial_mxc as uart driver for MX53 MFG.
This change is required by ENGR00131779.
Signed-off-by: Lily Zhang <r58066@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Update uboot LPDDR2 init code with the following changes
from latest script (v04) from Marek Xu:
http://compass.freescale.net/doc/220496654/Codex_LPDDR2_266MHz.inc.txt
1. Driver strength changed to 0x00180000 from 0x00200000
2. Memory type value changed to 0x04000000 from 0x02000000
3. New ZQ calibration entries with delay between load PU/PD and clear
4. Register at memory location 0x14000024 changed to 0x0048D005
from 0x0048EB05
Signed-off-by: Anish Trivedi <anish@freescale.com>
|
|
|
|
|
|
| |
nand read and write page may fail in some pages.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This change make a bootable default setting of MX53 EVK and MX51 BBG board,
the old default setting is too old to boot android system up.
Also add the recovery command in the env strings, if you want
to boot to recovery mode with mx53_evk, you can just :
> run bootcmd_android_recovery
This command will boot android into recovery mode.
Also fix MX51 can't see UI in recovery mode.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
|
|
|
|
|
|
| |
using ext4 as default recovery filesystem.
Signed-off-by: Terry Lv <r65388@freescale.com>
|