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-rw-r--r--post/board/lwmon5/Makefile28
-rw-r--r--post/board/lwmon5/dsp.c57
-rw-r--r--post/board/lwmon5/dspic.c110
-rw-r--r--post/board/lwmon5/fpga.c97
-rw-r--r--post/board/lwmon5/gdc.c99
-rw-r--r--post/board/lwmon5/sysmon.c259
-rw-r--r--post/board/lwmon5/watchdog.c136
-rw-r--r--post/cpu/ppc4xx/cache.c2
-rw-r--r--post/drivers/rtc.c15
-rw-r--r--post/post.c18
-rw-r--r--post/tests.c28
11 files changed, 843 insertions, 6 deletions
diff --git a/post/board/lwmon5/Makefile b/post/board/lwmon5/Makefile
new file mode 100644
index 0000000..5a92d1c
--- /dev/null
+++ b/post/board/lwmon5/Makefile
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
+#
+# Developed for DENX Software Engineering GmbH
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+LIB = libpostlwmon5.a
+
+COBJS = sysmon.o watchdog.o dspic.o fpga.o dsp.o gdc.o
+
+include $(TOPDIR)/post/rules.mk
diff --git a/post/board/lwmon5/dsp.c b/post/board/lwmon5/dsp.c
new file mode 100644
index 0000000..1946f09
--- /dev/null
+++ b/post/board/lwmon5/dsp.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
+ *
+ * Developed for DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+
+#if CONFIG_POST & CFG_POST_DSP
+#include <asm/io.h>
+
+/* This test verifies DSP status bits in FPGA */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DSP_STATUS_REG 0xC4000008
+
+int dsp_post_test(int flags)
+{
+ uint read_value;
+ int ret;
+
+ ret = 0;
+ read_value = in_be32((void *)DSP_STATUS_REG) & 0x3;
+ if (read_value != 0x3) {
+ post_log("\nDSP status read %08X\n", read_value);
+ ret = 1;
+ }
+
+ return ret;
+}
+
+#endif /* CONFIG_POST & CFG_POST_DSP */
+#endif /* CONFIG_POST */
diff --git a/post/board/lwmon5/dspic.c b/post/board/lwmon5/dspic.c
new file mode 100644
index 0000000..fcbbc60
--- /dev/null
+++ b/post/board/lwmon5/dspic.c
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
+ *
+ * Developed for DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_POST
+
+/* There are two tests for dsPIC currently implemented:
+ * 1. dsPIC ready test. Done in board_early_init_f(). Only result verified here.
+ * 2. dsPIC POST result test. This test gets dsPIC POST codes and version.
+ */
+
+#include <post.h>
+
+#include <i2c.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DSPIC_POST_ERROR_REG 0x800
+#define DSPIC_SYS_ERROR_REG 0x802
+#define DSPIC_VERSION_REG 0x804
+
+#if CONFIG_POST & CFG_POST_BSPEC1
+
+/* Verify that dsPIC ready test done early at hw init passed ok */
+int dspic_init_post_test(int flags)
+{
+ if (in_be32((void *)CFG_DSPIC_TEST_ADDR) & CFG_DSPIC_TEST_MASK) {
+ post_log("dsPIC init test failed\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+#endif /* CONFIG_POST & CFG_POST_BSPEC1 */
+
+#if CONFIG_POST & CFG_POST_BSPEC2
+/* Read a register from the dsPIC. */
+int dspic_read(ushort reg, ushort *data)
+{
+ uchar buf[sizeof(*data)];
+ int rval;
+
+ rval = i2c_read(CFG_I2C_DSPIC_IO_ADDR, reg, sizeof(reg),
+ buf, sizeof(*data));
+
+ *data = (buf[0] << 8) | buf[1];
+
+ return rval;
+}
+
+/* Verify error codes regs, display version */
+int dspic_post_test(int flags)
+{
+ ushort data;
+ int ret = 0;
+
+ post_log("\n");
+ if (dspic_read(DSPIC_VERSION_REG, &data)) {
+ post_log("dsPIC : failed read version\n");
+ ret = 1;
+ } else {
+ post_log("dsPIC version: %u.%u\n",
+ (data >> 8) & 0xFF, data & 0xFF);
+ }
+
+ if (dspic_read(DSPIC_POST_ERROR_REG, &data)) {
+ post_log("dsPIC : failed read POST code\n");
+ } else {
+ post_log("dsPIC POST code 0x%04X\n", data);
+ }
+ if (data != 0)
+ ret = 1;
+
+ if (dspic_read(DSPIC_SYS_ERROR_REG, &data)) {
+ post_log("dsPIC : failed read system error\n");
+ ret = 1;
+ } else if (data != 0) {
+ post_log("dsPIC SYS-ERROR code: 0x%04X\n", data);
+ ret = 1;
+ }
+
+ return ret;
+}
+
+#endif /* CONFIG_POST & CFG_POST_BSPEC2 */
+#endif /* CONFIG_POST */
diff --git a/post/board/lwmon5/fpga.c b/post/board/lwmon5/fpga.c
new file mode 100644
index 0000000..2d95b5e
--- /dev/null
+++ b/post/board/lwmon5/fpga.c
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
+ *
+ * Developed for DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CONFIG_POST
+
+/* This test performs testing of FPGA SCRATCH register,
+ * gets FPGA version and run get_ram_size() on FPGA memory
+ */
+
+#include <post.h>
+
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FPGA_SCRATCH_REG 0xC4000050
+#define FPGA_VERSION_REG 0xC4000040
+#define FPGA_RAM_START 0xC4200000
+#define FPGA_RAM_END 0xC4203FFF
+#define FPGA_STAT 0xC400000C
+
+#if CONFIG_POST & CFG_POST_BSPEC3
+
+static int one_scratch_test(uint value)
+{
+ uint read_value;
+ int ret = 0;
+
+ out_be32((void *)FPGA_SCRATCH_REG, value);
+ /* read other location (protect against data lines capacity) */
+ ret = in_be16((void *)FPGA_VERSION_REG);
+ /* verify test pattern */
+ read_value = in_be32((void *)FPGA_SCRATCH_REG);
+ if (read_value != value) {
+ post_log("FPGA SCRATCH test failed write %08X, read %08X\n",
+ value, read_value);
+ ret = 1;
+ }
+
+ return ret;
+}
+
+/* Verify FPGA, get version & memory size */
+int fpga_post_test(int flags)
+{
+ uint old_value;
+ ushort version;
+ uint read_value;
+ int ret = 0;
+
+ post_log("\n");
+ old_value = in_be32((void *)FPGA_SCRATCH_REG);
+
+ if (one_scratch_test(0x55555555))
+ ret = 1;
+ if (one_scratch_test(0xAAAAAAAA))
+ ret = 1;
+
+ out_be32((void *)FPGA_SCRATCH_REG, old_value);
+
+ version = in_be16((void *)FPGA_VERSION_REG);
+ post_log("FPGA : version %u.%u\n",
+ (version >> 8) & 0xFF, version & 0xFF);
+
+ /* Enable write to FPGA RAM */
+ out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
+
+ read_value = get_ram_size((void *)CFG_FPGA_BASE_1, 0x4000);
+ post_log("FPGA RAM size: %d bytes\n", read_value);
+
+ return ret;
+}
+
+#endif /* CONFIG_POST & CFG_POST_BSPEC3 */
+#endif /* CONFIG_POST */
diff --git a/post/board/lwmon5/gdc.c b/post/board/lwmon5/gdc.c
new file mode 100644
index 0000000..4af6a7a
--- /dev/null
+++ b/post/board/lwmon5/gdc.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
+ *
+ * Developed for DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CONFIG_POST
+
+/* This test attempts to verify board GDC. A scratch register tested, then
+ * simple memory test (get_ram_size()) run over GDC memory.
+ */
+
+#include <post.h>
+
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GDC_SCRATCH_REG 0xC1FF8044
+#define GDC_VERSION_REG 0xC1FF8084
+#define GDC_RAM_START 0xC0000000
+#define GDC_RAM_END 0xC2000000
+
+#if CONFIG_POST & CFG_POST_BSPEC4
+
+static int gdc_test_reg_one(uint value)
+{
+ int ret;
+ uint read_value;
+
+ /* write test pattern */
+ out_be32((void *)GDC_SCRATCH_REG, value);
+ /* read other location (protect against data lines capacity) */
+ ret = in_be32((void *)GDC_RAM_START);
+ /* verify test pattern */
+ read_value = in_be32((void *)GDC_SCRATCH_REG);
+ if (read_value != value) {
+ post_log("GDC SCRATCH test failed write %08X, read %08X\n",
+ value, read_value);
+ }
+
+ return (read_value != value);
+}
+
+/* Verify GDC, get memory size */
+int gdc_post_test(int flags)
+{
+ uint old_value;
+ int ret = 0;
+
+ post_log("\n");
+ old_value = in_be32((void *)GDC_SCRATCH_REG);
+
+ /*
+ * GPIOC2 register behaviour: the LIME graphics processor has a
+ * maximum of 5 GPIO ports that can be used in this hardware
+ * configuration. Thus only the bits for these 5 GPIOs can be
+ * activated in the GPIOC2 register. All other bits will always be
+ * read as zero.
+ */
+ if (gdc_test_reg_one(0x00150015))
+ ret = 1;
+ if (gdc_test_reg_one(0x000A000A))
+ ret = 1;
+
+ out_be32((void *)GDC_SCRATCH_REG, old_value);
+
+ old_value = in_be32((void *)GDC_VERSION_REG);
+ post_log("GDC chip version %u.%u, year %04X\n",
+ (old_value >> 8) & 0xFF, old_value & 0xFF,
+ (old_value >> 16) & 0xFFFF);
+
+ old_value = get_ram_size((void *)GDC_RAM_START,
+ GDC_RAM_END - GDC_RAM_START);
+ post_log("GDC RAM size: %d bytes\n", old_value);
+
+ return ret;
+}
+#endif /* CONFIG_POST & CFG_POST_BSPEC4 */
+#endif /* CONFIG_POST */
diff --git a/post/board/lwmon5/sysmon.c b/post/board/lwmon5/sysmon.c
new file mode 100644
index 0000000..0cf1cf2
--- /dev/null
+++ b/post/board/lwmon5/sysmon.c
@@ -0,0 +1,259 @@
+/*
+ * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
+ *
+ * Developed for DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <post.h>
+#include <common.h>
+
+#ifdef CONFIG_POST
+
+/*
+ * SYSMON test
+ *
+ * This test performs the system hardware monitoring.
+ * The test passes when all the following voltages and temperatures
+ * are within allowed ranges:
+ *
+ * Temperature -40 .. +85 C
+ * +5V +4.75 .. +5.25 V
+ * +5V standby +4.75 .. +5.25 V
+ *
+ * LCD backlight is not enabled if temperature values are not within
+ * allowed ranges (-30 .. + 80). The brightness of backlite can be
+ * controlled by setting "brightness" enviroment variable. Default value is 50%
+ *
+ * See the list of all parameters in the sysmon_table below
+ */
+
+#include <post.h>
+#include <watchdog.h>
+#include <i2c.h>
+
+#if defined(CONFIG_VIDEO)
+#include <mb862xx.h>
+#endif
+
+#if CONFIG_POST & CFG_POST_SYSMON
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* from dspic.c */
+extern int dspic_read(ushort reg, ushort *data);
+
+#define RELOC(x) if (x != NULL) x = (void *) ((ulong) (x) + gd->reloc_off)
+
+typedef struct sysmon_s sysmon_t;
+typedef struct sysmon_table_s sysmon_table_t;
+
+static void sysmon_dspic_init (sysmon_t * this);
+static int sysmon_dspic_read (sysmon_t * this, uint addr);
+static int sysmon_dspic_read_sgn (sysmon_t * this, uint addr);
+static void sysmon_backlight_disable (sysmon_table_t * this);
+
+struct sysmon_s
+{
+ uchar chip;
+ void (*init)(sysmon_t *);
+ int (*read)(sysmon_t *, uint);
+};
+
+static sysmon_t sysmon_dspic =
+ {CFG_I2C_DSPIC_IO_ADDR, sysmon_dspic_init, sysmon_dspic_read};
+
+static sysmon_t sysmon_dspic_sgn =
+ {CFG_I2C_DSPIC_IO_ADDR, sysmon_dspic_init, sysmon_dspic_read_sgn};
+
+static sysmon_t * sysmon_list[] =
+{
+ &sysmon_dspic,
+ &sysmon_dspic_sgn,
+ NULL
+};
+
+struct sysmon_table_s
+{
+ char * name;
+ char * unit_name;
+ sysmon_t * sysmon;
+ void (*exec_before)(sysmon_table_t *);
+ void (*exec_after)(sysmon_table_t *);
+
+ int unit_precision;
+ int unit_div;
+ int unit_min;
+ int unit_max;
+ uint val_mask;
+ uint val_min;
+ uint val_max;
+ int val_valid;
+ uint val_min_alt;
+ uint val_max_alt;
+ int val_valid_alt;
+ uint addr;
+};
+
+static sysmon_table_t sysmon_table[] =
+{
+ {"Temperature", " C", &sysmon_dspic_sgn, NULL, sysmon_backlight_disable,
+ 1, 1, -32768, 32767, 0xFFFF, 0x8000-40, 0x8000+85, 0,
+ 0x8000-30, 0x8000+80, 0, 0x12BC},
+
+ {"+ 5 V", "V", &sysmon_dspic, NULL, NULL,
+ 100, 1000, 0, 0xFFFF, 0xFFFF, 4750, 5250, 0,
+ 4750, 5250, 0, 0x12CA},
+
+ {"+ 5 V standby", "V", &sysmon_dspic, NULL, NULL,
+ 100, 1000, 0, 0xFFFF, 0xFFFF, 4750, 5250, 0,
+ 4750, 5250, 0, 0x12C6},
+};
+static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]);
+
+int sysmon_init_f (void)
+{
+ sysmon_t ** l;
+
+ for (l = sysmon_list; *l; l++)
+ (*l)->init(*l);
+
+ return 0;
+}
+
+void sysmon_reloc (void)
+{
+ sysmon_t ** l;
+ sysmon_table_t * t;
+
+ for (l = sysmon_list; *l; l++) {
+ RELOC(*l);
+ RELOC((*l)->init);
+ RELOC((*l)->read);
+ }
+
+ for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) {
+ RELOC(t->exec_before);
+ RELOC(t->exec_after);
+ RELOC(t->sysmon);
+ }
+}
+
+static char *sysmon_unit_value (sysmon_table_t *s, uint val)
+{
+ static char buf[32];
+ char *p, sign;
+ int decimal, frac;
+ int unit_val =
+ s->unit_min + (s->unit_max - s->unit_min) * val / s->val_mask;
+
+ if (val == -1)
+ return "I/O ERROR";
+
+ if (unit_val < 0) {
+ sign = '-';
+ unit_val = -unit_val;
+ } else
+ sign = '+';
+
+ p = buf + sprintf(buf, "%c%2d", sign, unit_val / s->unit_div);
+
+
+ frac = unit_val % s->unit_div;
+
+ frac /= (s->unit_div / s->unit_precision);
+
+ decimal = s->unit_precision;
+
+ if (decimal != 1)
+ *p++ = '.';
+ for (decimal /= 10; decimal != 0; decimal /= 10)
+ *p++ = '0' + (frac / decimal) % 10;
+ strcpy(p, s->unit_name);
+
+ return buf;
+}
+
+static void sysmon_dspic_init (sysmon_t * this)
+{
+}
+
+static int sysmon_dspic_read (sysmon_t * this, uint addr)
+{
+ ushort data;
+
+ return (dspic_read(addr, &data)) ? -1 : data;
+}
+
+static int sysmon_dspic_read_sgn (sysmon_t * this, uint addr)
+{
+ ushort data;
+
+ /* To fit into the table range we should add 0x8000 */
+ return (dspic_read(addr, &data)) ? -1 :
+ (signed short)data + 0x8000;
+}
+
+static void sysmon_backlight_disable (sysmon_table_t * this)
+{
+#if defined(CONFIG_VIDEO)
+ board_backlight_switch(this->val_valid_alt);
+#endif
+}
+
+int sysmon_post_test (int flags)
+{
+ int res = 0;
+ sysmon_table_t * t;
+ int val;
+
+ for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) {
+ if (t->exec_before)
+ t->exec_before(t);
+
+ val = t->sysmon->read(t->sysmon, t->addr);
+ if (val != -1) {
+ t->val_valid = val >= t->val_min && val <= t->val_max;
+ t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt;
+ } else {
+ t->val_valid = 0;
+ t->val_valid_alt = 0;
+ }
+
+ if (t->exec_after)
+ t->exec_after(t);
+
+ if ((!t->val_valid) || (flags & POST_MANUAL)) {
+ printf("%-17s = %-10s ", t->name, sysmon_unit_value(t, val));
+ printf("allowed range");
+ printf(" %-8s ..", sysmon_unit_value(t, t->val_min));
+ printf(" %-8s", sysmon_unit_value(t, t->val_max));
+ printf(" %s\n", t->val_valid ? "OK" : "FAIL");
+ }
+
+ if (!t->val_valid)
+ res = 1;
+ }
+
+ return res;
+}
+
+#endif /* CONFIG_POST & CFG_POST_SYSMON */
+#endif /* CONFIG_POST */
diff --git a/post/board/lwmon5/watchdog.c b/post/board/lwmon5/watchdog.c
new file mode 100644
index 0000000..48ff687
--- /dev/null
+++ b/post/board/lwmon5/watchdog.c
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
+ *
+ * Developed for DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * This test verifies if the reason of last reset was an abnormal voltage
+ * condition, than it performs watchdog test, measuing time required to
+ * trigger watchdog reset.
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_WATCHDOG
+
+#include <watchdog.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+static uint watchdog_magic_read(void)
+{
+ return in_be32((void *)CFG_WATCHDOG_FLAGS_ADDR) &
+ CFG_WATCHDOG_MAGIC_MASK;
+}
+
+static void watchdog_magic_write(uint value)
+{
+ out_be32((void *)CFG_WATCHDOG_FLAGS_ADDR, value |
+ (in_be32((void *)CFG_WATCHDOG_FLAGS_ADDR) &
+ ~CFG_WATCHDOG_MAGIC_MASK));
+}
+
+int sysmon1_post_test(int flags)
+{
+ if (gpio_read_in_bit(CFG_GPIO_SYSMON_STATUS)) {
+ /*
+ * 3.1. GPIO62 is low
+ * Assuming system voltage failure.
+ */
+ post_log("Abnormal voltage detected (GPIO62)\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+int lwmon5_watchdog_post_test(int flags)
+{
+ ulong time;
+
+ /* On each reset scratch register 1 should be tested,
+ * but first test GPIO62:
+ */
+ if (!(flags & POST_MANUAL) && sysmon1_post_test(flags)) {
+ /*
+ * 3.1. GPIO62 is low
+ * Assuming system voltage failure.
+ */
+ /* 3.1.1. Set scratch register 1 to 0x0000xxxx */
+ watchdog_magic_write(0);
+ /* 3.1.2. Mark test as failed due to voltage?! */
+ return 1;
+ }
+
+ if (watchdog_magic_read() != CFG_WATCHDOG_MAGIC) {
+ /*
+ * 3.2. Scratch register 1 differs from magic value 0x1248xxxx
+ * Assuming PowerOn
+ */
+ int ints;
+ ulong base;
+
+ /* 3.2.1. Set magic value to scratch register */
+ watchdog_magic_write(CFG_WATCHDOG_MAGIC);
+
+ ints = disable_interrupts ();
+ /* 3.2.2. strobe watchdog once */
+ WATCHDOG_RESET();
+ out_be32((void *)CFG_WATCHDOG_TIME_ADDR, 0);
+ /* 3.2.3. save time of strobe in scratch register 2 */
+ base = post_time_ms (0);
+
+ /* 3.2.4. Wait for 150 ms (enough for reset to happen) */
+ while ((time = post_time_ms (base)) < 150)
+ out_be32((void *)CFG_WATCHDOG_TIME_ADDR, time);
+ if (ints)
+ enable_interrupts ();
+
+ /*
+ * 3.2.5. Reset didn't happen. - Set 0x0000xxxx
+ * into scratch register 1
+ */
+ watchdog_magic_write(0);
+ /* 3.2.6. Mark test as failed. */
+ post_log("hw watchdog time : %u ms, failed ", time);
+ return 2;
+ }
+
+ /*
+ * 3.3. Scratch register matches magic value 0x1248xxxx
+ * Assume this is watchdog-initiated reset
+ */
+ /* 3.3.1. So, the test succeed, save measured time to syslog. */
+ time = in_be32((void *)CFG_WATCHDOG_TIME_ADDR);
+ post_log("hw watchdog time : %u ms, passed ", time);
+ /* 3.3.2. Set scratch register 1 to 0x0000xxxx */
+ watchdog_magic_write(0);
+
+ return 0;
+}
+
+#endif /* CONFIG_POST & CFG_POST_WATCHDOG */
+#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c
index c86a150..466ca92 100644
--- a/post/cpu/ppc4xx/cache.c
+++ b/post/cpu/ppc4xx/cache.c
@@ -42,8 +42,6 @@
#define CACHE_POST_SIZE 1024
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
-
int cache_post_test1 (int tlb, void *p, int size);
int cache_post_test2 (int tlb, void *p, int size);
int cache_post_test3 (int tlb, void *p, int size);
diff --git a/post/drivers/rtc.c b/post/drivers/rtc.c
index 7d4f9b8..e3da5e6 100644
--- a/post/drivers/rtc.c
+++ b/post/drivers/rtc.c
@@ -28,6 +28,8 @@
*
* The Real Time Clock (RTC) operation is verified by this test.
* The following features are verified:
+ * o) RTC Power Fault
+ * This is verified by analyzing the rtc_get() return status.
* o) Time uniformity
* This is verified by reading RTC in polling within
* a short period of time.
@@ -96,6 +98,10 @@ int rtc_post_test (int flags)
unsigned int ynl = 1999;
unsigned int yl = 2000;
unsigned int skipped = 0;
+ int reliable;
+
+ /* Time reliability */
+ reliable = rtc_get (&svtm);
/* Time uniformity */
if (rtc_post_skip (&diff) != 0) {
@@ -176,6 +182,15 @@ int rtc_post_test (int flags)
}
rtc_post_restore (&svtm, skipped);
+ /* If come here, then RTC operates correcty, check the correctness
+ * of the time it reports.
+ */
+ if (reliable < 0) {
+ post_log ("RTC Time is not reliable! Power fault? \n");
+
+ return -1;
+ }
+
return 0;
}
diff --git a/post/post.c b/post/post.c
index 4ff75ee..1df0657 100644
--- a/post/post.c
+++ b/post/post.c
@@ -157,8 +157,10 @@ static void post_bootmode_test_off (void)
static void post_get_flags (int *test_flags)
{
- int flag[] = { POST_POWERON, POST_NORMAL, POST_SLOWTEST };
- char *var[] = { "post_poweron", "post_normal", "post_slowtest" };
+ int flag[] = { POST_POWERON, POST_NORMAL, POST_SLOWTEST,
+ POST_CRITICAL };
+ char *var[] = { "post_poweron", "post_normal", "post_slowtest",
+ "post_critical" };
int varnum = sizeof (var) / sizeof (var[0]);
char list[128]; /* long enough for POST list */
char *name;
@@ -224,7 +226,9 @@ static int post_run_single (struct post_test *test,
if (!(flags & POST_REBOOT)) {
if ((test_flags & POST_REBOOT) && !(flags & POST_MANUAL)) {
- post_bootmode_test_on (i);
+ post_bootmode_test_on (
+ (gd->flags & GD_FLG_POSTFAIL) ?
+ POST_FAIL_SAVE | i : i);
}
if (test_flags & POST_PREREL)
@@ -236,10 +240,14 @@ static int post_run_single (struct post_test *test,
if (test_flags & POST_PREREL) {
if ((*test->test) (flags) == 0)
post_log_mark_succ ( test->testid );
+ else if (test_flags & POST_CRITICAL)
+ gd->flags |= GD_FLG_POSTFAIL;
} else {
if ((*test->test) (flags) != 0) {
post_log ("FAILED\n");
show_boot_progress (-32);
+ if (test_flags & POST_CRITICAL)
+ gd->flags |= GD_FLG_POSTFAIL;
}
else
post_log ("PASSED\n");
@@ -266,6 +274,10 @@ int post_run (char *name, int flags)
unsigned int last;
if (post_bootmode_get (&last) & POST_POWERTEST) {
+ if (last & POST_FAIL_SAVE) {
+ last &= ~POST_FAIL_SAVE;
+ gd->flags |= GD_FLG_POSTFAIL;
+ }
if (last < post_list_size &&
(flags & test_flags[last] & POST_ALWAYS) &&
(flags & test_flags[last] & POST_MEM)) {
diff --git a/post/tests.c b/post/tests.c
index 698f85c..53d01e3 100644
--- a/post/tests.c
+++ b/post/tests.c
@@ -48,6 +48,13 @@ extern int dsp_post_test (int flags);
extern int codec_post_test (int flags);
extern int ecc_post_test (int flags);
+extern int dspic_init_post_test (int flags);
+extern int dspic_post_test (int flags);
+extern int gdc_post_test (int flags);
+extern int fpga_post_test (int flags);
+extern int lwmon5_watchdog_post_test(int flags);
+extern int sysmon1_post_test(int flags);
+
extern int sysmon_init_f (void);
extern void sysmon_reloc (void);
@@ -68,6 +75,9 @@ struct post_test post_list[] =
},
#endif
#if CONFIG_POST & CFG_POST_WATCHDOG
+#if defined(CONFIG_POST_WATCHDOG)
+ CONFIG_POST_WATCHDOG,
+#else
{
"Watchdog timer test",
"watchdog",
@@ -79,6 +89,7 @@ struct post_test post_list[] =
CFG_POST_WATCHDOG
},
#endif
+#endif
#if CONFIG_POST & CFG_POST_I2C
{
"I2C test",
@@ -225,7 +236,7 @@ struct post_test post_list[] =
CFG_POST_DSP
},
#endif
-#if CONFIG_POST & CFG_POST_DSP
+#if CONFIG_POST & CFG_POST_CODEC
{
"CODEC test",
"codec",
@@ -249,6 +260,21 @@ struct post_test post_list[] =
CFG_POST_ECC
},
#endif
+#if CONFIG_POST & CFG_POST_BSPEC1
+ CONFIG_POST_BSPEC1,
+#endif
+#if CONFIG_POST & CFG_POST_BSPEC2
+ CONFIG_POST_BSPEC2,
+#endif
+#if CONFIG_POST & CFG_POST_BSPEC3
+ CONFIG_POST_BSPEC3,
+#endif
+#if CONFIG_POST & CFG_POST_BSPEC4
+ CONFIG_POST_BSPEC4,
+#endif
+#if CONFIG_POST & CFG_POST_BSPEC4
+ CONFIG_POST_BSPEC5,
+#endif
};
unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test);
generated by cgit v1.1 at 2024-12-22 04:07:13 +0000