diff options
Diffstat (limited to 'post')
| -rw-r--r-- | post/cpu/ppc4xx/Makefile | 1 | ||||
| -rw-r--r-- | post/cpu/ppc4xx/ocm.c | 89 | ||||
| -rw-r--r-- | post/tests.c | 13 |
3 files changed, 103 insertions, 0 deletions
diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile index f19dc5d..1cfd3bb 100644 --- a/post/cpu/ppc4xx/Makefile +++ b/post/cpu/ppc4xx/Makefile @@ -29,6 +29,7 @@ COBJS-$(CONFIG_HAS_POST) += cache.o COBJS-$(CONFIG_HAS_POST) += denali_ecc.o COBJS-$(CONFIG_HAS_POST) += ether.o COBJS-$(CONFIG_HAS_POST) += fpu.o +COBJS-$(CONFIG_HAS_POST) += ocm.o COBJS-$(CONFIG_HAS_POST) += spr.o COBJS-$(CONFIG_HAS_POST) += uart.o COBJS-$(CONFIG_HAS_POST) += watchdog.o diff --git a/post/cpu/ppc4xx/ocm.c b/post/cpu/ppc4xx/ocm.c new file mode 100644 index 0000000..88aa93e --- /dev/null +++ b/post/cpu/ppc4xx/ocm.c @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2008 Ilya Yanok, EmCraft Systems, yanok@emcraft.com + * + * Developed for DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +/* + * This test attempts to verify on-chip memory (OCM). Result is written + * to the scratch register and if test succeed it won't be run till next + * power on. + */ + +#include <post.h> + +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define OCM_TEST_PATTERN1 0x55555555 +#define OCM_TEST_PATTERN2 0xAAAAAAAA + +#if CONFIG_POST & CFG_POST_OCM + +static uint ocm_status_read(void) +{ + return in_be32((void *)CFG_OCM_STATUS_ADDR) & + CFG_OCM_STATUS_MASK; +} + +static void ocm_status_write(uint value) +{ + out_be32((void *)CFG_OCM_STATUS_ADDR, value | + (in_be32((void *)CFG_OCM_STATUS_ADDR) & + ~CFG_OCM_STATUS_MASK)); +} + +static inline int ocm_test_word(uint value, uint *address) +{ + uint read_value; + + *address = value; + sync(); + read_value = *address; + + return (read_value != value); +} + +int ocm_post_test(int flags) +{ + uint old_value; + int ret = 0; + uint *address = (uint*)CFG_OCM_BASE; + + if (ocm_status_read() == CFG_OCM_STATUS_OK) + return 0; + for (; address < (uint*)(CFG_OCM_BASE + CFG_OCM_SIZE); address++) { + old_value = *address; + if (ocm_test_word(OCM_TEST_PATTERN1, address) || + ocm_test_word(OCM_TEST_PATTERN2, address)) { + ret = 1; + *address = old_value; + printf("OCM POST failed at %p!\n", address); + break; + } + *address = old_value; + } + ocm_status_write(ret ? CFG_OCM_STATUS_FAIL : CFG_OCM_STATUS_OK); + return ret; +} +#endif /* CONFIG_POST & CFG_POST_OCM */ diff --git a/post/tests.c b/post/tests.c index 5db59d6..cdf4c86 100644 --- a/post/tests.c +++ b/post/tests.c @@ -29,6 +29,7 @@ #include <post.h> +extern int ocm_post_test (int flags); extern int cache_post_test (int flags); extern int watchdog_post_test (int flags); extern int i2c_post_test (int flags); @@ -60,6 +61,18 @@ extern void sysmon_reloc (void); struct post_test post_list[] = { +#if CONFIG_POST & CFG_POST_OCM + { + "OCM test", + "ocm", + "This test checks on chip memory (OCM).", + POST_ROM | POST_ALWAYS | POST_PREREL | POST_CRITICAL, + &ocm_post_test, + NULL, + NULL, + CFG_POST_OCM + }, +#endif #if CONFIG_POST & CFG_POST_CACHE { "Cache test", |