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-rw-r--r--post/board/lwmon5/Makefile29
-rw-r--r--post/cpu/ppc4xx/Makefile2
-rw-r--r--post/cpu/ppc4xx/cache.c45
-rw-r--r--post/cpu/ppc4xx/denali_ecc.c (renamed from post/board/lwmon5/ecc.c)102
-rw-r--r--post/cpu/ppc4xx/ether.c89
-rw-r--r--post/cpu/ppc4xx/uart.c15
-rw-r--r--post/lib_ppc/cpu.c11
-rw-r--r--post/tests.c2
8 files changed, 160 insertions, 135 deletions
diff --git a/post/board/lwmon5/Makefile b/post/board/lwmon5/Makefile
deleted file mode 100644
index c3f54e3..0000000
--- a/post/board/lwmon5/Makefile
+++ /dev/null
@@ -1,29 +0,0 @@
-#
-# (C) Copyright 2002-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-
-LIB = libpostlwmon5.a
-
-COBJS = ecc.o
-
-include $(TOPDIR)/post/rules.mk
diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile
index f1034da..e3f44b7 100644
--- a/post/cpu/ppc4xx/Makefile
+++ b/post/cpu/ppc4xx/Makefile
@@ -24,6 +24,6 @@
LIB = libpostppc4xx.a
AOBJS = cache_4xx.o
-COBJS = cache.o ether.o fpu.o spr.o uart.o watchdog.o
+COBJS = cache.o denali_ecc.o ether.o fpu.o spr.o uart.o watchdog.o
include $(TOPDIR)/post/rules.mk
diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c
index 109ca1f..c86a150 100644
--- a/post/cpu/ppc4xx/cache.c
+++ b/post/cpu/ppc4xx/cache.c
@@ -51,8 +51,6 @@ int cache_post_test4 (int tlb, void *p, int size);
int cache_post_test5 (int tlb, void *p, int size);
int cache_post_test6 (int tlb, void *p, int size);
-static int tlb = -1; /* index to the victim TLB entry */
-
#ifdef CONFIG_440
static unsigned char testarea[CACHE_POST_SIZE]
__attribute__((__aligned__(CACHE_POST_SIZE)));
@@ -60,9 +58,10 @@ __attribute__((__aligned__(CACHE_POST_SIZE)));
int cache_post_test (int flags)
{
- void* virt = (void*)CFG_POST_CACHE_ADDR;
+ void *virt = (void *)CFG_POST_CACHE_ADDR;
int ints;
int res = 0;
+ int tlb = -1; /* index to the victim TLB entry */
/*
* All 44x variants deal with cache management differently
@@ -73,25 +72,23 @@ int cache_post_test (int flags)
#ifdef CONFIG_440
int word0, i;
- if (tlb < 0) {
- /*
- * Allocate a new TLB entry, since we are going to modify
- * the write-through and caching inhibited storage attributes.
- */
- program_tlb((u32)testarea, (u32)virt,
- CACHE_POST_SIZE, TLB_WORD2_I_ENABLE);
-
- /* Find the TLB entry */
- for (i = 0;; i++) {
- if (i >= PPC4XX_TLB_SIZE) {
- printf ("Failed to program tlb entry\n");
- return -1;
- }
- word0 = mftlb1(i);
- if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
- tlb = i;
- break;
- }
+ /*
+ * Allocate a new TLB entry, since we are going to modify
+ * the write-through and caching inhibited storage attributes.
+ */
+ program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE,
+ TLB_WORD2_I_ENABLE);
+
+ /* Find the TLB entry */
+ for (i = 0;; i++) {
+ if (i >= PPC4XX_TLB_SIZE) {
+ printf ("Failed to program tlb entry\n");
+ return -1;
+ }
+ word0 = mftlb1(i);
+ if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
+ tlb = i;
+ break;
}
}
#endif
@@ -119,6 +116,10 @@ int cache_post_test (int flags)
if (ints)
enable_interrupts ();
+#ifdef CONFIG_440
+ remove_tlb((u32)virt, CACHE_POST_SIZE);
+#endif
+
return res;
}
diff --git a/post/board/lwmon5/ecc.c b/post/cpu/ppc4xx/denali_ecc.c
index 3fa3ba6..7723483 100644
--- a/post/board/lwmon5/ecc.c
+++ b/post/cpu/ppc4xx/denali_ecc.c
@@ -31,7 +31,7 @@
#include <common.h>
#include <watchdog.h>
-#ifdef CONFIG_POST
+#if defined(CONFIG_POST) && (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
#include <post.h>
@@ -47,12 +47,10 @@
#include <asm/io.h>
#include <ppc440.h>
-#include "../../../board/lwmon5/sdram.h"
-
DECLARE_GLOBAL_DATA_PTR;
const static unsigned char syndrome_codes[] = {
- 0xF4, 0XF1, 0XEC ,0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
+ 0xF4, 0XF1, 0XEC, 0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2,
0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A,
@@ -65,9 +63,9 @@ const static unsigned char syndrome_codes[] = {
#define ECC_START_ADDR 0x10
#define ECC_STOP_ADDR 0x2000
-#define ECC_PATTERN 0x0101010101010101ull
-#define ECC_PATTERN_CORR 0x0101010101010100ull
-#define ECC_PATTERN_UNCORR 0x010101010101010Full
+#define ECC_PATTERN 0x01010101
+#define ECC_PATTERN_CORR 0x11010101
+#define ECC_PATTERN_UNCORR 0xF1010101
static int test_ecc_error(void)
{
@@ -152,68 +150,78 @@ static int test_ecc_error(void)
static int test_ecc(unsigned long ecc_addr)
{
- volatile unsigned long long *ecc_mem;
unsigned long value;
- unsigned long ecc_data;
- volatile unsigned long *lecc_mem;
- int pret, ret = 0;
+ volatile unsigned *const ecc_mem = (volatile unsigned *) ecc_addr;
+ int pret;
+ int ret = 0;
sync();
eieio();
WATCHDOG_RESET();
- ecc_mem = (unsigned long long *)ecc_addr;
- lecc_mem = (ulong *)ecc_addr;
- *ecc_mem = ECC_PATTERN;
+ debug("Entering test_ecc(0x%08lX)\n", ecc_addr);
+ out_be32(ecc_mem, ECC_PATTERN);
+ out_be32(ecc_mem + 1, ECC_PATTERN);
+ in_be32(ecc_mem);
pret = test_ecc_error();
- if (pret != 0)
+ if (pret != 0) {
+ debug("pret: expected 0, got %d\n", pret);
ret = 1;
-
- /* disconnect ecc */
+ }
+ /* test for correctable error */
+ /* disconnect from ecc storage */
mfsdram(DDR0_22, value);
- mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
+ mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
| DDR0_22_CTRL_RAW_ECC_DISABLE);
- /* injecting error */
- *ecc_mem = ECC_PATTERN_CORR;
+ /* creating (correctable) single-bit error */
+ out_be32(ecc_mem, ECC_PATTERN_CORR);
/* enable ecc */
mfsdram(DDR0_22, value);
- mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
+ mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
| DDR0_22_CTRL_RAW_ECC_ENABLE);
+ sync();
+ eieio();
- ecc_data = *lecc_mem;
+ in_be32(ecc_mem);
pret = test_ecc_error();
/* if read data ok, 1 correctable error must be fixed */
- if (pret != 3)
+ if (pret != 3) {
+ debug("pret: expected 3, got %d\n", pret);
ret = 1;
-
+ }
/* test for uncorrectable error */
/* disconnect from ecc storage */
mfsdram(DDR0_22, value);
- mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
+ mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
| DDR0_22_CTRL_RAW_NO_ECC_RAM);
- /* injecting multiply bit error */
-
- *ecc_mem = ECC_PATTERN_UNCORR;
+ /* creating (uncorrectable) multiple-bit error */
+ out_be32(ecc_mem, ECC_PATTERN_UNCORR);
/* enable ecc */
mfsdram(DDR0_22, value);
- mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
+ mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
| DDR0_22_CTRL_RAW_ECC_ENABLE);
+ sync();
+ eieio();
- ecc_data = *lecc_mem;
- /* what the data should be read? */
-
+ in_be32(ecc_mem);
pret = test_ecc_error();
/* info about uncorrectable error must appear */
- if (pret != 5)
+ if (pret != 5) {
+ debug("pret: expected 5, got %d\n", pret);
ret = 1;
+ }
+ /* remove error from SDRAM */
+ out_be32(ecc_mem, ECC_PATTERN);
+ /* clear error caused by read-modify-write */
+ mfsdram(DDR0_00, value);
+ mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
sync();
eieio();
-
return ret;
}
@@ -223,45 +231,37 @@ int ecc_post_test (int flags)
unsigned long value;
unsigned long iaddr;
-#if CONFIG_DDR_ECC
sync();
eieio();
+ mfsdram(DDR0_22, value);
+ if (0x3 != DDR0_22_CTRL_RAW_DECODE(value)) {
+ debug("SDRAM ECC not enabled, skipping ECC POST.\n");
+ return 0;
+ }
+
/* mask all int */
mfsdram(DDR0_01, value);
- mtsdram(DDR0_01, (value &~ DDR0_01_INT_MASK_MASK)
+ mtsdram(DDR0_01, (value & ~DDR0_01_INT_MASK_MASK)
| DDR0_01_INT_MASK_ALL_OFF);
/* clear error status */
mfsdram(DDR0_00, value);
mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
- /* enable full support of ECC */
- mfsdram(DDR0_22, value);
- mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
- | DDR0_22_CTRL_RAW_ECC_ENABLE);
-
- for (iaddr = ECC_START_ADDR; iaddr < ECC_STOP_ADDR; iaddr += iaddr) {
+ for (iaddr = ECC_START_ADDR; iaddr <= ECC_STOP_ADDR; iaddr += iaddr) {
ret = test_ecc(iaddr);
if (ret)
break;
}
-
- /* clear error status */
- mfsdram(DDR0_00, value);
- mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
-
/*
* Clear possible errors resulting from ECC testing.
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
set_mcsr(get_mcsr());
-#endif
-
return ret;
}
-
#endif /* CONFIG_POST & CFG_POST_ECC */
-#endif /* CONFIG_POST */
+#endif /* defined(CONFIG_POST) && ... */
diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c
index ab23ca5..4ac7491 100644
--- a/post/cpu/ppc4xx/ether.c
+++ b/post/cpu/ppc4xx/ether.c
@@ -52,6 +52,28 @@
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Get count of EMAC devices (doesn't have to be the max. possible number
+ * supported by the cpu)
+ *
+ * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
+ * EMAC count is possible. As it is needed for the Kilauea/Haleakala
+ * 405EX/405EXr eval board, using the same binary.
+ */
+#if defined(CONFIG_BOARD_EMAC_COUNT)
+#define LAST_EMAC_NUM board_emac_count()
+#else /* CONFIG_BOARD_EMAC_COUNT */
+#if defined(CONFIG_HAS_ETH3)
+#define LAST_EMAC_NUM 4
+#elif defined(CONFIG_HAS_ETH2)
+#define LAST_EMAC_NUM 3
+#elif defined(CONFIG_HAS_ETH1)
+#define LAST_EMAC_NUM 2
+#else
+#define LAST_EMAC_NUM 1
+#endif
+#endif /* CONFIG_BOARD_EMAC_COUNT */
+
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
#endif
@@ -65,6 +87,8 @@ static volatile mal_desc_t rx __cacheline_aligned;
static char *tx_buf;
static char *rx_buf;
+int board_emac_count(void);
+
static void ether_post_init (int devnum, int hw_addr)
{
int i;
@@ -93,11 +117,11 @@ static void ether_post_init (int devnum, int hw_addr)
sync ();
#endif
/* reset emac */
- out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
+ out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST);
sync ();
for (i = 0;; i++) {
- if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST))
+ if (!(in_be32 ((void*)(EMAC_M0 + hw_addr)) & EMAC_M0_SRST))
break;
if (i >= 1000) {
printf ("Timeout resetting EMAC\n");
@@ -120,7 +144,7 @@ static void ether_post_init (int devnum, int hw_addr)
else
mode_reg |= EMAC_M1_OBCI_GT100;
- out32 (EMAC_M1 + hw_addr, mode_reg);
+ out_be32 ((void*)(EMAC_M1 + hw_addr), mode_reg);
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
@@ -145,6 +169,8 @@ static void ether_post_init (int devnum, int hw_addr)
rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
rx.data_len = 0;
rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
+ flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
+ flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
switch (devnum) {
case 1:
@@ -186,40 +212,40 @@ static void ether_post_init (int devnum, int hw_addr)
/* set internal loopback mode */
#ifdef CFG_POST_ETHER_EXT_LOOPBACK
- out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | 0 |
- EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
- EMAC_M1_MF_100MBPS | EMAC_M1_IST |
- in32 (EMAC_M1));
+ out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | 0 |
+ EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
+ EMAC_M1_MF_100MBPS | EMAC_M1_IST |
+ in_be32 ((void*)(EMAC_M1 + hw_addr)));
#else
- out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
- EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
- EMAC_M1_MF_100MBPS | EMAC_M1_IST |
- in32 (EMAC_M1));
+ out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | EMAC_M1_ILE |
+ EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
+ EMAC_M1_MF_100MBPS | EMAC_M1_IST |
+ in_be32 ((void*)(EMAC_M1 + hw_addr)));
#endif
/* set transmit enable & receive enable */
- out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
+ out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_TXE | EMAC_M0_RXE);
/* enable broadcast address */
- out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE);
+ out_be32 ((void*)(EMAC_RXM + hw_addr), EMAC_RMR_BAE);
/* set transmit request threshold register */
- out32 (EMAC_TRTR + hw_addr, 0x18000000); /* 256 byte threshold */
+ out_be32 ((void*)(EMAC_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */
/* set receive low/high water mark register */
#if defined(CONFIG_440)
/* 440s has a 64 byte burst length */
- out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000);
+ out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x80009000);
#else
/* 405s have a 16 byte burst length */
- out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000);
+ out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
#endif /* defined(CONFIG_440) */
- out32 (EMAC_TXM1 + hw_addr, 0xf8640000);
+ out_be32 ((void*)(EMAC_TXM1 + hw_addr), 0xf8640000);
/* Set fifo limit entry in tx mode 0 */
- out32 (EMAC_TXM0 + hw_addr, 0x00000003);
+ out_be32 ((void*)(EMAC_TXM0 + hw_addr), 0x00000003);
/* Frame gap set */
- out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008);
+ out_be32 ((void*)(EMAC_I_FRAME_GAP_REG + hw_addr), 0x00000008);
sync ();
}
@@ -246,7 +272,7 @@ static void ether_post_halt (int devnum, int hw_addr)
udelay (1000);
}
/* emac reset */
- out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
+ out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST);
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* remove clocks for EMAC internal loopback */
@@ -266,14 +292,17 @@ static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
return;
}
udelay (1000);
+ invalidate_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
}
tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
tx.data_len = length;
memcpy (tx.data_ptr, packet, length);
+ flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
+ flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
sync ();
- out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0);
+ out_be32 ((void*)(EMAC_TXM0 + hw_addr), in_be32 ((void*)(EMAC_TXM0 + hw_addr)) | EMAC_TXM0_GNP0);
sync ();
}
@@ -288,13 +317,17 @@ static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_lengt
return 0;
}
udelay (1000);
+ invalidate_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
}
length = rx.data_len - 4;
- if (length <= max_length)
+ if (length <= max_length) {
+ invalidate_dcache_range((u32)rx.data_ptr, (u32)rx.data_ptr + length);
memcpy(packet, rx.data_ptr, length);
+ }
sync ();
rx.ctrl |= MAL_RX_CTRL_EMPTY;
+ flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
sync ();
return length;
@@ -372,6 +405,7 @@ Done:
int ether_post_test (int flags)
{
int res = 0;
+ int i;
/* Allocate tx & rx packet buffers */
tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
@@ -383,13 +417,10 @@ int ether_post_test (int flags)
goto out_free;
}
- /* EMAC0 */
- if (test_ctlr (0, 0))
- res = -1;
-
- /* EMAC1 */
- if (test_ctlr (1, 0x100))
- res = -1;
+ for (i = 0; i < LAST_EMAC_NUM; i++) {
+ if (test_ctlr (i, i*0x100))
+ res = -1;
+ }
out_free:
free (tx_buf);
diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c
index 7c3ed40..f47b48e 100644
--- a/post/cpu/ppc4xx/uart.c
+++ b/post/cpu/ppc4xx/uart.c
@@ -101,6 +101,17 @@
#define UCR0_UDIV_POS 0
#define UCR1_UDIV_POS 8
#define UDIV_MAX 127
+#elif defined(CONFIG_405EX)
+#define UART0_BASE 0xef600200
+#define UART1_BASE 0xef600300
+#define CR0_MASK 0x000000ff
+#define CR0_EXTCLK_ENA 0x00800000
+#define CR0_UDIV_POS 0
+#define UDIV_SUBTRACT 0
+#define UART0_SDR sdr_uart0
+#define UART1_SDR sdr_uart1
+#define MFREG(a, d) mfsdr(a, d)
+#define MTREG(a, d) mtsdr(a, d)
#else /* CONFIG_405GP || CONFIG_405CR */
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
@@ -137,7 +148,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_440)
+#if defined(CONFIG_440) || defined(CONFIG_405EX)
#if !defined(CFG_EXT_SERIAL_CLOCK)
static void serial_divs (int baudrate, unsigned long *pudiv,
unsigned short *pbdiv)
@@ -183,7 +194,7 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
static int uart_post_init (unsigned long dev_base)
{
- unsigned long reg;
+ unsigned long reg = 0;
unsigned long udiv;
unsigned short bdiv;
volatile char val;
diff --git a/post/lib_ppc/cpu.c b/post/lib_ppc/cpu.c
index 1f2ded2..4ab6d2d 100644
--- a/post/lib_ppc/cpu.c
+++ b/post/lib_ppc/cpu.c
@@ -36,6 +36,7 @@
#include <watchdog.h>
#include <post.h>
+#include <asm/mmu.h>
#if CONFIG_POST & CFG_POST_CPU
@@ -59,6 +60,8 @@ extern int cpu_post_test_multi (void);
extern int cpu_post_test_string (void);
extern int cpu_post_test_complex (void);
+DECLARE_GLOBAL_DATA_PTR;
+
ulong cpu_post_makecr (long v)
{
ulong cr = 0;
@@ -81,6 +84,10 @@ int cpu_post_test (int flags)
WATCHDOG_RESET();
if (ic)
icache_disable ();
+#ifdef CONFIG_4xx_DCACHE
+ /* disable cache */
+ change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
+#endif
if (ret == 0)
ret = cpu_post_test_cmp ();
@@ -129,6 +136,10 @@ int cpu_post_test (int flags)
if (ic)
icache_enable ();
+#ifdef CONFIG_4xx_DCACHE
+ /* enable cache */
+ change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
+#endif
WATCHDOG_RESET();
diff --git a/post/tests.c b/post/tests.c
index e1c3d28..0c49e32 100644
--- a/post/tests.c
+++ b/post/tests.c
@@ -194,7 +194,7 @@ struct post_test post_list[] =
"SPR test",
"spr",
"This test checks SPR contents.",
- POST_ROM | POST_ALWAYS | POST_PREREL,
+ POST_RAM | POST_ALWAYS,
&spr_post_test,
NULL,
NULL,
generated by cgit v1.1 at 2024-11-16 18:27:19 +0000