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-rw-r--r--lib_blackfin/board.c14
-rw-r--r--lib_blackfin/cache.c35
2 files changed, 40 insertions, 9 deletions
diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c
index ba57392..e184fd2 100644
--- a/lib_blackfin/board.c
+++ b/lib_blackfin/board.c
@@ -250,7 +250,6 @@ void init_cplbtables(void)
extern int exception_init(void);
extern int irq_init(void);
-extern int rtc_init(void);
extern int timer_init(void);
void board_init_f(ulong bootflag)
@@ -313,9 +312,6 @@ void board_init_f(ulong bootflag)
display_banner();
checkboard();
-#if defined(CONFIG_RTC_BFIN) && defined(CONFIG_CMD_DATE)
- rtc_init();
-#endif
timer_init();
printf("Clock: VCO: %lu MHz, Core: %lu MHz, System: %lu MHz\n",
@@ -384,6 +380,11 @@ void board_init_r(gd_t * id, ulong dest_addr)
spi_init_r();
#endif
+#ifdef CONFIG_CMD_NAND
+ puts("NAND: ");
+ nand_init(); /* go init the NAND */
+#endif
+
/* relocate environment function pointers etc. */
env_relocate();
@@ -431,11 +432,6 @@ void board_init_r(gd_t * id, ulong dest_addr)
copy_filename(BootFile, s, sizeof(BootFile));
#endif
-#ifdef CONFIG_CMD_NAND
- puts("NAND: ");
- nand_init(); /* go init the NAND */
-#endif
-
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r();
diff --git a/lib_blackfin/cache.c b/lib_blackfin/cache.c
index c2f6e28..870c5bf 100644
--- a/lib_blackfin/cache.c
+++ b/lib_blackfin/cache.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <asm/blackfin.h>
+#include <asm/mach-common/bits/mpu.h>
void flush_cache(unsigned long addr, unsigned long size)
{
@@ -24,3 +25,37 @@ void flush_cache(unsigned long addr, unsigned long size)
if (dcache_status())
blackfin_dcache_flush_range((void *)addr, (void *)(addr + size));
}
+
+void icache_enable(void)
+{
+ bfin_write_IMEM_CONTROL(IMC | ENICPLB);
+ SSYNC();
+}
+
+void icache_disable(void)
+{
+ bfin_write_IMEM_CONTROL(0);
+ SSYNC();
+}
+
+int icache_status(void)
+{
+ return bfin_read_IMEM_CONTROL() & IMC;
+}
+
+void dcache_enable(void)
+{
+ bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+ SSYNC();
+}
+
+void dcache_disable(void)
+{
+ bfin_write_DMEM_CONTROL(0);
+ SSYNC();
+}
+
+int dcache_status(void)
+{
+ return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE;
+}