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-rw-r--r--include/configs/hmi1001.h1
-rw-r--r--include/configs/ocotea.h3
-rw-r--r--include/ppc440.h16
3 files changed, 11 insertions, 9 deletions
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index cfaf153..095b5f6 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -210,6 +210,7 @@
*/
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_PHY_ADDR 0x00
+#define CONFIG_MII 1 /* MII PHY management */
/*
* GPIO configuration
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
index 0e3660b..fe4e638 100644
--- a/include/configs/ocotea.h
+++ b/include/configs/ocotea.h
@@ -148,8 +148,9 @@
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
+#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/
/*-----------------------------------------------------------------------
* I2C
diff --git a/include/ppc440.h b/include/ppc440.h
index 1c7f11c..25e338f 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -3293,26 +3293,26 @@ typedef struct { unsigned long add; /* gpio core base address */
/*
* Macros for accessing the indirect EBC registers
*/
-#define mtebc(reg, data) { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); }
-#define mfebc(reg, data) { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); }
+#define mtebc(reg, data) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); } while (0)
+#define mfebc(reg, data) do { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); } while (0)
/*
* Macros for accessing the indirect SDRAM controller registers
*/
-#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); }
-#define mfsdram(reg, data) { mtdcr(memcfga,reg);data = mfdcr(memcfgd); }
+#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0)
+#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0)
/*
* Macros for accessing the indirect clocking controller registers
*/
-#define mtclk(reg, data) { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); }
-#define mfclk(reg, data) { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); }
+#define mtclk(reg, data) do { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); } while (0)
+#define mfclk(reg, data) do { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); } while (0)
/*
* Macros for accessing the sdr controller registers
*/
-#define mtsdr(reg, data) { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); }
-#define mfsdr(reg, data) { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); }
+#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
+#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
#ifndef __ASSEMBLY__