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-rw-r--r--include/ahci.h2
-rw-r--r--include/asm-arm/arch-kirkwood/gpio.h53
-rw-r--r--include/asm-arm/arch-kirkwood/kirkwood.h1
-rw-r--r--include/asm-arm/arch-nomadik/gpio.h42
-rw-r--r--include/asm-arm/arch-omap24xx/i2c.h44
-rw-r--r--include/asm-arm/arch-omap3/i2c.h70
-rw-r--r--include/asm-arm/arch-omap3/omap3.h35
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h2
-rw-r--r--include/asm-arm/errno.h139
-rw-r--r--include/asm-arm/unaligned.h18
-rw-r--r--include/asm-avr32/arch-at32ap700x/chip-features.h5
-rw-r--r--include/asm-avr32/arch-at32ap700x/clk.h6
-rw-r--r--include/asm-avr32/arch-at32ap700x/portmux.h3
-rw-r--r--include/asm-avr32/errno.h133
-rw-r--r--include/asm-avr32/global_data.h3
-rw-r--r--include/asm-blackfin/blackfin_local.h3
-rw-r--r--include/asm-blackfin/errno.h157
-rw-r--r--include/asm-generic/errno.h155
-rw-r--r--include/asm-m68k/errno.h139
-rw-r--r--include/asm-microblaze/byteorder.h4
-rw-r--r--include/asm-microblaze/errno.h1
-rw-r--r--include/asm-ppc/config.h9
-rw-r--r--include/asm-ppc/errno.h139
-rw-r--r--include/asm-ppc/gpio.h24
-rw-r--r--include/asm-ppc/immap_83xx.h11
-rw-r--r--include/asm-ppc/immap_86xx.h4
-rw-r--r--include/asm-ppc/ppc4xx_config.h (renamed from include/console.h)28
-rw-r--r--include/asm-ppc/processor.h48
-rw-r--r--include/asm-sh/errno.h157
-rw-r--r--include/asm-sparc/errno.h163
-rw-r--r--include/bus_vcxk.h36
-rw-r--r--include/common.h32
-rw-r--r--include/compiler.h125
-rw-r--r--include/config_cmd_default.h6
-rw-r--r--include/configs/ASH405.h6
-rw-r--r--include/configs/AmigaOneG3SE.h2
-rw-r--r--include/configs/BMW.h4
-rw-r--r--include/configs/CATcenter.h8
-rw-r--r--include/configs/CMS700.h2
-rw-r--r--include/configs/CPU86.h10
-rw-r--r--include/configs/CPU87.h4
-rw-r--r--include/configs/EB+MCF-EV123.h176
-rw-r--r--include/configs/FPS850L.h4
-rw-r--r--include/configs/FPS860L.h4
-rw-r--r--include/configs/G2000.h20
-rw-r--r--include/configs/GEN860T.h17
-rw-r--r--include/configs/HH405.h2
-rw-r--r--include/configs/HMI10.h4
-rw-r--r--include/configs/HUB405.h2
-rw-r--r--include/configs/IDS8247.h2
-rw-r--r--include/configs/MIP405.h12
-rw-r--r--include/configs/MPC8313ERDB.h4
-rw-r--r--include/configs/MPC8315ERDB.h5
-rw-r--r--include/configs/MPC8323ERDB.h3
-rw-r--r--include/configs/MPC832XEMDS.h33
-rw-r--r--include/configs/MPC8349EMDS.h6
-rw-r--r--include/configs/MPC8349ITX.h35
-rw-r--r--include/configs/MPC8360EMDS.h29
-rw-r--r--include/configs/MPC8360ERDK.h2
-rw-r--r--include/configs/MPC837XEMDS.h4
-rw-r--r--include/configs/MPC837XERDB.h21
-rw-r--r--include/configs/MPC8536DS.h12
-rw-r--r--include/configs/MPC8540ADS.h4
-rw-r--r--include/configs/MPC8541CDS.h4
-rw-r--r--include/configs/MPC8544DS.h7
-rw-r--r--include/configs/MPC8548CDS.h4
-rw-r--r--include/configs/MPC8555CDS.h4
-rw-r--r--include/configs/MPC8560ADS.h4
-rw-r--r--include/configs/MPC8568MDS.h4
-rw-r--r--include/configs/MPC8569MDS.h6
-rw-r--r--include/configs/MPC8572DS.h9
-rw-r--r--include/configs/MPC8610HPCD.h2
-rw-r--r--include/configs/MPC8641HPCN.h4
-rw-r--r--include/configs/MVBC_P.h14
-rw-r--r--include/configs/MVBLM7.h1
-rw-r--r--include/configs/NETPHONE.h87
-rw-r--r--include/configs/NETTA.h100
-rw-r--r--include/configs/NETTA2.h87
-rw-r--r--include/configs/NETVIA.h76
-rw-r--r--include/configs/NSCU.h2
-rw-r--r--include/configs/P2020DS.h10
-rw-r--r--include/configs/PCIPPC2.h12
-rw-r--r--include/configs/PCIPPC6.h12
-rw-r--r--include/configs/PIP405.h6
-rw-r--r--include/configs/PLU405.h2
-rw-r--r--include/configs/PM520.h19
-rw-r--r--include/configs/PM826.h14
-rw-r--r--include/configs/PM828.h13
-rw-r--r--include/configs/PMC405DE.h378
-rw-r--r--include/configs/PPChameleonEVB.h29
-rw-r--r--include/configs/RBC823.h9
-rw-r--r--include/configs/SIMPC8313.h2
-rw-r--r--include/configs/SM850.h8
-rw-r--r--include/configs/SXNI855T.h67
-rw-r--r--include/configs/TK885D.h3
-rw-r--r--include/configs/TQM823L.h4
-rw-r--r--include/configs/TQM823M.h4
-rw-r--r--include/configs/TQM8272.h2
-rw-r--r--include/configs/TQM834x.h13
-rw-r--r--include/configs/TQM850L.h4
-rw-r--r--include/configs/TQM850M.h4
-rw-r--r--include/configs/TQM855L.h5
-rw-r--r--include/configs/TQM855M.h5
-rw-r--r--include/configs/TQM85xx.h4
-rw-r--r--include/configs/TQM860L.h5
-rw-r--r--include/configs/TQM860M.h5
-rw-r--r--include/configs/TQM862L.h5
-rw-r--r--include/configs/TQM862M.h5
-rw-r--r--include/configs/TQM866M.h3
-rw-r--r--include/configs/TQM885D.h3
-rw-r--r--include/configs/VCMA9.h40
-rw-r--r--include/configs/VOH405.h2
-rw-r--r--include/configs/WUH405.h2
-rw-r--r--include/configs/XPEDITE1000.h356
-rw-r--r--include/configs/XPEDITE1K.h274
-rw-r--r--include/configs/XPEDITE5170.h2
-rw-r--r--include/configs/XPEDITE5200.h2
-rw-r--r--include/configs/XPEDITE5370.h11
-rw-r--r--include/configs/acadia.h2
-rw-r--r--include/configs/afeb9260.h3
-rw-r--r--include/configs/amcc-common.h13
-rw-r--r--include/configs/ap325rxa.h7
-rw-r--r--include/configs/apollon.h2
-rw-r--r--include/configs/aria.h1
-rw-r--r--include/configs/at91cap9adk.h5
-rw-r--r--include/configs/at91rm9200dk.h35
-rw-r--r--include/configs/at91rm9200ek.h6
-rw-r--r--include/configs/at91sam9260ek.h3
-rw-r--r--include/configs/at91sam9261ek.h3
-rw-r--r--include/configs/at91sam9263ek.h3
-rw-r--r--include/configs/at91sam9m10g45ek.h4
-rw-r--r--include/configs/at91sam9rlek.h3
-rw-r--r--include/configs/bf533-stamp.h2
-rw-r--r--include/configs/bf537-minotaur.h5
-rw-r--r--include/configs/bf537-srv1.h5
-rw-r--r--include/configs/bf548-ezkit.h7
-rw-r--r--include/configs/canyonlands.h20
-rw-r--r--include/configs/cm-bf548.h7
-rw-r--r--include/configs/cm-bf561.h2
-rw-r--r--include/configs/cmc_pu2.h5
-rw-r--r--include/configs/compactcenter.h437
-rw-r--r--include/configs/csb637.h37
-rw-r--r--include/configs/davinci_schmoogie.h1
-rw-r--r--include/configs/davinci_sffsdr.h1
-rw-r--r--include/configs/delta.h11
-rw-r--r--include/configs/digsy_mtc.h1
-rw-r--r--include/configs/dlvision.h225
-rw-r--r--include/configs/gr_ep2s60.h2
-rw-r--r--include/configs/imx31_litekit.h7
-rw-r--r--include/configs/imx31_phycore.h7
-rw-r--r--include/configs/keymile-common.h17
-rw-r--r--include/configs/kilauea.h13
-rw-r--r--include/configs/km8xx.h2
-rw-r--r--include/configs/kmeter1.h10
-rw-r--r--include/configs/m501sk.h10
-rw-r--r--include/configs/mecp5123.h1
-rw-r--r--include/configs/meesc.h2
-rw-r--r--include/configs/mgcoge.h24
-rw-r--r--include/configs/mimc200.h16
-rw-r--r--include/configs/mp2usb.h7
-rw-r--r--include/configs/mv88f6281gtw_ge.h200
-rw-r--r--include/configs/mx31pdk.h7
-rw-r--r--include/configs/netstar.h2
-rw-r--r--include/configs/nhk8815.h18
-rw-r--r--include/configs/omap2420h4.h36
-rw-r--r--include/configs/omap3_beagle.h7
-rw-r--r--include/configs/omap3_evm.h13
-rw-r--r--include/configs/omap3_overo.h8
-rw-r--r--include/configs/omap3_pandora.h8
-rw-r--r--include/configs/omap3_zoom1.h9
-rw-r--r--include/configs/omap3_zoom2.h8
-rw-r--r--include/configs/pdnb3.h3
-rw-r--r--include/configs/pm9261.h3
-rw-r--r--include/configs/pm9263.h3
-rw-r--r--include/configs/qemu-mips.h2
-rw-r--r--include/configs/quad100hd.h2
-rw-r--r--include/configs/rd6281a.h198
-rw-r--r--include/configs/rsk7203.h7
-rw-r--r--include/configs/sbc2410x.h23
-rw-r--r--include/configs/sbc8349.h4
-rw-r--r--include/configs/sc3.h1
-rw-r--r--include/configs/sheevaplug.h195
-rw-r--r--include/configs/smdk6400.h2
-rw-r--r--include/configs/socrates.h2
-rw-r--r--include/configs/stxxtc.h82
-rw-r--r--include/configs/svm_sc8xx.h4
-rw-r--r--include/configs/vct.h9
-rw-r--r--include/configs/virtlab2.h4
-rw-r--r--include/configs/vme8349.h608
-rw-r--r--include/configs/zylonite.h10
-rw-r--r--include/elf.h10
-rw-r--r--include/environment.h6
-rw-r--r--include/fsl_esdhc.h8
-rw-r--r--include/hwconfig.h69
-rw-r--r--include/i2c.h2
-rw-r--r--include/image.h13
-rw-r--r--include/iomux.h6
-rw-r--r--include/lcd.h22
-rw-r--r--include/libfdt_env.h53
-rw-r--r--include/linux/mtd/nand.h2
-rw-r--r--include/linux/mtd/nand_ids.h60
-rw-r--r--include/linux/mtd/nand_legacy.h196
-rw-r--r--include/lzma/LzmaDec.h (renamed from include/lzma/LzmaDecode.h)10
-rw-r--r--include/lzma/LzmaTools.h2
-rw-r--r--include/lzma/LzmaTypes.h15
-rw-r--r--include/malloc.h5
-rw-r--r--include/mb862xx.h69
-rw-r--r--include/nand.h2
-rw-r--r--include/net.h9
-rw-r--r--include/netdev.h3
-rw-r--r--include/ppc405.h55
-rw-r--r--include/ppc440.h98
-rw-r--r--include/serial.h2
-rw-r--r--include/stdio_dev.h (renamed from include/devices.h)33
-rw-r--r--include/tsi148.h218
-rw-r--r--include/twl4030.h401
-rw-r--r--include/u-boot/md5.h2
217 files changed, 4726 insertions, 3090 deletions
diff --git a/include/ahci.h b/include/ahci.h
index b363ee1..0c6bbbd 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
* Author: Jason Jin<Jason.jin@freescale.com>
* Zhang Wei<wei.zhang@freescale.com>
*
diff --git a/include/asm-arm/arch-kirkwood/gpio.h b/include/asm-arm/arch-kirkwood/gpio.h
new file mode 100644
index 0000000..a79102b
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/gpio.h
@@ -0,0 +1,53 @@
+/*
+ * arch/asm-arm/mach-kirkwood/include/mach/gpio.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/*
+ * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
+ * Removed kernel level irq handling. Took some macros from kernel to
+ * allow build.
+ *
+ * Dieter Kiermaier dk-arm-linux@gmx.de
+ */
+
+#ifndef __KIRKWOOD_GPIO_H
+#define __KIRKWOOD_GPIO_H
+
+/* got from kernel include/linux/kernel.h */
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+/* got from kernel include/linux/bitops.h */
+#define BITS_PER_BYTE 8
+#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+
+#define GPIO_MAX 50
+#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000)
+#define GPIO_OUT(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
+#define GPIO_IO_CONF(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
+#define GPIO_BLINK_EN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
+#define GPIO_IN_POL(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
+#define GPIO_DATA_IN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
+#define GPIO_EDGE_CAUSE(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
+#define GPIO_EDGE_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
+#define GPIO_LEVEL_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
+
+/*
+ * Kirkwood-specific GPIO API
+ */
+
+void kw_gpio_set_valid(unsigned pin, int mode);
+int kw_gpio_is_valid(unsigned pin, int mode);
+int kw_gpio_direction_input(unsigned pin);
+int kw_gpio_direction_output(unsigned pin, int value);
+int kw_gpio_get_value(unsigned pin);
+void kw_gpio_set_value(unsigned pin, int value);
+void kw_gpio_set_blink(unsigned pin, int blink);
+void kw_gpio_set_unused(unsigned pin);
+
+#define GPIO_INPUT_OK (1 << 0)
+#define GPIO_OUTPUT_OK (1 << 1)
+
+#endif
diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h
index 47679dd..2470efb 100644
--- a/include/asm-arm/arch-kirkwood/kirkwood.h
+++ b/include/asm-arm/arch-kirkwood/kirkwood.h
@@ -44,6 +44,7 @@
#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470))
#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
+#define KW_TWSI_BASE (KW_REGISTER(0x11000))
#define KW_UART0_BASE (KW_REGISTER(0x12000))
#define KW_UART1_BASE (KW_REGISTER(0x12100))
#define KW_MPP_BASE (KW_REGISTER(0x10000))
diff --git a/include/asm-arm/arch-nomadik/gpio.h b/include/asm-arm/arch-nomadik/gpio.h
new file mode 100644
index 0000000..1d3c9ce
--- /dev/null
+++ b/include/asm-arm/arch-nomadik/gpio.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2009 Alessandro Rubini
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __NMK_GPIO_H__
+#define __NMK_GPIO_H__
+
+/*
+ * These functions are called from the soft-i2c driver, but
+ * are also used by board files to set output bits.
+ */
+
+enum nmk_af { /* alternate function settings */
+ GPIO_GPIO = 0,
+ GPIO_ALT_A,
+ GPIO_ALT_B,
+ GPIO_ALT_C
+};
+
+extern void nmk_gpio_af(int gpio, int alternate_function);
+extern void nmk_gpio_dir(int gpio, int dir);
+extern void nmk_gpio_set(int gpio, int val);
+extern int nmk_gpio_get(int gpio);
+
+#endif /* __NMK_GPIO_H__ */
diff --git a/include/asm-arm/arch-omap24xx/i2c.h b/include/asm-arm/arch-omap24xx/i2c.h
index 7248950..44db7a2 100644
--- a/include/asm-arm/arch-omap24xx/i2c.h
+++ b/include/asm-arm/arch-omap24xx/i2c.h
@@ -104,4 +104,48 @@
#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
+/* These values were copied from omap3, include/asm-arm/arch-omap3/i2c.h. */
+#define OMAP_I2C_STANDARD 100000
+#define OMAP_I2C_FAST_MODE 400000
+#define OMAP_I2C_HIGH_SPEED 3400000
+
+#define SYSTEM_CLOCK_12 12000000
+#define SYSTEM_CLOCK_13 13000000
+#define SYSTEM_CLOCK_192 19200000
+#define SYSTEM_CLOCK_96 96000000
+
+#ifndef I2C_IP_CLK
+#define I2C_IP_CLK SYSTEM_CLOCK_96
+#endif
+
+#ifndef I2C_INTERNAL_SAMPLING_CLK
+#define I2C_INTERNAL_SAMPLING_CLK 19200000
+#endif
+
+/* These are the trim values for standard and fast speed */
+#ifndef I2C_FASTSPEED_SCLL_TRIM
+#define I2C_FASTSPEED_SCLL_TRIM 6
+#endif
+#ifndef I2C_FASTSPEED_SCLH_TRIM
+#define I2C_FASTSPEED_SCLH_TRIM 6
+#endif
+
+/* These are the trim values for high speed */
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+#endif
+
+#define I2C_PSC_MAX 0x0f
+#define I2C_PSC_MIN 0x00
+
+
#endif
diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch-omap3/i2c.h
index 3937f35..8b339cc 100644
--- a/include/asm-arm/arch-omap3/i2c.h
+++ b/include/asm-arm/arch-omap3/i2c.h
@@ -112,16 +112,72 @@
#define I2C_SCLH_HSSCLH 8
#define I2C_SCLH_HSSCLH_M 0xFF
-#define OMAP_I2C_STANDARD 100
-#define OMAP_I2C_FAST_MODE 400
-#define OMAP_I2C_HIGH_SPEED 3400
+#define OMAP_I2C_STANDARD 100000
+#define OMAP_I2C_FAST_MODE 400000
+#define OMAP_I2C_HIGH_SPEED 3400000
-#define SYSTEM_CLOCK_12 12000
-#define SYSTEM_CLOCK_13 13000
-#define SYSTEM_CLOCK_192 19200
-#define SYSTEM_CLOCK_96 96000
+#define SYSTEM_CLOCK_12 12000000
+#define SYSTEM_CLOCK_13 13000000
+#define SYSTEM_CLOCK_192 19200000
+#define SYSTEM_CLOCK_96 96000000
+/* Use the reference value of 96MHz if not explicitly set by the board */
+#ifndef I2C_IP_CLK
#define I2C_IP_CLK SYSTEM_CLOCK_96
+#endif
+
+/*
+ * The reference minimum clock for high speed is 19.2MHz.
+ * The linux 2.6.30 kernel uses this value.
+ * The reference minimum clock for fast mode is 9.6MHz
+ * The reference minimum clock for standard mode is 4MHz
+ * In TRM, the value of 12MHz is used.
+ */
+#ifndef I2C_INTERNAL_SAMPLING_CLK
+#define I2C_INTERNAL_SAMPLING_CLK 19200000
+#endif
+
+/*
+ * The equation for the low and high time is
+ * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
+ * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
+ *
+ * If the duty cycle is 50%
+ *
+ * tlow = scll + scll_trim = sampling clock / (2 * speed)
+ * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
+ *
+ * In TRM
+ * scll_trim = 7
+ * sclh_trim = 5
+ *
+ * The linux 2.6.30 kernel uses
+ * scll_trim = 6
+ * sclh_trim = 6
+ *
+ * These are the trim values for standard and fast speed
+ */
+#ifndef I2C_FASTSPEED_SCLL_TRIM
+#define I2C_FASTSPEED_SCLL_TRIM 6
+#endif
+#ifndef I2C_FASTSPEED_SCLH_TRIM
+#define I2C_FASTSPEED_SCLH_TRIM 6
+#endif
+
+/* These are the trim values for high speed */
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+#endif
+
#define I2C_PSC_MAX 0x0f
#define I2C_PSC_MIN 0x00
diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h
index 7c11019..fa8f46d 100644
--- a/include/asm-arm/arch-omap3/omap3.h
+++ b/include/asm-arm/arch-omap3/omap3.h
@@ -181,39 +181,4 @@ typedef struct gpio {
#define WIDTH_8BIT 0x0000
#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
-/* I2C power management companion definitions */
-#define PWRMGT_ADDR_ID1 0x48
-#define PWRMGT_ADDR_ID2 0x49
-#define PWRMGT_ADDR_ID3 0x4A
-#define PWRMGT_ADDR_ID4 0x4B
-
-/* I2C ID3 (slave3) register */
-#define LEDEN 0xEE
-
-#define LEDAON (0x1 << 0)
-#define LEDBON (0x1 << 1)
-#define LEDAPWM (0x1 << 4)
-#define LEDBPWM (0x1 << 5)
-
-/* I2C ID4 (slave4) register */
-#define VAUX2_DEV_GRP 0x76
-#define VAUX2_DEDICATED 0x79
-#define VAUX3_DEV_GRP 0x7A
-#define VAUX3_DEDICATED 0x7D
-#define VMMC1_DEV_GRP 0x82
-#define VMMC1_DEDICATED 0x85
-#define VPLL2_DEV_GRP 0x8E
-#define VPLL2_DEDICATED 0x91
-#define VDAC_DEV_GRP 0x96
-#define VDAC_DEDICATED 0x99
-
-#define DEV_GRP_P1 0x20
-#define DEV_GRP_ALL 0xE0
-
-#define VAUX2_VSEL_28 0x09
-#define VAUX3_VSEL_28 0x03
-#define VPLL2_VSEL_18 0x05
-#define VDAC_VSEL_18 0x03
-#define VMMC1_VSEL_30 0x02
-
#endif
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 2a723dc..f34af19 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1217,7 +1217,7 @@ typedef void (*ExcpHndlr) (void) ;
#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3)
-#define GCDR(x) __REG2(0x40300420, ((x) & 0x60) >> 3)
+#define GCDR(x) __REG2(0x40E00420, ((x) & 0x60) >> 3)
/* Multi-funktion Pin Registers, uncomplete, only:
* - GPIO
diff --git a/include/asm-arm/errno.h b/include/asm-arm/errno.h
index 134a8fc..4c82b50 100644
--- a/include/asm-arm/errno.h
+++ b/include/asm-arm/errno.h
@@ -1,138 +1 @@
-#ifndef _ARM_ERRNO_H
-#define _ARM_ERRNO_H
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Arg list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-#define EDEADLOCK 58 /* File locking deadlock error */
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-/* Should never be seen by user programs */
-#define ERESTARTSYS 512
-#define ERESTARTNOINTR 513
-#define ERESTARTNOHAND 514 /* restart if no handler.. */
-#define ENOIOCTLCMD 515 /* No ioctl command */
-
-#define _LAST_ERRNO 515
-
-#endif
+#include <asm-generic/errno.h>
diff --git a/include/asm-arm/unaligned.h b/include/asm-arm/unaligned.h
new file mode 100644
index 0000000..d644df7
--- /dev/null
+++ b/include/asm-arm/unaligned.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_ARM_UNALIGNED_H
+#define _ASM_ARM_UNALIGNED_H
+
+#include <linux/unaligned/access_ok.h>
+#include <linux/unaligned/generic.h>
+
+/*
+ * Select endianness
+ */
+#ifndef __ARMEB__
+#define get_unaligned __get_unaligned_le
+#define put_unaligned __put_unaligned_le
+#else
+#define get_unaligned __get_unaligned_be
+#define put_unaligned __put_unaligned_be
+#endif
+
+#endif /* _ASM_ARM_UNALIGNED_H */
diff --git a/include/asm-avr32/arch-at32ap700x/chip-features.h b/include/asm-avr32/arch-at32ap700x/chip-features.h
index c47107e..40a2476 100644
--- a/include/asm-avr32/arch-at32ap700x/chip-features.h
+++ b/include/asm-avr32/arch-at32ap700x/chip-features.h
@@ -32,4 +32,9 @@
#define AT32AP700x_CHIP_HAS_MACB
#endif
+/* AP7000 and AP7002 have LCD controller, but AP7001 does not */
+#if defined(CONFIG_AT32AP7000) || defined(CONFIG_AT32AP7002)
+#define AT32AP700x_CHIP_HAS_LCDC
+#endif
+
#endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h
index d83e93b..7a0b655 100644
--- a/include/asm-avr32/arch-at32ap700x/clk.h
+++ b/include/asm-avr32/arch-at32ap700x/clk.h
@@ -83,6 +83,12 @@ static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
return get_pba_clk_rate();
}
#endif
+#ifdef AT32AP700x_CHIP_HAS_LCDC
+static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
+{
+ return get_hsb_clk_rate();
+}
+#endif
extern void clk_init(void);
diff --git a/include/asm-avr32/arch-at32ap700x/portmux.h b/include/asm-avr32/arch-at32ap700x/portmux.h
index 96fe70d..1ba52e5 100644
--- a/include/asm-avr32/arch-at32ap700x/portmux.h
+++ b/include/asm-avr32/arch-at32ap700x/portmux.h
@@ -85,5 +85,8 @@ void portmux_enable_mmci(unsigned int slot, unsigned long flags,
void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength);
void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength);
#endif
+#ifdef AT32AP700x_CHIP_HAS_LCDC
+void portmux_enable_lcdc(int pin_config);
+#endif
#endif /* __ASM_AVR32_ARCH_PORTMUX_H__ */
diff --git a/include/asm-avr32/errno.h b/include/asm-avr32/errno.h
index ea3506f..4c82b50 100644
--- a/include/asm-avr32/errno.h
+++ b/include/asm-avr32/errno.h
@@ -1,132 +1 @@
-#ifndef _ASM_AVR32_ERRNO_H
-#define _ASM_AVR32_ERRNO_H
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Argument list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-
-#define EDEADLOCK EDEADLK
-
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-#endif /* _ASM_AVR32_ERRNO_H */
+#include <asm-generic/errno.h>
diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h
index 97a6c61..efbdda9 100644
--- a/include/asm-avr32/global_data.h
+++ b/include/asm-avr32/global_data.h
@@ -42,6 +42,9 @@ typedef struct global_data {
unsigned long env_addr; /* Address of env struct */
unsigned long env_valid; /* Checksum of env valid? */
unsigned long cpu_hz; /* cpu core clock frequency */
+#if defined(CONFIG_LCD)
+ void *fb_base; /* framebuffer address */
+#endif
void **jt; /* jump table */
} gd_t;
diff --git a/include/asm-blackfin/blackfin_local.h b/include/asm-blackfin/blackfin_local.h
index e17d8a2..8ec7928 100644
--- a/include/asm-blackfin/blackfin_local.h
+++ b/include/asm-blackfin/blackfin_local.h
@@ -61,6 +61,9 @@ extern u_long get_sclk(void);
# define bfin_revid() (*pCHIPID >> 28)
+extern bool bfin_os_log_check(void);
+extern void bfin_os_log_dump(void);
+
extern void blackfin_icache_flush_range(const void *, const void *);
extern void blackfin_dcache_flush_range(const void *, const void *);
extern void blackfin_icache_dcache_flush_range(const void *, const void *);
diff --git a/include/asm-blackfin/errno.h b/include/asm-blackfin/errno.h
index 0d2c618..4c82b50 100644
--- a/include/asm-blackfin/errno.h
+++ b/include/asm-blackfin/errno.h
@@ -1,156 +1 @@
-/*
- * U-boot - errno.h Error number defines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _BLACKFIN_ERRNO_H
-#define _BLACKFIN_ERRNO_H
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Arg list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-
-#define EDEADLOCK EDEADLK
-
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-#endif
+#include <asm-generic/errno.h>
diff --git a/include/asm-generic/errno.h b/include/asm-generic/errno.h
new file mode 100644
index 0000000..39dc515
--- /dev/null
+++ b/include/asm-generic/errno.h
@@ -0,0 +1,155 @@
+/*
+ * U-boot - errno.h Error number defines
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _GENERIC_ERRNO_H
+#define _GENERIC_ERRNO_H
+
+#define EPERM 1 /* Operation not permitted */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Argument list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No child processes */
+#define EAGAIN 11 /* Try again */
+#define ENOMEM 12 /* Out of memory */
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define ENOTBLK 15 /* Block device required */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* File table overflow */
+#define EMFILE 24 /* Too many open files */
+#define ENOTTY 25 /* Not a typewriter */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#define EDOM 33 /* Math argument out of domain of func */
+#define ERANGE 34 /* Math result not representable */
+#define EDEADLK 35 /* Resource deadlock would occur */
+#define ENAMETOOLONG 36 /* File name too long */
+#define ENOLCK 37 /* No record locks available */
+#define ENOSYS 38 /* Function not implemented */
+#define ENOTEMPTY 39 /* Directory not empty */
+#define ELOOP 40 /* Too many symbolic links encountered */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#define ENOMSG 42 /* No message of desired type */
+#define EIDRM 43 /* Identifier removed */
+#define ECHRNG 44 /* Channel number out of range */
+#define EL2NSYNC 45 /* Level 2 not synchronized */
+#define EL3HLT 46 /* Level 3 halted */
+#define EL3RST 47 /* Level 3 reset */
+#define ELNRNG 48 /* Link number out of range */
+#define EUNATCH 49 /* Protocol driver not attached */
+#define ENOCSI 50 /* No CSI structure available */
+#define EL2HLT 51 /* Level 2 halted */
+#define EBADE 52 /* Invalid exchange */
+#define EBADR 53 /* Invalid request descriptor */
+#define EXFULL 54 /* Exchange full */
+#define ENOANO 55 /* No anode */
+#define EBADRQC 56 /* Invalid request code */
+#define EBADSLT 57 /* Invalid slot */
+
+#define EDEADLOCK EDEADLK
+
+#define EBFONT 59 /* Bad font file format */
+#define ENOSTR 60 /* Device not a stream */
+#define ENODATA 61 /* No data available */
+#define ETIME 62 /* Timer expired */
+#define ENOSR 63 /* Out of streams resources */
+#define ENONET 64 /* Machine is not on the network */
+#define ENOPKG 65 /* Package not installed */
+#define EREMOTE 66 /* Object is remote */
+#define ENOLINK 67 /* Link has been severed */
+#define EADV 68 /* Advertise error */
+#define ESRMNT 69 /* Srmount error */
+#define ECOMM 70 /* Communication error on send */
+#define EPROTO 71 /* Protocol error */
+#define EMULTIHOP 72 /* Multihop attempted */
+#define EDOTDOT 73 /* RFS specific error */
+#define EBADMSG 74 /* Not a data message */
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#define ENOTUNIQ 76 /* Name not unique on network */
+#define EBADFD 77 /* File descriptor in bad state */
+#define EREMCHG 78 /* Remote address changed */
+#define ELIBACC 79 /* Can not access a needed shared library */
+#define ELIBBAD 80 /* Accessing a corrupted shared library */
+#define ELIBSCN 81 /* .lib section in a.out corrupted */
+#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
+#define ELIBEXEC 83 /* Cannot exec a shared library directly */
+#define EILSEQ 84 /* Illegal byte sequence */
+#define ERESTART 85 /* Interrupted system call should be restarted */
+#define ESTRPIPE 86 /* Streams pipe error */
+#define EUSERS 87 /* Too many users */
+#define ENOTSOCK 88 /* Socket operation on non-socket */
+#define EDESTADDRREQ 89 /* Destination address required */
+#define EMSGSIZE 90 /* Message too long */
+#define EPROTOTYPE 91 /* Protocol wrong type for socket */
+#define ENOPROTOOPT 92 /* Protocol not available */
+#define EPROTONOSUPPORT 93 /* Protocol not supported */
+#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
+#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
+#define EADDRINUSE 98 /* Address already in use */
+#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
+#define ENETDOWN 100 /* Network is down */
+#define ENETUNREACH 101 /* Network is unreachable */
+#define ENETRESET 102 /* Network dropped connection because of reset */
+#define ECONNABORTED 103 /* Software caused connection abort */
+#define ECONNRESET 104 /* Connection reset by peer */
+#define ENOBUFS 105 /* No buffer space available */
+#define EISCONN 106 /* Transport endpoint is already connected */
+#define ENOTCONN 107 /* Transport endpoint is not connected */
+#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS 109 /* Too many references: cannot splice */
+#define ETIMEDOUT 110 /* Connection timed out */
+#define ECONNREFUSED 111 /* Connection refused */
+#define EHOSTDOWN 112 /* Host is down */
+#define EHOSTUNREACH 113 /* No route to host */
+#define EALREADY 114 /* Operation already in progress */
+#define EINPROGRESS 115 /* Operation now in progress */
+#define ESTALE 116 /* Stale NFS file handle */
+#define EUCLEAN 117 /* Structure needs cleaning */
+#define ENOTNAM 118 /* Not a XENIX named type file */
+#define ENAVAIL 119 /* No XENIX semaphores available */
+#define EISNAM 120 /* Is a named type file */
+#define EREMOTEIO 121 /* Remote I/O error */
+#define EDQUOT 122 /* Quota exceeded */
+#define ENOMEDIUM 123 /* No medium found */
+#define EMEDIUMTYPE 124 /* Wrong medium type */
+
+#endif
diff --git a/include/asm-m68k/errno.h b/include/asm-m68k/errno.h
index ff364b8..4c82b50 100644
--- a/include/asm-m68k/errno.h
+++ b/include/asm-m68k/errno.h
@@ -1,138 +1 @@
-#ifndef _PPC_ERRNO_H
-#define _PPC_ERRNO_H
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Arg list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-#define EDEADLOCK 58 /* File locking deadlock error */
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-/* Should never be seen by user programs */
-#define ERESTARTSYS 512
-#define ERESTARTNOINTR 513
-#define ERESTARTNOHAND 514 /* restart if no handler.. */
-#define ENOIOCTLCMD 515 /* No ioctl command */
-
-#define _LAST_ERRNO 515
-
-#endif
+#include <asm-generic/errno.h>
diff --git a/include/asm-microblaze/byteorder.h b/include/asm-microblaze/byteorder.h
index 51cacb0..a4a75b7 100644
--- a/include/asm-microblaze/byteorder.h
+++ b/include/asm-microblaze/byteorder.h
@@ -27,7 +27,9 @@
I think this is a symptom of a bug in mb-gcc. JW 20040303
*/
-static __inline__ __const__ __u16 ___arch__swab16 (__u16 half_word)
+
+
+static __inline__ __u16 ___arch__swab16 (__u16 half_word)
{
/* 32 bit temp to cast result, forcing clearing of high word */
__u32 temp;
diff --git a/include/asm-microblaze/errno.h b/include/asm-microblaze/errno.h
new file mode 100644
index 0000000..4c82b50
--- /dev/null
+++ b/include/asm-microblaze/errno.h
@@ -0,0 +1 @@
+#include <asm-generic/errno.h>
diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h
index ca143c7..c9ba805 100644
--- a/include/asm-ppc/config.h
+++ b/include/asm-ppc/config.h
@@ -29,10 +29,11 @@
#endif
#endif
-#ifndef CONFIG_FSL_DMA
-#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
- !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \
- (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
+/* Check if boards need to enable FSL DMA engine for SDRAM init */
+#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
+#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
+ ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
+ !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
#define CONFIG_FSL_DMA
#endif
#endif
diff --git a/include/asm-ppc/errno.h b/include/asm-ppc/errno.h
index ff364b8..4c82b50 100644
--- a/include/asm-ppc/errno.h
+++ b/include/asm-ppc/errno.h
@@ -1,138 +1 @@
-#ifndef _PPC_ERRNO_H
-#define _PPC_ERRNO_H
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Arg list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-#define EDEADLOCK 58 /* File locking deadlock error */
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-/* Should never be seen by user programs */
-#define ERESTARTSYS 512
-#define ERESTARTNOINTR 513
-#define ERESTARTNOHAND 514 /* restart if no handler.. */
-#define ENOIOCTLCMD 515 /* No ioctl command */
-
-#define _LAST_ERRNO 515
-
-#endif
+#include <asm-generic/errno.h>
diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h
index fc05dc0..23e29b1 100644
--- a/include/asm-ppc/gpio.h
+++ b/include/asm-ppc/gpio.h
@@ -24,6 +24,8 @@
#ifndef __ASM_PPC_GPIO_H
#define __ASM_PPC_GPIO_H
+#include <asm/types.h>
+
/* 4xx PPC's have 2 GPIO controllers */
#if defined(CONFIG_405EZ) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
@@ -34,6 +36,28 @@
#define GPIO_GROUP_MAX 1
#endif
+/* GPIO controller */
+struct ppc4xx_gpio {
+ u32 or; /* Output Control */
+ u32 tcr; /* Tri-State Control */
+ u32 osl; /* Output Select 16..31 */
+ u32 osh; /* Output Select 0..15 */
+ u32 tsl; /* Tri-State Select 16..31 */
+ u32 tsh; /* Tri-State Select 0..15 */
+ u32 odr; /* Open Drain */
+ u32 ir; /* Input */
+ u32 rr1; /* Receive Register 1 */
+ u32 rr2; /* Receive Register 2 */
+ u32 rr3; /* Receive Register 3 */
+ u32 reserved;
+ u32 is1l; /* Input Select 1 16..31 */
+ u32 is1h; /* Input Select 1 0..15 */
+ u32 is2l; /* Input Select 2 16..31 */
+ u32 is2h; /* Input Select 2 0..15 */
+ u32 is3l; /* Input Select 3 16..31 */
+ u32 is3h; /* Input Select 3 0..15 */
+};
+
/* Offsets */
#define GPIOx_OR 0x00 /* GPIO Output Register */
#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 7c6a151..c60a7d2 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -650,6 +650,12 @@ typedef struct immap {
u8 res7[0xC0000];
} immap_t;
+#ifdef CONFIG_HAS_FSL_MPH_USB
+#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x22000 /* use the MPH controller */
+#else
+#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 /* use the DR controller */
+#endif
+
#elif defined(CONFIG_MPC8313)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
@@ -856,7 +862,10 @@ typedef struct immap {
#define CONFIG_SYS_MPC83xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
-#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000
+
+#ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
+#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000
+#endif
#define CONFIG_SYS_MPC83xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
#endif /* __IMMAP_83xx__ */
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index a839834..fdfc654 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -114,9 +114,9 @@ typedef struct ccsr_ddr {
uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
- uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */
+ uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */
uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
- uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
+ uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
diff --git a/include/console.h b/include/asm-ppc/ppc4xx_config.h
index bc8b139..49acb60 100644
--- a/include/console.h
+++ b/include/asm-ppc/ppc4xx_config.h
@@ -1,6 +1,9 @@
/*
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2009
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -19,18 +22,21 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
*/
-#ifndef _CONSOLE_H_
-#define _CONSOLE_H_
+#ifndef __PPC4xx_CONFIG_H
+#define __PPC4xx_CONFIG_H
-#include <devices.h>
+#include <common.h>
-/*
-** VARIABLES
-*/
+struct ppc4xx_config {
+ char label[16];
+ char description[64];
+ u8 val[CONFIG_4xx_CONFIG_BLOCKSIZE];
+};
-extern device_t *stdio_devices[] ;
-extern char *stdio_names[MAX_FILES] ;
+extern struct ppc4xx_config ppc4xx_config_val[];
+extern int ppc4xx_config_count;
-#endif
+#endif /* __PPC4xx_CONFIG_H */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 65546ad..2841104 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -96,6 +96,10 @@
#define CONFIG_BOOKE
#endif
+#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
+#ifdef CONFIG_BOOKE
+#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */
+#endif
#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
#define SPRN_CTR 0x009 /* Count Register */
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
@@ -166,6 +170,9 @@
#define SPRN_DBSR 0x3F0 /* Debug Status Register */
#else
#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
+#ifdef CONFIG_BOOKE
+#define SPRN_DBDR 0x3f3 /* Debug Data Register */
+#endif
#define SPRN_DBSR 0x130 /* Book E Debug Status Register */
#define DBSR_IC 0x08000000 /* Book E Instruction Completion */
#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
@@ -173,6 +180,10 @@
#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
#define DCCR_NOCACHE 0 /* Noncacheable */
#define DCCR_CACHE 1 /* Cacheable */
+#ifndef CONFIG_BOOKE
+#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */
+#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */
+#endif
#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
#define DCWR_COPY 0 /* Copy-back */
@@ -184,7 +195,20 @@
#endif /* CONFIG_BOOKE */
#define SPRN_DEC 0x016 /* Decrement Register */
#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */
+#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */
+#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */
+#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */
+#endif
#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */
+#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */
+#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */
+#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */
+#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */
+#endif
#define SPRN_EAR 0x11A /* External Address Register */
#ifndef CONFIG_BOOKE
#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
@@ -269,16 +293,34 @@
#define ICCR_NOCACHE 0 /* Noncacheable */
#define ICCR_CACHE 1 /* Cacheable */
#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */
+#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */
+#endif
#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */
+#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */
+#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */
+#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */
+#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */
+#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */
+#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */
+#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */
+#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */
+#endif
#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
#define SPRN_LR 0x008 /* Link Register */
#define SPRN_MBAR 0x137 /* System memory base address */
#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
+#ifdef CONFIG_BOOKE
+#define SPRN_MMUCR 0x3b2 /* MMU Control Register */
+#endif
#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
@@ -297,6 +339,9 @@
#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
#define SPRN_PVR 0x11F /* Processor Version Register */
#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_RSTCFG 0x39b /* Reset Configuration */
+#endif
#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
@@ -315,6 +360,7 @@
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
+
#ifdef CONFIG_BOOKE
#define SPRN_SVR 0x3FF /* System Version Register */
#else
@@ -837,8 +883,10 @@
#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */
#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
+#define PVR_460EX_RB 0x130218A4 /* 460EX rev B with and without Sec Eng*/
#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */
+#define PVR_460GT_RB 0x130218A5 /* 460GT rev B with and without Sec Eng*/
#define PVR_460SX_RA 0x13541800 /* 460SX rev A */
#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
#define PVR_460GX_RA 0x13541802 /* 460GX rev A */
diff --git a/include/asm-sh/errno.h b/include/asm-sh/errno.h
index 0d2c618..4c82b50 100644
--- a/include/asm-sh/errno.h
+++ b/include/asm-sh/errno.h
@@ -1,156 +1 @@
-/*
- * U-boot - errno.h Error number defines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _BLACKFIN_ERRNO_H
-#define _BLACKFIN_ERRNO_H
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Arg list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-
-#define EDEADLOCK EDEADLK
-
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-#endif
+#include <asm-generic/errno.h>
diff --git a/include/asm-sparc/errno.h b/include/asm-sparc/errno.h
index 3a74f6f..4c82b50 100644
--- a/include/asm-sparc/errno.h
+++ b/include/asm-sparc/errno.h
@@ -1,162 +1 @@
-/* SPARC errno definitions, taken from asm-ppc/errno.h
- *
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPARC_ERRNO_H__
-#define __SPARC_ERRNO_H__
-
-#define EPERM 1 /* Operation not permitted */
-#define ENOENT 2 /* No such file or directory */
-#define ESRCH 3 /* No such process */
-#define EINTR 4 /* Interrupted system call */
-#define EIO 5 /* I/O error */
-#define ENXIO 6 /* No such device or address */
-#define E2BIG 7 /* Arg list too long */
-#define ENOEXEC 8 /* Exec format error */
-#define EBADF 9 /* Bad file number */
-#define ECHILD 10 /* No child processes */
-#define EAGAIN 11 /* Try again */
-#define ENOMEM 12 /* Out of memory */
-#define EACCES 13 /* Permission denied */
-#define EFAULT 14 /* Bad address */
-#define ENOTBLK 15 /* Block device required */
-#define EBUSY 16 /* Device or resource busy */
-#define EEXIST 17 /* File exists */
-#define EXDEV 18 /* Cross-device link */
-#define ENODEV 19 /* No such device */
-#define ENOTDIR 20 /* Not a directory */
-#define EISDIR 21 /* Is a directory */
-#define EINVAL 22 /* Invalid argument */
-#define ENFILE 23 /* File table overflow */
-#define EMFILE 24 /* Too many open files */
-#define ENOTTY 25 /* Not a typewriter */
-#define ETXTBSY 26 /* Text file busy */
-#define EFBIG 27 /* File too large */
-#define ENOSPC 28 /* No space left on device */
-#define ESPIPE 29 /* Illegal seek */
-#define EROFS 30 /* Read-only file system */
-#define EMLINK 31 /* Too many links */
-#define EPIPE 32 /* Broken pipe */
-#define EDOM 33 /* Math argument out of domain of func */
-#define ERANGE 34 /* Math result not representable */
-#define EDEADLK 35 /* Resource deadlock would occur */
-#define ENAMETOOLONG 36 /* File name too long */
-#define ENOLCK 37 /* No record locks available */
-#define ENOSYS 38 /* Function not implemented */
-#define ENOTEMPTY 39 /* Directory not empty */
-#define ELOOP 40 /* Too many symbolic links encountered */
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#define ENOMSG 42 /* No message of desired type */
-#define EIDRM 43 /* Identifier removed */
-#define ECHRNG 44 /* Channel number out of range */
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#define EL3HLT 46 /* Level 3 halted */
-#define EL3RST 47 /* Level 3 reset */
-#define ELNRNG 48 /* Link number out of range */
-#define EUNATCH 49 /* Protocol driver not attached */
-#define ENOCSI 50 /* No CSI structure available */
-#define EL2HLT 51 /* Level 2 halted */
-#define EBADE 52 /* Invalid exchange */
-#define EBADR 53 /* Invalid request descriptor */
-#define EXFULL 54 /* Exchange full */
-#define ENOANO 55 /* No anode */
-#define EBADRQC 56 /* Invalid request code */
-#define EBADSLT 57 /* Invalid slot */
-#define EDEADLOCK 58 /* File locking deadlock error */
-#define EBFONT 59 /* Bad font file format */
-#define ENOSTR 60 /* Device not a stream */
-#define ENODATA 61 /* No data available */
-#define ETIME 62 /* Timer expired */
-#define ENOSR 63 /* Out of streams resources */
-#define ENONET 64 /* Machine is not on the network */
-#define ENOPKG 65 /* Package not installed */
-#define EREMOTE 66 /* Object is remote */
-#define ENOLINK 67 /* Link has been severed */
-#define EADV 68 /* Advertise error */
-#define ESRMNT 69 /* Srmount error */
-#define ECOMM 70 /* Communication error on send */
-#define EPROTO 71 /* Protocol error */
-#define EMULTIHOP 72 /* Multihop attempted */
-#define EDOTDOT 73 /* RFS specific error */
-#define EBADMSG 74 /* Not a data message */
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#define ENOTUNIQ 76 /* Name not unique on network */
-#define EBADFD 77 /* File descriptor in bad state */
-#define EREMCHG 78 /* Remote address changed */
-#define ELIBACC 79 /* Can not access a needed shared library */
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#define EILSEQ 84 /* Illegal byte sequence */
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#define ESTRPIPE 86 /* Streams pipe error */
-#define EUSERS 87 /* Too many users */
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#define EDESTADDRREQ 89 /* Destination address required */
-#define EMSGSIZE 90 /* Message too long */
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#define ENOPROTOOPT 92 /* Protocol not available */
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#define EADDRINUSE 98 /* Address already in use */
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#define ENETDOWN 100 /* Network is down */
-#define ENETUNREACH 101 /* Network is unreachable */
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#define ECONNABORTED 103 /* Software caused connection abort */
-#define ECONNRESET 104 /* Connection reset by peer */
-#define ENOBUFS 105 /* No buffer space available */
-#define EISCONN 106 /* Transport endpoint is already connected */
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#define ETIMEDOUT 110 /* Connection timed out */
-#define ECONNREFUSED 111 /* Connection refused */
-#define EHOSTDOWN 112 /* Host is down */
-#define EHOSTUNREACH 113 /* No route to host */
-#define EALREADY 114 /* Operation already in progress */
-#define EINPROGRESS 115 /* Operation now in progress */
-#define ESTALE 116 /* Stale NFS file handle */
-#define EUCLEAN 117 /* Structure needs cleaning */
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#define EISNAM 120 /* Is a named type file */
-#define EREMOTEIO 121 /* Remote I/O error */
-#define EDQUOT 122 /* Quota exceeded */
-
-#define ENOMEDIUM 123 /* No medium found */
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-
-/* Should never be seen by user programs */
-#define ERESTARTSYS 512
-#define ERESTARTNOINTR 513
-#define ERESTARTNOHAND 514 /* restart if no handler.. */
-#define ENOIOCTLCMD 515 /* No ioctl command */
-
-#define _LAST_ERRNO 515
-
-#endif
+#include <asm-generic/errno.h>
diff --git a/include/bus_vcxk.h b/include/bus_vcxk.h
new file mode 100644
index 0000000..88af53f
--- /dev/null
+++ b/include/bus_vcxk.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2005-2009
+ * Jens Scharsig @ BuS Elektronik GmbH & Co. KG, <esw@bus-elektronik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BUS_VCXK_H_
+#define __BUS_VCXK_H_
+
+extern int vcxk_init(unsigned long width, unsigned long height);
+extern void vcxk_setpixel(int x, int y, unsigned long color);
+extern int vcxk_acknowledge_wait(void);
+extern int vcxk_request(void);
+extern void vcxk_loadimage(ulong source);
+extern int vcxk_display_bitmap(ulong addr, int x, int y);
+extern void vcxk_setbrightness(unsigned int side, short brightness);
+extern int video_display_bitmap(ulong addr, int x, int y);
+
+#endif
diff --git a/include/common.h b/include/common.h
index a6c7c07..a6922fd 100644
--- a/include/common.h
+++ b/include/common.h
@@ -27,6 +27,8 @@
#undef _LINUX_CONFIG_H
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
+#ifndef __ASSEMBLY__ /* put C only stuff in this section */
+
typedef unsigned char uchar;
typedef volatile unsigned long vu_long;
typedef volatile unsigned short vu_short;
@@ -636,11 +638,9 @@ int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */
/*
* STDIO based functions (can always be used)
*/
-
/* serial stuff */
void serial_printf (const char *fmt, ...)
__attribute__ ((format (__printf__, 1, 2)));
-
/* stdin */
int getc(void);
int tstc(void);
@@ -660,7 +660,6 @@ void vprintf(const char *fmt, va_list args);
/*
* FILE based functions (can only be used AFTER relocation!)
*/
-
#define stdin 0
#define stdout 1
#define stderr 2
@@ -690,6 +689,21 @@ int pcmcia_init (void);
*/
void show_boot_progress(int val);
+/* Multicore arch functions */
+#ifdef CONFIG_MP
+int cpu_status(int nr);
+int cpu_reset(int nr);
+int cpu_release(int nr, int argc, char *argv[]);
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+/* Put only stuff here that the assembler can digest */
+
+#ifdef CONFIG_POST
+#define CONFIG_HAS_POST
+#endif
+
#ifdef CONFIG_INIT_CRITICAL
#error CONFIG_INIT_CRITICAL is deprecated!
#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
@@ -697,6 +711,7 @@ void show_boot_progress(int val);
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define ROUND(a,b) (((a) + (b)) & ~((b) - 1))
#define DIV_ROUND(n,d) (((n) + ((d)/2)) / (d))
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
@@ -704,15 +719,4 @@ void show_boot_progress(int val);
#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
-/* Multicore arch functions */
-#ifdef CONFIG_MP
-int cpu_status(int nr);
-int cpu_reset(int nr);
-int cpu_release(int nr, int argc, char *argv[]);
-#endif
-
-#ifdef CONFIG_POST
-#define CONFIG_HAS_POST
-#endif
-
#endif /* __COMMON_H_ */
diff --git a/include/compiler.h b/include/compiler.h
new file mode 100644
index 0000000..272fd3c
--- /dev/null
+++ b/include/compiler.h
@@ -0,0 +1,125 @@
+/*
+ * Keep all the ugly #ifdef for system stuff here
+ */
+
+#ifndef __COMPILER_H__
+#define __COMPILER_H__
+
+#include <stddef.h>
+
+#ifdef USE_HOSTCC
+
+#if defined(__BEOS__) || \
+ defined(__NetBSD__) || \
+ defined(__FreeBSD__) || \
+ defined(__sun__) || \
+ defined(__APPLE__)
+# include <inttypes.h>
+#elif defined(__linux__) || defined(__WIN32__) || defined(__MINGW32__)
+# include <stdint.h>
+#endif
+
+#include <errno.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+extern int errno;
+
+#if !defined(__WIN32__) && !defined(__MINGW32__)
+# include <sys/mman.h>
+#endif
+
+/* Not all systems (like Windows) has this define, and yes
+ * we do replace/emulate mmap() on those systems ...
+ */
+#ifndef MAP_FAILED
+# define MAP_FAILED ((void *)-1)
+#endif
+
+#include <fcntl.h>
+#ifndef O_BINARY /* should be define'd on __WIN32__ */
+#define O_BINARY 0
+#endif
+
+#ifdef __linux__
+# include <endian.h>
+# include <byteswap.h>
+#elif defined(__MACH__)
+# include <machine/endian.h>
+typedef unsigned long ulong;
+typedef unsigned int uint;
+#endif
+
+typedef uint8_t __u8;
+typedef uint16_t __u16;
+typedef uint32_t __u32;
+
+#define uswap_16(x) \
+ ((((x) & 0xff00) >> 8) | \
+ (((x) & 0x00ff) << 8))
+#define uswap_32(x) \
+ ((((x) & 0xff000000) >> 24) | \
+ (((x) & 0x00ff0000) >> 8) | \
+ (((x) & 0x0000ff00) << 8) | \
+ (((x) & 0x000000ff) << 24))
+#define _uswap_64(x, sfx) \
+ ((((x) & 0xff00000000000000##sfx) >> 56) | \
+ (((x) & 0x00ff000000000000##sfx) >> 40) | \
+ (((x) & 0x0000ff0000000000##sfx) >> 24) | \
+ (((x) & 0x000000ff00000000##sfx) >> 8) | \
+ (((x) & 0x00000000ff000000##sfx) << 8) | \
+ (((x) & 0x0000000000ff0000##sfx) << 24) | \
+ (((x) & 0x000000000000ff00##sfx) << 40) | \
+ (((x) & 0x00000000000000ff##sfx) << 56))
+#if defined(__GNUC__)
+# define uswap_64(x) _uswap_64(x, ull)
+#else
+# define uswap_64(x) _uswap_64(x, )
+#endif
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+# define cpu_to_le16(x) (x)
+# define cpu_to_le32(x) (x)
+# define cpu_to_le64(x) (x)
+# define le16_to_cpu(x) (x)
+# define le32_to_cpu(x) (x)
+# define le64_to_cpu(x) (x)
+# define cpu_to_be16(x) uswap_16(x)
+# define cpu_to_be32(x) uswap_32(x)
+# define cpu_to_be64(x) uswap_64(x)
+# define be16_to_cpu(x) uswap_16(x)
+# define be32_to_cpu(x) uswap_32(x)
+# define be64_to_cpu(x) uswap_64(x)
+#else
+# define cpu_to_le16(x) uswap_16(x)
+# define cpu_to_le32(x) uswap_32(x)
+# define cpu_to_le64(x) uswap_64(x)
+# define le16_to_cpu(x) uswap_16(x)
+# define le32_to_cpu(x) uswap_32(x)
+# define le64_to_cpu(x) uswap_64(x)
+# define cpu_to_be16(x) (x)
+# define cpu_to_be32(x) (x)
+# define cpu_to_be64(x) (x)
+# define be16_to_cpu(x) (x)
+# define be32_to_cpu(x) (x)
+# define be64_to_cpu(x) (x)
+#endif
+
+#else /* !USE_HOSTCC */
+
+#include <linux/string.h>
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+/* Types for `void *' pointers. */
+#if __WORDSIZE == 64
+typedef unsigned long int uintptr_t;
+#else
+typedef unsigned int uintptr_t;
+#endif
+
+#endif
+
+#endif
diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h
index 0376e44..a5d87a6 100644
--- a/include/config_cmd_default.h
+++ b/include/config_cmd_default.h
@@ -20,14 +20,13 @@
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_ECHO /* echo arguments */
-#define CONFIG_CMD_SAVEENV /* saveenv */
-#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_IMI /* iminfo */
+#define CONFIG_CMD_ITEST /* Integer (and string) test */
#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_IMLS /* List all found images */
#endif
-#define CONFIG_CMD_ITEST /* Integer (and string) test */
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_LOADS /* loads */
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
@@ -35,6 +34,7 @@
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_RUN /* run command in env variable */
+#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
#define CONFIG_CMD_SOURCE /* "source" command support */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 2ee4f80..694a87b 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -157,8 +157,10 @@
#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-#define CONFIG_SYS_NAND_QUIET 1
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CONFIG_SYS_NAND_QUIET 1
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/*-----------------------------------------------------------------------
* PCI stuff
diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h
index fe04f27..0dfb23b 100644
--- a/include/configs/AmigaOneG3SE.h
+++ b/include/configs/AmigaOneG3SE.h
@@ -363,7 +363,7 @@
#define CONFIG_USB_UHCI 1
#define CONFIG_USB_STORAGE 1
#define CONFIG_USB_KEYBOARD 1
-#define CONFIG_SYS_DEVICE_DEREGISTER 1 /* needed by CONFIG_USB_KEYBOARD */
+#define CONFIG_SYS_STDIO_DEREGISTER 1 /* needed by CONFIG_USB_KEYBOARD */
/*
* Autoboot stuff
diff --git a/include/configs/BMW.h b/include/configs/BMW.h
index 24ffb00..98f6396 100644
--- a/include/configs/BMW.h
+++ b/include/configs/BMW.h
@@ -81,13 +81,9 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_ELF
-/* CONFIG_CMD_DOC required legacy NAND support */
-#define CONFIG_NAND_LEGACY
-
#if 0
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index 39f41e6..229a513 100644
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -209,16 +209,8 @@
/* For CATcenter there is only NAND on the module */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
#define NAND_NO_RB
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index ae8494d..2384925 100644
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -165,6 +165,8 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index cf21fd9..6d76d9f 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -146,15 +146,6 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*-----------------------------------------------------------------------
- * Disk-On-Chip configuration
- */
-
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
-/*-----------------------------------------------------------------------
* Miscellaneous configuration options
*/
@@ -179,7 +170,6 @@
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index 489378a..83b010c 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -182,7 +182,6 @@
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
@@ -190,9 +189,6 @@
#define CONFIG_CMD_PCI
#endif
-
-#define CONFIG_NAND_LEGACY
-
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index a13db7c..a0b27a8 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -1,7 +1,7 @@
/*
* Configuation settings for the BuS EB+MCF-EV123 boards.
*
- * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -25,16 +25,15 @@
#ifndef _CONFIG_EB_MCF_EV123_H_
#define _CONFIG_EB_MCF_EV123_H_
-#define CONFIG_EB_MCF_EV123
-
#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
-/*
- * High Level Configuration Options (easy to change)
- */
+/*----------------------------------------------------------------------*
+ * High Level Configuration Options (easy to change) *
+ *----------------------------------------------------------------------*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5282 /* define processor type */
+#define CONFIG_EB_MCF_EV123
#define CONFIG_MISC_INIT_R
@@ -43,29 +42,33 @@
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
+#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
#define CONFIG_BOOTCOMMAND "printenv"
-/* Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
- */
+/*----------------------------------------------------------------------*
+ * Options *
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_BOOT_RETRY_TIME -1
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_SPLASH_SCREEN
+
+/*----------------------------------------------------------------------*
+ * Configuration for environment *
+ * Environment is in the second sector of the first 256k of flash *
+ *----------------------------------------------------------------------*/
+
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_ADDR 0xF003C000 /* End of 256K */
#define CONFIG_ENV_SECT_SIZE 0x4000
#define CONFIG_ENV_IS_IN_FLASH 1
-/*
-#define CONFIG_ENV_IS_EMBEDDED 1
-#define CONFIG_ENV_ADDR_REDUND 0xF0018000
-#define CONFIG_ENV_SECT_SIZE_REDUND 0x4000
-*/
#else
#define CONFIG_ENV_ADDR 0xFFE04000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH 1
#endif
-
/*
* BOOTP options
*/
@@ -74,7 +77,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
@@ -86,50 +88,20 @@
#define CONFIG_MCFTMR
-#define CONFIG_MCFFEC
-#ifdef CONFIG_MCFFEC
-# define CONFIG_NET_MULTI 1
-# define CONFIG_MII 1
-# define CONFIG_MII_INIT 1
-# define CONFIG_SYS_DISCOVER_PHY
-# define CONFIG_SYS_RX_ETH_BUFFER 8
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CONFIG_SYS_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-#ifdef CONFIG_MCFFEC
-# define CONFIG_ETHADDR 00:CF:52:82:EB:01
-# define CONFIG_IPADDR 192.162.1.2
-# define CONFIG_NETMASK 255.255.255.0
-# define CONFIG_SERVERIP 192.162.1.1
-# define CONFIG_GATEWAYIP 192.162.1.1
-# define CONFIG_OVERWRITE_ETHADDR_ONCE
-#endif /* CONFIG_MCFFEC */
#define CONFIG_BOOTDELAY 5
-#define CONFIG_SYS_PROMPT "\nEV123 U-Boot> "
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "\nEV123 U-Boot> "
+#define CONFIG_SYS_LONGHELP 1
#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR 0x20000
@@ -138,29 +110,53 @@
/*#define CONFIG_SYS_DRAM_TEST 1 */
#undef CONFIG_SYS_DRAM_TEST
-/* Clock and PLL Configuration */
+/*----------------------------------------------------------------------*
+ * Clock and PLL Configuration *
+ *----------------------------------------------------------------------*/
#define CONFIG_SYS_HZ 10000000
#define CONFIG_SYS_CLK 58982400 /* 9,8304MHz * 6 */
/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
-#define CONFIG_SYS_MFD 0x01 /* PLL Multiplication Factor Devider */
-#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
+#define CONFIG_SYS_MFD 0x01 /* PLL Multiplication Factor Devider */
+#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
-/*
+/*----------------------------------------------------------------------*
+ * Network *
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_MCFFEC
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1
+#define CONFIG_MII_INIT 1
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_RX_ETH_BUFFER 8
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#define CONFIG_SYS_FEC0_PINMUX 0
+#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
+#define MCFFEC_TOUT_LOOP 50000
+
+#define CONFIG_ETHADDR 00:CF:52:82:EB:01
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/*-------------------------------------------------------------------------
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
- */
-#define CONFIG_SYS_MBAR 0x40000000
+ *-----------------------------------------------------------------------*/
+
+#define CONFIG_SYS_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ *-----------------------------------------------------------------------*/
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
+#define CONFIG_SYS_INIT_RAM_END 0x10000
+#define CONFIG_SYS_GBL_DATA_SIZE 64
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
@@ -169,18 +165,11 @@
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE1 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE1 16 /* SDRAM size in MB */
-
-/*
-#define CONFIG_SYS_SDRAM_BASE0 CONFIG_SYS_SDRAM_BASE1+CONFIG_SYS_SDRAM_SIZE1*1024*1024
-#define CONFIG_SYS_SDRAM_SIZE0 16 */ /* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_SIZE1 16 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE1
#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE1
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
-#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */
@@ -199,11 +188,16 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
+
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
+#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
+
#define CONFIG_SYS_MAX_FLASH_SECT 35
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
@@ -246,16 +240,40 @@
#define CONFIG_SYS_PCDAT 0x0000000
#define CONFIG_SYS_PEHLPAR 0xC0
-#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
+#define CONFIG_SYS_PUAPAR 0x0F
#define CONFIG_SYS_DDRUA 0x05
#define CONFIG_SYS_PJPAR 0xFF
/*-----------------------------------------------------------------------
- * CCM configuration
+ * VIDEO configuration
*/
-#define CONFIG_SYS_CCM_SIZ 0
+#define CONFIG_VIDEO
-/*---------------------------------------------------------------------*/
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_VCXK 1
+
+#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
+#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
+#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS3_BASE
+#define CONFIG_SYS_VCXK_AUTODETECT 1
+
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
+
+#define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
+
+#define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
+
+#define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
+#define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
+#define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
+
+#endif /* CONFIG_VIDEO */
#endif /* _CONFIG_M5282EVB_H */
/*---------------------------------------------------------------------*/
diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h
index aceecd8..1190656 100644
--- a/include/configs/FPS850L.h
+++ b/include/configs/FPS850L.h
@@ -36,9 +36,9 @@
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_FPS850L 1 /* ...on a FingerPrint Sensor */
-#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h
index 4a61d7c..73bcccc 100644
--- a/include/configs/FPS860L.h
+++ b/include/configs/FPS860L.h
@@ -36,9 +36,9 @@
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */
-#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
index bf9fd82..6819c3e 100644
--- a/include/configs/G2000.h
+++ b/include/configs/G2000.h
@@ -196,32 +196,12 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CONFIG_SYS_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#endif
/*-----------------------------------------------------------------------
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index 8f18ab2..12f879a 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -244,10 +244,6 @@
#define CONFIG_CMD_MII
#define CONFIG_CMD_BEDBUG
-#if !defined(CONFIG_SC)
- #define CONFIG_CMD_DOC
-#endif
-
#ifdef CONFIG_POST
#define CONFIG_CMD_DIAG
#endif
@@ -279,9 +275,6 @@
#define CONFIG_FPGA_VIRTEX2
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-
-#define CONFIG_NAND_LEGACY
-
/*
* Verbose help from command monitor.
*/
@@ -738,16 +731,6 @@
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
- * Disk On Chip (millenium) configuration
- */
-#if !defined(CONFIG_SC)
-#define CONFIG_SYS_MAX_DOC_DEVICE 1
-#undef CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-#undef CONFIG_SYS_DOC_PASSIVE_PROBE
-#endif
-
-/*
* FEC interrupt assignment
*/
#define FEC_INTERRUPT SIU_LEVEL1
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 9233523..1a2266f 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -219,6 +219,8 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h
index 6c8e81f..88e1946 100644
--- a/include/configs/HMI10.h
+++ b/include/configs/HMI10.h
@@ -45,8 +45,8 @@
#endif
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index ea502d4..518d94d 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -160,6 +160,8 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index 51e012c..4c4af05 100644
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -265,6 +265,8 @@
#define CONFIG_SYS_NAND0_BASE 0xE1000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#endif /* CONFIG_CMD_NAND */
/*-----------------------------------------------------------------------
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 8315cfe..7ac9342 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -84,12 +84,9 @@
#if !defined(CONFIG_MIP405T)
#define CONFIG_CMD_USB
- #define CONFIG_CMD_DOC
#endif
-#define CONFIG_NAND_LEGACY
-
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/**************************************************************
@@ -384,13 +381,6 @@
#define CONFIG_ISO_PARTITION /* Experimental */
/************************************************************
- * Disk-On-Chip configuration
- ************************************************************/
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-#define CONFIG_SYS_DOC_SHORT_TIMEOUT
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-/************************************************************
* Keyboard support
************************************************************/
#undef CONFIG_ISA_KEYBOARD
@@ -415,7 +405,7 @@
#define CONFIG_USB_STORAGE
/* Enable needed helper functions */
-#define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */
+#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
#endif
/************************************************************
* Debug support
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 2308568..d9aa60b 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -36,7 +36,6 @@
#define CONFIG_MPC8313ERDB 1
#define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI
#define CONFIG_MISC_INIT_R
@@ -211,7 +210,7 @@
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
@@ -236,6 +235,7 @@
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index e03a107..d5e62e3 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -72,6 +72,7 @@
#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_HWCONFIG
/*
* IMMR new address
@@ -226,6 +227,7 @@
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
@@ -330,8 +332,7 @@
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
#define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
-#define CONFIG_83XX_GENERIC_PCIE 1
+#define CONFIG_PCIE
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 24f37e7..907965d 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -18,7 +18,6 @@
#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
#define CONFIG_PCI 1
-#define CONFIG_83XX_GENERIC_PCI 1
/*
* System Clock Setup
@@ -156,7 +155,7 @@
#endif
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 669577e..4e23a11 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -144,7 +144,7 @@
#endif
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
@@ -315,15 +315,15 @@
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
@@ -334,6 +334,7 @@
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -500,14 +501,14 @@
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else
@@ -536,9 +537,7 @@
/*
* Environment Configuration
- */
-
-#define CONFIG_ENV_OVERWRITE
+ */ #define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index ea5fbff..3cf59ef 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -38,9 +38,6 @@
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
-#undef CONFIG_PCI
-#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-
#define PCI_66M
#ifdef PCI_66M
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
@@ -201,7 +198,7 @@
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
@@ -374,7 +371,6 @@
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_83XX_GENERIC_PCI
#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index d4d3256..fd5ad70 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -79,6 +79,7 @@
#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */
#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
+#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
#endif
#define CONFIG_PCI
@@ -155,6 +156,25 @@
#endif
+#ifdef CONFIG_SYS_USB_HOST
+/*
+ * Support USB
+ */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+
+/* Current USB implementation supports the only USB controller,
+ * so we have to choose between the MPH or the DR ones */
+#if 1
+#define CONFIG_HAS_FSL_MPH_USB
+#else
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+#endif
+
/*
* DDR Setup
*/
@@ -288,7 +308,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
@@ -456,9 +476,11 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SDRAM
-#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114)
+#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
+ || defined(CONFIG_USB_STORAGE)
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
+ #define CONFIG_SUPPORT_VFAT
#endif
#ifdef CONFIG_COMPACT_FLASH
@@ -467,6 +489,9 @@ boards, we say we have two, but don't display a message if we find only one. */
#ifdef CONFIG_SATA_SIL3114
#define CONFIG_CMD_SATA
+#endif
+
+#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
#define CONFIG_CMD_EXT2
#endif
@@ -560,12 +585,14 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
+#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
/*
* System IO Config
*/
#define CONFIG_SYS_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */
-#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
+#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) /* USB DR as device + USB MPH as host */
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 3497ba0..fe6ec48 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -170,7 +170,7 @@
#endif
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
@@ -350,15 +350,15 @@
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
@@ -369,6 +369,7 @@
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -539,14 +540,14 @@
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index f584435..68d68bb 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -212,6 +212,7 @@
#define CONFIG_NAND_FSL_UPM 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */
@@ -276,7 +277,6 @@
* Addresses are mapped 1-1.
*/
#define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI 1
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 4befcab..a2a2aad 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -111,6 +111,7 @@
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_HWCONFIG
/*
* IMMR new address
@@ -380,8 +381,7 @@
#ifndef __ASSEMBLY__
extern int board_pci_host_broken(void);
#endif
-#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
-#define CONFIG_83XX_GENERIC_PCIE 1
+#define CONFIG_PCIE
#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 2b7d629..b637f73 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -34,6 +34,7 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
/*
* On-board devices
@@ -48,8 +49,7 @@
#define CONFIG_83XX_PCICLK 66666667 /* in HZ */
#else
#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#define CONFIG_83XX_GENERIC_PCI 1
-#define CONFIG_83XX_GENERIC_PCIE 1
+#define CONFIG_PCIE
#endif
#ifndef CONFIG_SYS_CLK_FREQ
@@ -228,7 +228,7 @@
#undef CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
@@ -342,6 +342,9 @@
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+#define CONFIG_SYS_64BIT_STRTOUL 1
+#define CONFIG_SYS_64BIT_VSPRINTF 1
+
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
@@ -510,6 +513,18 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_MMC 1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 7085d28..0aaab4a 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -45,6 +45,7 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -218,6 +219,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
+#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
+#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
+#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
+#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
+#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
+#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
+#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
@@ -563,10 +571,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 5253611..4af599b 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -418,10 +418,10 @@
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 813512c..a8f206f 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -440,10 +440,10 @@ extern unsigned long get_clock_freq(void);
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 1d8fecf..2de3139 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -44,6 +44,7 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -192,6 +193,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
+#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
+#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
@@ -458,10 +461,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 7089ac7..bebb9e9 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -500,10 +500,10 @@ extern unsigned long get_clock_freq(void);
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index ef95118..94952dc 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -438,10 +438,10 @@ extern unsigned long get_clock_freq(void);
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 761a370..c1a1a6d 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -452,10 +452,10 @@
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index ac34047..7b8c6c7 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -456,10 +456,10 @@ extern unsigned long get_clock_freq(void);
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 27044f7..32e747e 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -471,10 +471,10 @@ extern unsigned long get_clock_freq(void);
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
/* Initial Memory map for Linux*/
/*
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 235be51..64f5c4b 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -237,6 +237,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
+#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
+#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
+#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
+#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
+#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
@@ -607,10 +612,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 2f40ef4..a3b5c7c 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -317,7 +317,7 @@
#define CONFIG_PCI_OHCI 1
#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_USB_KEYBOARD 1
-#define CONFIG_SYS_DEVICE_DEREGISTER
+#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL 1
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 60ce0f3..bf2e359 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -224,6 +224,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
+#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
+#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
@@ -391,7 +393,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_PCI_OHCI 1
#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_USB_KEYBOARD 1
-#define CONFIG_SYS_DEVICE_DEREGISTER
+#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL 1
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h
index edbc701..867e8e0 100644
--- a/include/configs/MVBC_P.h
+++ b/include/configs/MVBC_P.h
@@ -68,9 +68,9 @@
#define MV_VCI mvBlueCOUGAR-P
#define MV_FPGA_DATA 0xff860000
#define MV_FPGA_SIZE 0x0003c886
-#define MV_KERNEL_ADDR 0xffc00000
+#define MV_KERNEL_ADDR 0xffd00000
#define MV_INITRD_ADDR 0xff900000
-#define MV_INITRD_LENGTH 0x00300000
+#define MV_INITRD_LENGTH 0x00400000
#define MV_SCRATCH_ADDR 0x00000000
#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
#define MV_SOURCE_ADDR 0xff840000
@@ -105,6 +105,7 @@
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_I2C
#undef CONFIG_WATCHDOG
@@ -182,6 +183,7 @@
"propdev_debug=0\0" \
"gevss_debug=0\0" \
"watchdog=1\0" \
+ "sensor_cnt=1\0" \
""
#undef XMK_STR
@@ -249,6 +251,14 @@
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_MODULE 1
+#define CONFIG_SYS_I2C_SPEED 86000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/*
* Ethernet configuration
*/
#define CONFIG_NET_MULTI
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index ac8cb57..aa91805 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -40,7 +40,6 @@
#define CONFIG_SYS_IMMR 0xE0000000
#define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI
#define CONFIG_PCI_SKIP_HOST_BRIDGE
#define CONFIG_HARD_I2C
#define CONFIG_TSEC_ENET
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
index 796938a..76ca916 100644
--- a/include/configs/NETPHONE.h
+++ b/include/configs/NETPHONE.h
@@ -120,7 +120,6 @@
*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
@@ -497,95 +496,9 @@
#define DSP_BASE 0xF1000000
#define NAND_BASE 0xF1010000
-/****************************************************************/
-
-/* NAND */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_NAND_BASE NAND_BASE
-#define CONFIG_MTD_NAND_ECC_JFFS2
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_MTD_NAND_UNSAFE
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define SECTORSIZE 512
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
-#define NAND_DISABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
- } while(0)
-
-#define NAND_ENABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
- } while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
- } while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
- } while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
- } while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
- } while(0)
-
-#if CONFIG_NETPHONE_VERSION == 1
-#define NAND_WAIT_READY(nand) \
- do { \
- int _tries = 0; \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
- if (++_tries > 100000) \
- break; \
- } while (0)
-#elif CONFIG_NETPHONE_VERSION == 2
-#define NAND_WAIT_READY(nand) \
- do { \
- int _tries = 0; \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
- if (++_tries > 100000) \
- break; \
- } while (0)
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define READ_NAND(adr) \
- ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
/*****************************************************************************/
#define CONFIG_SYS_DIRECT_FLASH_TFTP
-#define CONFIG_SYS_DIRECT_NAND_TFTP
/*****************************************************************************/
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 724e807..4f9f9fe 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -134,7 +134,6 @@
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_PING
@@ -616,105 +615,6 @@
#define ER_BASE 0xF1020000
#define DUMMY_BASE 0xF1FF0000
-/****************************************************************/
-
-/* NAND */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_NAND_BASE NAND_BASE
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_MTD_NAND_UNSAFE
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/* #define NAND_NO_RB */
-
-#define SECTORSIZE 512
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */
-#define NAND_DISABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 5)); \
- } while(0)
-
-#define NAND_ENABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \
- } while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \
- } while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 3)); \
- } while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \
- } while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 4)); \
- } while(0)
-
-#ifndef NAND_NO_RB
-#define NAND_WAIT_READY(nand) \
- do { \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \
- WATCHDOG_RESET(); \
- } \
- } while (0)
-#else
-#define NAND_WAIT_READY(nand) udelay(12)
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define READ_NAND(adr) \
- ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
-#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nand0"
-#define CONFIG_JFFS2_PART_SIZE 0x00100000
-#define CONFIG_JFFS2_PART_OFFSET 0x00200000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nand0=netta-nand"
-#define MTDPARTS_DEFAULT "mtdparts=netta-nand:1m@2m(jffs2)"
-*/
-
/*****************************************************************************/
#define CONFIG_SYS_DIRECT_FLASH_TFTP
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
index a14b2dd..d060cb7 100644
--- a/include/configs/NETTA2.h
+++ b/include/configs/NETTA2.h
@@ -121,7 +121,6 @@
*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
@@ -498,95 +497,9 @@
#define DSP_BASE 0xF1000000
#define NAND_BASE 0xF1010000
-/****************************************************************/
-
-/* NAND */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_NAND_BASE NAND_BASE
-#define CONFIG_MTD_NAND_ECC_JFFS2
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_MTD_NAND_UNSAFE
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define SECTORSIZE 512
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
-#define NAND_DISABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
- } while(0)
-
-#define NAND_ENABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
- } while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
- } while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
- } while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
- } while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
- } while(0)
-
-#if CONFIG_NETTA2_VERSION == 1
-#define NAND_WAIT_READY(nand) \
- do { \
- int _tries = 0; \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
- if (++_tries > 100000) \
- break; \
- } while (0)
-#elif CONFIG_NETTA2_VERSION == 2
-#define NAND_WAIT_READY(nand) \
- do { \
- int _tries = 0; \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
- if (++_tries > 100000) \
- break; \
- } while (0)
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define READ_NAND(adr) \
- ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
/*****************************************************************************/
#define CONFIG_SYS_DIRECT_FLASH_TFTP
-#define CONFIG_SYS_DIRECT_NAND_TFTP
/*****************************************************************************/
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
index f97bdcb..a18b480 100644
--- a/include/configs/NETVIA.h
+++ b/include/configs/NETVIA.h
@@ -107,7 +107,7 @@
#define CONFIG_CMD_PING
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-#define CONFIG_CMD_NAND
+/* #define CONFIG_CMD_NAND */ /* disabled */
#endif
@@ -393,80 +393,6 @@
#endif
-/*****************************************************************************/
-
-#define CONFIG_NAND_LEGACY
-
-#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-
-/* NAND */
-#define CONFIG_SYS_NAND_BASE NAND_BASE
-#define CONFIG_MTD_NAND_ECC_JFFS2
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define SECTORSIZE 512
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#define NAND_DISABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= 0x0040; \
- } while(0)
-
-#define NAND_ENABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \
- } while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \
- } while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= 0x0100; \
- } while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \
- } while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= 0x0080; \
- } while(0)
-
-#define NAND_WAIT_READY(nand) \
- do { \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \
- ; \
- } while (0)
-
-#define WRITE_NAND_COMMAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define READ_NAND(adr) \
- ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
-#endif
/*****************************************************************************/
diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h
index 6abd3f1..5dd72ff 100644
--- a/include/configs/NSCU.h
+++ b/include/configs/NSCU.h
@@ -38,6 +38,8 @@
#define CONFIG_NSCU 1
#define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 676f013..5c2c5cb 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -282,6 +282,11 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
#define PIXIS_VWATCH 0x24 /* Watchdog Register */
#define PIXIS_LED 0x25 /* LED Register */
+#define PIXIS_SW(x) 0x20 + (x - 1) * 2
+#define PIXIS_EN(x) 0x21 + (x - 1) * 2
+#define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */
+#define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */
+
/* old pixis referenced names */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
@@ -412,7 +417,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_SLAVE 0x7F
@@ -637,10 +641,10 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h
index 5951d00..99a8c4a 100644
--- a/include/configs/PCIPPC2.h
+++ b/include/configs/PCIPPC2.h
@@ -75,7 +75,6 @@
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
@@ -84,8 +83,6 @@
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-#define CONFIG_NAND_LEGACY
-
/*
* Miscellaneous configurable options
*/
@@ -251,15 +248,6 @@
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*-----------------------------------------------------------------------
- * Disk-On-Chip configuration
- */
-
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
-/*-----------------------------------------------------------------------
RTC m48t59
*/
#define CONFIG_RTC_MK48T59
diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h
index a683a8f..66e6d24 100644
--- a/include/configs/PCIPPC6.h
+++ b/include/configs/PCIPPC6.h
@@ -75,7 +75,6 @@
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
@@ -86,8 +85,6 @@
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-#define CONFIG_NAND_LEGACY
-
/*
* Miscellaneous configurable options
*/
@@ -253,15 +250,6 @@
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*-----------------------------------------------------------------------
- * Disk-On-Chip configuration
- */
-
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
-/*-----------------------------------------------------------------------
RTC m48t59
*/
#define CONFIG_RTC_MK48T59
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index e214d70..962b29e 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -71,14 +71,10 @@
#define CONFIG_CMD_USB
#define CONFIG_CMD_MII
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_BSP
-
-#define CONFIG_NAND_LEGACY
-
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/**************************************************************
@@ -361,7 +357,7 @@
#define CONFIG_USB_STORAGE
/* Enable needed helper functions */
-#define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */
+#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
/************************************************************
* Debug support
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 7f2337b..2e41526 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -183,6 +183,8 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*
* PCI stuff
*/
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index ff73ef9..f9687d2 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -86,12 +86,6 @@
#define CONFIG_USB_STORAGE
#endif
-#if !defined(CONFIG_BOOT_ROM)
-/* DoC requires legacy NAND for now */
-#define CONFIG_NAND_LEGACY
-#endif
-
-
/*
* BOOTP options
*/
@@ -117,10 +111,6 @@
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
-#if !defined(CONFIG_BOOT_ROM)
-#define CONFIG_CMD_DOC
-#endif
-
#if defined(CONFIG_MPC5200)
#define CONFIG_CMD_PCI
#endif
@@ -186,15 +176,6 @@
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-/*
- * Disk-On-Chip configuration
- */
-
-#define CONFIG_SYS_DOC_SHORT_TIMEOUT
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
#define CONFIG_SYS_DOC_BASE 0xE0000000
#define CONFIG_SYS_DOC_SIZE 0x00100000
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index b58f529..636bd26 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -169,7 +169,6 @@
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
@@ -179,19 +178,6 @@
#define CONFIG_CMD_PCI
#endif
-
-#define CONFIG_NAND_LEGACY
-
-/*
- * Disk-On-Chip configuration
- */
-
-#define CONFIG_SYS_DOC_SHORT_TIMEOUT
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/PM828.h b/include/configs/PM828.h
index 96c86f7..9d620af 100644
--- a/include/configs/PM828.h
+++ b/include/configs/PM828.h
@@ -169,7 +169,6 @@
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
@@ -179,18 +178,6 @@
#define CONFIG_CMD_PCI
#endif
-
-/*
- * Disk-On-Chip configuration
- */
-#define CONFIG_NAND_LEGACY
-
-#define CONFIG_SYS_DOC_SHORT_TIMEOUT
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
new file mode 100644
index 0000000..5232745
--- /dev/null
+++ b/include/configs/PMC405DE.h
@@ -0,0 +1,378 @@
+/*
+ * (C) Copyright 2009
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP 1 /* This is a PPC405 CPU */
+#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+
+#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+
+#undef CONFIG_BOOTARGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT /* enable preboot variable */
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address */
+#define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */
+
+#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+#define CONFIG_PRAM 0
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+
+#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
+
+#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
+
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK
+#define CONFIG_SYS_BASE_BAUD 691200
+#define CONFIG_UART1_CONSOLE
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * PCI stuff
+ */
+#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
+#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+/*
+ * PCI identification
+ */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
+#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
+#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
+#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
+#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
+
+#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
+
+#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */
+#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */
+#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_FLASH_BASE 0xfe000000
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
+
+/*
+ * Environment in EEPROM setup
+ */
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_OFFSET 0x100
+#define CONFIG_ENV_SIZE 0x700
+
+/*
+ * I2C EEPROM (24W16) for environment
+ */
+#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
+ /* 16 byte page write mode using*/
+ /* last 4 bits of the address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_WREN 1
+
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20
+
+/*
+ * RTC
+ */
+#define CONFIG_RTC_RX8025
+
+/*
+ * External Bus Controller (EBC) Setup
+ * (max. 55MHZ EBC clock)
+ */
+/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP 0x03017200
+#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000)
+
+/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_CPLD_BASE 0xef000000
+#define CONFIG_SYS_EBC_PB1AP 0x00800000
+#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
+/* inside SDRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
+/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes res. for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
+} \
+}
+
+#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */
+#define CONFIG_SYS_GPIO_HWREV_SHIFT 27
+#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */
+#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */
+#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */
+#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */
+#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */
+#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */
+#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */
+#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#undef CONFIG_SYS_FCPU333MHZ
+#define CONFIG_SYS_FCPU266MHZ
+#undef CONFIG_SYS_FCPU133MHZ
+
+#if defined(CONFIG_SYS_FCPU333MHZ)
+/*
+ * CPU: 333MHz
+ * PLB/SDRAM/MAL: 111MHz
+ * OPB: 55MHz
+ * EBC: 55MHz
+ * PCI: 55MHz (111MHz on M66EN=1)
+ */
+#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+#endif
+
+#if defined(CONFIG_SYS_FCPU266MHZ)
+/*
+ * CPU: 266MHz
+ * PLB/SDRAM/MAL: 133MHz
+ * OPB: 66MHz
+ * EBC: 44MHz
+ * PCI: 44MHz (66MHz on M66EN=1)
+ */
+#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#endif
+
+#if defined(CONFIG_SYS_FCPU133MHZ)
+/*
+ * CPU: 133MHz
+ * PLB/SDRAM/MAL: 133MHz
+ * OPB: 66MHz
+ * EBC: 44MHz
+ * PCI: 44MHz (66MHz on M66EN=1)
+ */
+#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \
+ PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 16baf8c..6fba0ca 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -210,6 +210,9 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*
* nand device 1 on dave (PPChameleonEVB) needs more time,
* so we just introduce additional wait in nand_wait(),
@@ -309,32 +312,6 @@
} \
} while(0)
-#if 0
-#define SECTORSIZE 512
-#define NAND_NO_RB
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#ifdef NAND_NO_RB
-/* constant delay (see also tR in the datasheet) */
-#define NAND_WAIT_READY(nand) do { \
- udelay(12); \
-} while (0)
-#else
-/* use the R/B pin */
-/* TBD */
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-#endif
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
index f36244d..00ac6cf 100644
--- a/include/configs/RBC823.h
+++ b/include/configs/RBC823.h
@@ -114,7 +114,6 @@
#define CONFIG_CMD_CDP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
@@ -329,14 +328,6 @@
#endif
-/************************************************************
- * Disk-On-Chip configuration
- ************************************************************/
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
-#define CONFIG_SYS_DOC_SHORT_TIMEOUT
-#define CONFIG_SYS_DOC_SUPPORT_2000
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
-
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index 72fe115..b847ce8 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -37,7 +37,6 @@
#define CONFIG_MPC8313 1
#define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI
#define CONFIG_MISC_INIT_R
@@ -131,6 +130,7 @@
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
diff --git a/include/configs/SM850.h b/include/configs/SM850.h
index 4c469e3..7266f9a 100644
--- a/include/configs/SM850.h
+++ b/include/configs/SM850.h
@@ -38,15 +38,11 @@
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_SM850 1 /*...on a MPC850 Service Module */
-#undef CONFIG_8xx_CONS_SMC1 /* SMC1 not usable because Ethernet on SCC3 */
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
index cac04b4..8ee8cbf 100644
--- a/include/configs/SXNI855T.h
+++ b/include/configs/SXNI855T.h
@@ -163,75 +163,8 @@
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_DATE
-
-#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition */
-#undef CONFIG_CMD_MTDPARTS
-
-/*
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0x00780000
-#define CONFIG_JFFS2_PART_OFFSET 0x00080000
-*/
-
-#define CONFIG_JFFS2_DEV "nand0"
-#define CONFIG_JFFS2_PART_SIZE 0x00200000
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=sixnet-0,nand0=sixnet-nand"
-#define MTDPARTS_DEFAULT "mtdparts=sixnet-0:7680k@512k();sixnet-nand:2m(jffs2-nand)"
-*/
-
-/* NAND flash support */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_MTD_NAND_ECC_JFFS2
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-/* DFBUSY is available on Port C, bit 12; 0 if busy */
-#define NAND_WAIT_READY(nand) \
- while (!(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & 0x0008));
-#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr))
-#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr))
-#define WRITE_NAND(d, adr) \
- do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0)
-#define READ_NAND(adr) (*(volatile uint8_t *)(adr))
-#define CLE_LO 0x01 /* 0 selects CLE mode (CLE high) */
-#define ALE_LO 0x02 /* 0 selects ALE mode (ALE high) */
-#define CE_LO 0x04 /* 1 selects chip (CE low) */
-#define nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0)
-#define NAND_DISABLE_CE(nand) \
- nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO)
-#define NAND_ENABLE_CE(nand) \
- nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO)
-#define NAND_CTL_CLRALE(nandptr) \
- nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
-#define NAND_CTL_SETALE(nandptr) \
- nand_setcr((nandptr) + 1, CE_LO | CLE_LO)
-#define NAND_CTL_CLRCLE(nandptr) \
- nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
-#define NAND_CTL_SETCLE(nandptr) \
- nand_setcr((nandptr) + 1, CE_LO | ALE_LO)
-
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/TK885D.h b/include/configs/TK885D.h
index 14ff62c..1e6d9ce 100644
--- a/include/configs/TK885D.h
+++ b/include/configs/TK885D.h
@@ -48,7 +48,8 @@
/* 'cpuclk' variable with valid value) */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 1f816f3..966beae 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -43,8 +43,8 @@
#endif
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 42dcbfc..cfa693d 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -41,8 +41,8 @@
#endif
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
index 9cac696..6c462af 100644
--- a/include/configs/TQM8272.h
+++ b/include/configs/TQM8272.h
@@ -439,6 +439,8 @@
WRITE_NAND(d, addr); \
} while(0)
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#endif /* CONFIG_CMD_NAND */
#define CONFIG_PCI
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index efade69..492bdcc 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -250,9 +250,12 @@ extern int tqm834x_num_flash_banks;
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
/* PCI1 host bridge */
-#define CONFIG_SYS_PCI1_MEM_BASE 0xc0000000
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
@@ -418,10 +421,10 @@ extern int tqm834x_num_flash_banks;
#ifdef CONFIG_PCI
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
#else
#define CONFIG_SYS_IBAT3L (0)
#define CONFIG_SYS_IBAT3U (0)
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 290e211..dc0498e 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -37,8 +37,8 @@
#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index 2170df5..cdabc53 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -37,8 +37,8 @@
#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index 3d7dc42..1255928 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -37,9 +37,8 @@
#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index 35cfa08..584d40b 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -37,9 +37,8 @@
#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 6f13c63..1fbf4bf 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -351,8 +351,6 @@
/* NAND FLASH */
#ifdef CONFIG_NAND
-#undef CONFIG_NAND_LEGACY
-
#define CONFIG_NAND_FSL_UPM 1
#define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */
@@ -374,6 +372,8 @@
#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#endif /* CONFIG_NAND */
/*
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index 4ac485d..a772a27 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -37,9 +37,8 @@
#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 39da0bb..7c34786 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -37,9 +37,8 @@
#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index 1f79b17..75d2dac 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -40,9 +40,8 @@
#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index 86d5b01..0c7aacd 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -40,9 +40,8 @@
#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index 04f538c..071afd4 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -51,7 +51,8 @@
#endif
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index 4c80bad..d435819 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -47,7 +47,8 @@
/* 'cpuclk' variable with valid value) */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index de3092d..6051480 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -129,7 +129,7 @@
#define CONFIG_DOS_PARTITION 1
/* Enable needed helper functions */
-#define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */
+#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
/************************************************************
* RTC
@@ -246,42 +246,4 @@
#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
-/*-----------------------------------------------------------------------
- * NAND flash settings
- */
-#if defined(CONFIG_CMD_NAND)
-
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#define NAND_WAIT_READY(nand) NF_WaitRB()
-
-#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
-#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
-
-
-#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
-#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
-#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
-#define WRITE_NAND(d, adr) NF_Write(d)
-#define READ_NAND(adr) NF_Read()
-/* the following functions are NOP's because S3C24X0 handles this in hardware */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1
-#define CONFIG_MTD_NAND_ECC_JFFS2 1
-
-#endif
-
#endif /* __CONFIG_H */
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index 38a1d0d..17397e8 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -169,6 +169,8 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index 5c281a1..dbfa1aa 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -157,6 +157,8 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
diff --git a/include/configs/XPEDITE1000.h b/include/configs/XPEDITE1000.h
new file mode 100644
index 0000000..658e947
--- /dev/null
+++ b/include/configs/XPEDITE1000.h
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * config for XPedite1000 from XES Inc.
+ * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
+ * (C) Copyright 2003 Sandburst Corporation
+ * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_XPEDITE1000 1
+#define CONFIG_SYS_BOARD_NAME "XPedite1000"
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_440 1
+#define CONFIG_440GX 1 /* 440 GX */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+/*
+ * DDR config
+ */
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */
+#define CONFIG_VERY_BIG_RAM 1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
+#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
+#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
+#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x0400000
+#define CONFIG_SYS_MEMTEST_END 0x0C00000
+
+/* POST support */
+#define CONFIG_POST (CONFIG_SYS_POST_RTC | \
+ CONFIG_SYS_POST_I2C)
+
+/*
+ * LED support
+ */
+#define USR_LED0 0x00000080
+#define USR_LED1 0x00000100
+#define USR_LED2 0x00000200
+#define USR_LED3 0x00000400
+
+#ifndef __ASSEMBLY__
+extern unsigned long in32(unsigned int);
+extern void out32(unsigned int, unsigned long);
+
+#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0))
+#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1))
+#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2))
+#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3))
+
+#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0))
+#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1))
+#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2))
+#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
+#endif
+
+/*
+ * Use internal SRAM for initial stack
+ */
+#define CONFIG_SYS_TEMP_STACK_OCM 1
+#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 3
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 }
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST /* MirrorBit flashes are optional */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7f
+#define CONFIG_I2C_MULTI_BUS
+
+/* I2C EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C RTC: STMicro M41T00 */
+#define CONFIG_RTC_M41T11 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+
+/*
+ * PCI
+ */
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */
+
+/*
+ * Networking options
+ */
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_ETHPRIME "ppc_4xx_eth2"
+#define CONFIG_PHY_ADDR 4 /* PHY address phy0 not populated */
+#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */
+#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
+#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */
+#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SNTP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
+#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_PREBOOT /* enable preboot variable */
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
+#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE 0x8000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff U-Boot (512 KB)
+ * fff40000 - fff7ffff U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff FDT (256KB)
+ * ffc00000 - ffefffff OS image (3MB)
+ * ff000000 - ffbfffff OS Use/Filesystem (12MB)
+ */
+
+#define CONFIG_UBOOT_ENV_ADDR MK_STR(TEXT_BASE)
+#define CONFIG_FDT_ENV_ADDR MK_STR(0xfff00000)
+#define CONFIG_OS_ENV_ADDR MK_STR(0xffc00000)
+
+#define CONFIG_PROG_UBOOT \
+ "$download_cmd $loadaddr $ubootfile; " \
+ "if test $? -eq 0; then " \
+ "protect off "CONFIG_UBOOT_ENV_ADDR" +80000; " \
+ "erase "CONFIG_UBOOT_ENV_ADDR" +80000; " \
+ "cp.w $loadaddr "CONFIG_UBOOT_ENV_ADDR" 40000; " \
+ "protect on "CONFIG_UBOOT_ENV_ADDR" +80000; " \
+ "cmp.b $loadaddr "CONFIG_UBOOT_ENV_ADDR" 80000; " \
+ "if test $? -ne 0; then " \
+ "echo PROGRAM FAILED; " \
+ "else; " \
+ "echo PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_BOOT_OS_NET \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "if test -n $fdtaddr; then " \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "bootm $osaddr - $fdtaddr; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi; " \
+ "else; " \
+ "bootm $osaddr; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_OS \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_OS_ENV_ADDR" +$filesize; " \
+ "cp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \
+ "cmp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo OS PROGRAM FAILED; " \
+ "else; " \
+ "echo OS PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_FDT \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_FDT_ENV_ADDR" +$filesize;" \
+ "cp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \
+ "cmp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo FDT PROGRAM FAILED; " \
+ "else; " \
+ "echo FDT PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=yes\0" \
+ "download_cmd=tftp\0" \
+ "console_args=console=ttyS0,115200\0" \
+ "root_args=root=/dev/nfs rw\0" \
+ "misc_args=ip=on\0" \
+ "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+ "bootfile=/home/user/file\0" \
+ "osfile=/home/user/uImage-XPedite1000\0" \
+ "fdtfile=/home/user/xpedite1000.dtb\0" \
+ "ubootfile=/home/user/u-boot.bin\0" \
+ "fdtaddr=c00000\0" \
+ "osaddr=0x1000000\0" \
+ "loadaddr=0x1000000\0" \
+ "prog_uboot="CONFIG_PROG_UBOOT"\0" \
+ "prog_os="CONFIG_PROG_OS"\0" \
+ "prog_fdt="CONFIG_PROG_FDT"\0" \
+ "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
+ "bootcmd_flash=run set_bootargs; " \
+ "bootm "CONFIG_OS_ENV_ADDR" - "CONFIG_FDT_ENV_ADDR"\0" \
+ "bootcmd=run bootcmd_flash\0"
+#endif /* __CONFIG_H */
diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h
deleted file mode 100644
index 74e55c9..0000000
--- a/include/configs/XPEDITE1K.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * config for XPedite1000 from XES Inc.
- * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
- * (C) Copyright 2003 Sandburst Corporation
- * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_440 1
-#define CONFIG_440GX 1 /* 440 GX */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#define CONFIG_MISC_INIT_R
-#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time! */
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_RTC | \
- CONFIG_SYS_POST_I2C)
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* start of monitor */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
-#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
-#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
-
-#define USR_LED0 0x00000080
-#define USR_LED1 0x00000100
-#define USR_LED2 0x00000200
-#define USR_LED3 0x00000400
-
-#ifndef __ASSEMBLY__
-extern unsigned long in32(unsigned int);
-extern void out32(unsigned int, unsigned long);
-
-#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0))
-#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1))
-#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2))
-#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3))
-
-#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0))
-#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1))
-#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2))
-#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
-#endif
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-/* TBS: Xpedite 1000 has STMicro M41T00 via IIC */
-#define CONFIG_RTC_M41T11 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */
-#define CONFIG_VERY_BIG_RAM 1
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7f
-#define CONFIG_SYS_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} /* Don't probe these addrs */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_SIZE 0x100 /* Size of Environment vars */
-#define CONFIG_ENV_OFFSET 0x100
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* this is actually the second page of the eeprom */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_BOOTARGS "root=/dev/hda1 "
-#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
-#define CONFIG_BOOTDELAY 5 /* disable autoboot */
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address phy0 not populated */
-#define CONFIG_PHY1_ADDR 1 /* PHY address phy1 not populated */
-#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */
-#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */
-#define CONFIG_NET_MULTI 1
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
-#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_FAT
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-#endif /* __CONFIG_H */
diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h
index 2553293..8be9fa0 100644
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/XPEDITE5170.h
@@ -254,7 +254,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
/* PEX8518 slave I2C interface */
#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
@@ -580,6 +579,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
* Boot Flags
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index 89ab692..deda208 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -129,6 +129,7 @@
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
{0xfbf40000, 0xc0000} }
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
@@ -369,6 +370,7 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
* Boot Flags
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 536e063..acb62ad 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -124,6 +124,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
*/
#define CONFIG_SYS_NAND_BASE 0xef800000
#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
+#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
+ CONFIG_SYS_NAND_BASE2}
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
+#define CONFIG_NAND_FSL_ELBC
/*
* NOR flash configuration
@@ -137,6 +143,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
{0xf7f40000, 0xc0000} }
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
@@ -374,16 +381,17 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SNTP
/*
@@ -412,6 +420,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
* Boot Flags
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 9ffd86b..b710107 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -265,6 +265,8 @@
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h
index c5134a2..74677d8 100644
--- a/include/configs/afeb9260.h
+++ b/include/configs/afeb9260.h
@@ -106,6 +106,8 @@
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* NOR flash - no real flash on this board */
@@ -159,7 +161,6 @@
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 3b733c0..a2b7ee8 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -137,10 +137,11 @@
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the 40x Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
* Internal Definitions
@@ -214,9 +215,9 @@
" console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0" \
CONFIG_ADDMISC \
"initrd_high=30000000\0" \
- "kernel_addr_r=400000\0" \
- "fdt_addr_r=800000\0" \
- "ramdisk_addr_r=C00000\0" \
+ "kernel_addr_r=1000000\0" \
+ "fdt_addr_r=1800000\0" \
+ "ramdisk_addr_r=1900000\0" \
"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h
index 6f58a05..70dd47e 100644
--- a/include/configs/ap325rxa.h
+++ b/include/configs/ap325rxa.h
@@ -53,9 +53,10 @@
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9118 */
-#define CONFIG_DRIVER_SMC911X 1
-#define CONFIG_DRIVER_SMC911X_32_BIT 1
-#define CONFIG_DRIVER_SMC911X_BASE 0xB6080000
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_32_BIT 1
+#define CONFIG_SMC911X_BASE 0xB6080000
/* MEMORY */
#define AP325RXA_SDRAM_BASE (0x88000000)
diff --git a/include/configs/apollon.h b/include/configs/apollon.h
index fa5a7a9..575f60e 100644
--- a/include/configs/apollon.h
+++ b/include/configs/apollon.h
@@ -256,6 +256,8 @@
#define CONFIG_ENV_IS_IN_ONENAND 1
#define CONFIG_ENV_ADDR 0x00020000
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#ifdef CONFIG_SYS_USE_UBI
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "onenand0=onenand"
diff --git a/include/configs/aria.h b/include/configs/aria.h
index e7e238d..4211113 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -376,7 +376,6 @@
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SPEED 100000
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index 526cd60..0ef3554 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -123,7 +123,6 @@
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
-#endif
/* NAND flash */
#ifdef CONFIG_CMD_NAND
@@ -132,6 +131,9 @@
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#endif
+
/* Ethernet */
#define CONFIG_MACB 1
#define CONFIG_RMII 1
@@ -201,7 +203,6 @@
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 56128c1..590c69a 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -45,11 +45,6 @@
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
@@ -117,38 +112,8 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-
-#define CONFIG_NAND_LEGACY
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
-#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
-#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
-#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
-
-#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-/* the following are NOP's in our implementation */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index c898c73..b4f075e 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -56,11 +56,6 @@
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
@@ -311,7 +306,6 @@ struct bd_info_ext {
*/
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 1828c63..6cee593 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -122,6 +122,8 @@
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* NOR flash - no real flash on this board */
@@ -205,7 +207,6 @@
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 6d24023..3d108ab 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -132,6 +132,8 @@
#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* NOR flash - no real flash on this board */
@@ -223,7 +225,6 @@
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 00f3114..32f3f62 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -266,6 +266,8 @@
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
@@ -333,7 +335,6 @@
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 572c45b..4b46c31 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -118,6 +118,7 @@
/* NOR flash, if populated */
#ifndef CONFIG_CMD_NAND
#define CONFIG_SYS_NO_FLASH 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#else
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
@@ -140,6 +141,8 @@
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
@@ -209,7 +212,6 @@
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index c466823..9167304 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -118,6 +118,8 @@
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet - not present */
@@ -168,7 +170,6 @@
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index c03561c..4be2a5c 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -36,7 +36,7 @@
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
+#define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
/*
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
index 23c2d33..463b7d0 100644
--- a/include/configs/bf537-minotaur.h
+++ b/include/configs/bf537-minotaur.h
@@ -87,9 +87,8 @@
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_ROOTPATH /romfs
-/* Use a fixed MAC address for booting up. Firstboot linux
- * must fetch a valid MAC from the production server. */
-#define CONFIG_ETHADDR 02:80:ad:20:31:42
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */
/*
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
index 727b7e7..7368629 100644
--- a/include/configs/bf537-srv1.h
+++ b/include/configs/bf537-srv1.h
@@ -87,9 +87,8 @@
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_ROOTPATH /romfs
-/* Use a fixed MAC address for booting up. Firstboot linux
- * must fetch a valid MAC from the production server. */
-#define CONFIG_ETHADDR 02:80:ad:20:31:42
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */
/*
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index dbcd2af..5b9de16 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -69,9 +69,10 @@
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_SMC911X 1
-#define CONFIG_DRIVER_SMC911X_BASE 0x24000000
-#define CONFIG_DRIVER_SMC911X_16_BIT
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE 0x24000000
+#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME bf548-ezkit
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index 48c5198..217a8ee 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -330,6 +330,11 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
+
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_AD7414 1 /* use AD7414 */
@@ -442,6 +447,7 @@
/*
* Commands additional to the ones defined in amcc-common.h
*/
+#define CONFIG_CMD_CHIP_CONFIG
#if defined(CONFIG_ARCHES)
#define CONFIG_CMD_DTT
#define CONFIG_CMD_PCI
@@ -453,6 +459,7 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SATA
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
@@ -518,6 +525,19 @@
#endif /* CONFIG_ARCHES */
#endif /* CONFIG_460GT */
+/*
+ * SATA driver setup
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_SATA_DWC
+#define CONFIG_LIBATA
+#define SATA_BASE_ADDR 0xe20d1000 /* PPC460EX SATA Base Address */
+#define SATA_DMA_REG_ADDR 0xe20d0800 /* PPC460EX SATA Base Address */
+#define CONFIG_SYS_SATA_MAX_DEVICE 1 /* SATA MAX DEVICE */
+/* Convert sectorsize to wordsize */
+#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
+#endif
+
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
index 93c2239..b5cfc21 100644
--- a/include/configs/cm-bf548.h
+++ b/include/configs/cm-bf548.h
@@ -69,9 +69,10 @@
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_SMC911X 1
-#define CONFIG_DRIVER_SMC911X_BASE 0x24000000
-#define CONFIG_DRIVER_SMC911X_16_BIT
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE 0x24000000
+#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME cm-bf548
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:24:31:91 */
diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h
index 1153f11..59dc8d2 100644
--- a/include/configs/cm-bf561.h
+++ b/include/configs/cm-bf561.h
@@ -65,7 +65,7 @@
#define CONFIG_SMC91111_BASE 0x28000300
/* The next 3 lines are for use with EXT-BF5xx-USB-ETH2 */
/* #define CONFIG_DRIVER_SMC911X 1 */
-/* #define CONFIG_DRIVER_SMC911X_BASE 0x24080000 // AMS1 */
+/* #define CONFIG_DRIVER_SMC911X_BASE 0x24080000 /! AMS1 */
/* #define CONFIG_DRIVER_SMC911X_32_BIT 1 */
#define CONFIG_HOSTNAME cm-bf561
/* Uncomment next line to use fixed MAC address */
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index 80559bf..be478b2 100644
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -44,11 +44,6 @@
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
diff --git a/include/configs/compactcenter.h b/include/configs/compactcenter.h
new file mode 100644
index 0000000..f8a1bbb
--- /dev/null
+++ b/include/configs/compactcenter.h
@@ -0,0 +1,437 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on include/configs/canyonlands.h
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * compactcenter.h - configuration for CompactCenter (460EX)
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+/*
+ * This config file is used for CompactCenter and DevCon-Center
+ */
+#define CONFIG_460EX 1 /* Specific PPC460EX */
+#ifdef CONFIG_DEVCONCENTER
+#define CONFIG_HOSTNAME devconcenter
+#define CONFIG_IDENT_STRING " devconcenter 0.02"
+#else
+#define CONFIG_HOSTNAME compactcenter
+#define CONFIG_IDENT_STRING " compactcenter 0.02"
+#endif
+#define CONFIG_440 1
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+
+#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+#define CONFIG_FIT
+#define CFG_ALT_MEMTEST
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
+#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
+#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
+
+/* EBC stuff */
+#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */
+#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* later mapped here */
+#define CONFIG_SYS_FLASH_SIZE (128 << 20)
+#else
+#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */
+#define CONFIG_SYS_FLASH_SIZE (64 << 20)
+#endif
+
+#define CONFIG_SYS_NVRAM_BASE 0xE0000000
+#define CONFIG_SYS_UART_BASE 0xE0100000
+#define CONFIG_SYS_IO_BASE 0xE0200000
+
+#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
+#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
+#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */
+#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xC8000000
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
+#endif
+#define CONFIG_SYS_FLASH_BASE_PHYS \
+ (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
+ | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
+
+#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
+#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
+#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
+
+#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */
+
+#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */
+
+/*
+ * Initial RAM & stack pointer (placed in OCM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
+#define CONFIG_SYS_INIT_RAM_END (4 << 10)
+#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Serial Port
+ */
+#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
+
+/*
+ * Environment
+ */
+/*
+ * Define here the location of the environment variables (FLASH).
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
+
+/*
+ * FLASH related
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#ifdef CONFIG_DEVCONCENTER
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max num of sectors per chip*/
+#else
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
+#endif
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buff'd writes (20x faster) */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*
+ * DDR SDRAM
+ */
+
+#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
+
+#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
+#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
+#undef CONFIG_PPC4xx_DDR_METHOD_A
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+/* Memory Queue */
+#define CONFIG_SYS_SDRAM_R0BAS 0x0000f800
+#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
+#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
+#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
+#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
+#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
+#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C80
+#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
+#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
+
+/* SDRAM Controller */
+#define CONFIG_SYS_SDRAM0_MB0CF 0x00000201
+#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
+#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
+#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
+#define CONFIG_SYS_SDRAM0_MCOPT1 0x05122000
+#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0 0x00000000
+#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
+#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
+#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
+#define CONFIG_SYS_SDRAM0_CODT 0x00000020
+#define CONFIG_SYS_SDRAM0_RTR 0x06180000
+#define CONFIG_SYS_SDRAM0_INITPLR0 0xA8380000
+#define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400
+#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000
+#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000
+#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010000
+#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000542
+#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400
+#define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000
+#define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000
+#define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000
+#define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000
+#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442
+#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010380
+#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010000
+#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
+#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
+#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
+#define CONFIG_SYS_SDRAM0_RFDC 0x003F0000
+#define CONFIG_SYS_SDRAM0_RDCC 0x80000000
+#define CONFIG_SYS_SDRAM0_DLCR 0x00000000
+#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
+#define CONFIG_SYS_SDRAM0_WRDTR 0x84000800
+#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
+#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
+#define CONFIG_SYS_SDRAM0_SDTR3 0x090B0D15
+#define CONFIG_SYS_SDRAM0_MMODE 0x00000442
+#define CONFIG_SYS_SDRAM0_MEMODE 0x00000000
+
+#define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
+
+/* I2C SYSMON */
+#define CONFIG_DTT_LM63 1 /* National LM63 */
+#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
+#define CONFIG_DTT_PWM_LOOKUPTABLE \
+ { { 40, 10 }, { 50, 20 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT 0xa10
+
+/* RTC configuration */
+#define CONFIG_RTC_DS1337 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * Ethernet
+ */
+#define CONFIG_IBM_EMAC4_V4 1
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
+#define CONFIG_PHY1_ADDR 3
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CONFIG_PHY_DYNAMIC_ANEG 1
+
+/*
+ * USB-OHCI
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors*/
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
+#define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */
+#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ "kernel_addr=fc000000\0" \
+ "fdt_addr=fc1e0000\0" \
+ "ramdisk_addr=fc200000\0" \
+ "pciconfighost=1\0" \
+ "pcie_mode=RP:RP\0" \
+ ""
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * PCI stuff
+ */
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_DISABLE_PCIE
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
+#undef CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/*
+ * CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the
+ * boot EBC mapping only supports a maximum of 16MBytes
+ * (4.ff00.0000 - 4.ffff.ffff).
+ * To solve this problem, the FLASH has to get remapped to another
+ * EBC address which accepts bigger regions:
+ *
+ * 0xfc00.0000 -> 4.cc00.0000
+ */
+
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP 0x10055e00
+#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
+
+/* Memory Bank 1 (NVRAM) initialization */
+#define CONFIG_SYS_EBC_PB1AP 0x02815480
+/* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/
+#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NVRAM_BASE | 0x18000)
+
+/* Memory Bank 2 (UART) initialization */
+#define CONFIG_SYS_EBC_PB2AP 0x02815480
+/* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_UART_BASE | 0x1A000)
+
+/* Memory Bank 3 (IO) initialization */
+#define CONFIG_SYS_EBC_PB3AP 0x02815480
+/* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_IO_BASE | 0x1A000)
+
+/*
+ * PPC4xx GPIO Configuration
+ */
+/* 460EX: Use USB configuration */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+{ \
+/* GPIO Core 0 */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
+}, \
+{ \
+/* GPIO Core 1 */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
+{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 USB_SERVICE_SUSPEND_N */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51 SPI_CSS_N */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52 FPGA_PROGRAM_UC_N */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 FPGA_INIT_UC_N */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54 WD_STROBE */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 LED_2_OUT */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56 LED_1_OUT */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61 STARTUP_FINISHED_N */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62 STARTUP_FINISHED */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 SERVICE_PORT_ACTIVE */ \
+} \
+}
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index e1cdc7f..f4fd808 100644
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -45,11 +45,6 @@
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
@@ -121,38 +116,6 @@
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_PING
-#ifdef NAND_SUPPORT_HAS_BEEN_FIXED /* NAND support is broken / unimplemented */
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
-#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
-
-#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
-#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
-#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
-
-#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-/* the following are NOP's in our implementation */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-
-#endif /* NAND_SUPPORT_HAS_BEEN_FIXED */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 9cb9838..7909569 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -93,6 +93,7 @@
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/*=====================*/
/* Board related stuff */
/*=====================*/
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index a47620f..531baf1 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -88,6 +88,7 @@
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/* I2C switch definitions for PCA9543 chip */
#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
diff --git a/include/configs/delta.h b/include/configs/delta.h
index e7186e8..95e04f9 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -220,14 +220,14 @@
/*
* NAND Flash
*/
-#undef CONFIG_NAND_LEGACY
-
#define CONFIG_SYS_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
#undef CONFIG_SYS_NAND1_BASE
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/* nand timeout values */
#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000
#define CONFIG_SYS_NAND_OTHER_TO 100
@@ -255,13 +255,6 @@
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 1
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_ENV_IS_IN_NAND 1
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index 558010f..6ccebfa 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -272,6 +272,7 @@
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h
new file mode 100644
index 0000000..4533799
--- /dev/null
+++ b/include/configs/dlvision.h
@@ -0,0 +1,225 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP 1 /* this is a PPC405 CPU */
+#define CONFIG_4xx 1 /* member of PPC4xx family */
+#define CONFIG_DLVISION 1 /* on a Neo board */
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME dlvision
+#define CONFIG_IDENT_STRING " dlvision 0.01"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
+#define CONFIG_MISC_INIT_R /* call misc_init_r */
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ "kernel_addr=fc000000\0" \
+ "fdt_addr=fc1e0000\0" \
+ "ramdisk_addr=fc200000\0" \
+ ""
+
+#define CONFIG_PHY_ADDR 4 /* PHY address */
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
+#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD 691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address*/
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CONFIG_SYS_FLASH_BASE 0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP 0x92015480
+/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
+
+/* Memory Bank 1 (NVRAM) initializatio */
+#define CONFIG_SYS_EBC_PB1AP 0x92015480
+/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB1CR 0xFB858000
+
+/* Memory Bank 2 (UART) initialization */
+#define CONFIG_UART_BASE 0x7f100000
+#define CONFIG_SYS_EBC_PB2AP 0x92015480
+/* BAS=0x7f1,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB2CR 0x7f118000
+
+/* Memory Bank 3 (Latches) initialization */
+#define CONFIG_SYS_LATCH_BASE 0x7f200000
+#define CONFIG_SYS_EBC_PB3AP 0x92015480
+/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 6f58bac..7b0a08f 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -87,7 +87,7 @@
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
/* Enable needed helper functions */
-#define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */
+#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
#endif
/*
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 74f54c0..6131008 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -104,9 +104,10 @@
"prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"
-#define CONFIG_DRIVER_SMC911X 1
-#define CONFIG_DRIVER_SMC911X_BASE (CS4_BASE + 0x00020000)
-#define CONFIG_DRIVER_SMC911X_32_BIT 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000)
+#define CONFIG_SMC911X_32_BIT 1
/*
* Miscellaneous configurable options
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index cb42a7c..1dbafa0 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -106,9 +106,10 @@
"prg_jffs2=tftpboot 0x80000000 $(jffs2); erase 0xa01c0000 0xa1ffffff; cp.b 0x80000000 0xa01c0000 $(filesize)\0"
-#define CONFIG_DRIVER_SMC911X 1
-#define CONFIG_DRIVER_SMC911X_BASE 0xa8000000
-#define CONFIG_DRIVER_SMC911X_32_BIT 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE 0xa8000000
+#define CONFIG_SMC911X_32_BIT 1
/*
* Miscellaneous configurable options
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h
index 0fcf692..0cc1b3b 100644
--- a/include/configs/keymile-common.h
+++ b/include/configs/keymile-common.h
@@ -45,6 +45,7 @@
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_JFFS2_CMDLINE
+#define CONFIG_CMD_MTDPARTS
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
@@ -97,7 +98,7 @@
#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */
#define CONFIG_I2C_MULTI_BUS 1
-#define CONFIG_SYS_MAX_I2C_BUS 2
+#define CONFIG_SYS_MAX_I2C_BUS 1
#define CONFIG_SYS_I2C_INIT_BOARD 1
#define CONFIG_I2C_MUX 1
@@ -122,6 +123,20 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */
+
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for UBI/UBIFS */
+
+/* UBI Support for all Keymile boards */
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_CONCAT
+
/* define this to use the keymile's io muxing feature */
/*#define CONFIG_IO_MUXING */
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 97bac99..965599c 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -217,6 +217,8 @@
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
@@ -234,9 +236,11 @@
*
* DDR Autocalibration Method_B is the default.
*/
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
#undef CONFIG_PPC4xx_DDR_METHOD_A
+#endif
#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
@@ -372,9 +376,15 @@
*----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
/* Standard DTT sensor configuration */
#define CONFIG_DTT_DS1775 1
@@ -424,6 +434,7 @@
/*
* Commands additional to the ones defined in amcc-common.h
*/
+#define CONFIG_CMD_CHIP_CONFIG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_LOG
#define CONFIG_CMD_NAND
diff --git a/include/configs/km8xx.h b/include/configs/km8xx.h
index c305b89..b5552d2 100644
--- a/include/configs/km8xx.h
+++ b/include/configs/km8xx.h
@@ -121,7 +121,6 @@
#define CONFIG_SYS_FLASH_BASE 0xf0000000
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
/*
* For booting Linux, the board info and command line data
@@ -146,7 +145,6 @@
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
-#define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */
#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 19da133..869fd4c 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -33,7 +33,6 @@
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
-#undef CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_MISC_INIT_R 1
/*
* System Clock Setup
@@ -157,8 +156,7 @@
#undef CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
/*
* Initial RAM Base Address Setup
@@ -292,7 +290,6 @@
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
-#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
/* Address and size of Redundant Environment Sector */
@@ -314,7 +311,6 @@
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_I2C_MULTI_BUS 1
-#define CONFIG_SYS_MAX_I2C_BUS 2
#define CONFIG_I2C_MUX 1
/* EEprom support */
@@ -326,7 +322,7 @@
#define CONFIG_SYS_DTT_MAX_TEMP 70
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3
-#define CONFIG_SYS_DTT_BUS_NUM (2)
+#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -433,7 +429,7 @@
#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
-#define MTDIDS_DEFAULT "nor0=app"
+#define MTDIDS_DEFAULT "nor2=app"
#define MTDPARTS_DEFAULT \
"mtdparts=app:256k(u-boot),128k(env),128k(envred)," \
"1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)"
diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h
index 1e7d90e..5c06642 100644
--- a/include/configs/m501sk.h
+++ b/include/configs/m501sk.h
@@ -46,11 +46,6 @@
*/
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
@@ -162,11 +157,6 @@
#define CONFIG_SYS_PROMPT_HUSH_PS2 ">>"
#define CONFIG_SYS_MAX_NAND_DEVICE 0 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index e00859a..1ecae00 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -249,7 +249,6 @@
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index 28c4de0..8253172 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -119,6 +119,8 @@
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h
index cc42101..ea14948 100644
--- a/include/configs/mgcoge.h
+++ b/include/configs/mgcoge.h
@@ -98,13 +98,11 @@
"addcon=setenv bootargs ${bootargs} " \
"console=ttyCPM0,${baudrate}\0" \
"mtdids=nor0=boot,nor1=app \0" \
- "mtdparts=mtdparts=boot:384k(u-boot),128k(env),128k(envred)," \
- "3456k(free);app:3m(esw0),10m(rootfs0),3m(esw1)," \
- "10m(rootfs1),1m(var),5m(cfg) \0" \
"partition=nor1,5 \0" \
"new_env=prot off FE060000 FE09FFFF; era FE060000 FE09FFFF \0" \
"EEprom_ivm=pca9544a:70:4 \0" \
- "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
+ "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
+ "unlock=yes\0" \
""
#define CONFIG_SYS_SDRAM_BASE 0x00000000
@@ -112,13 +110,17 @@
#define CONFIG_SYS_FLASH_SIZE 32
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BASE_1 0x50000000
-#define CONFIG_SYS_FLASH_SIZE_1 64
+#define CONFIG_SYS_FLASH_SIZE_1 32
+#define CONFIG_SYS_FLASH_BASE_2 0x52000000
+#define CONFIG_SYS_FLASH_SIZE_2 32
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_FLASH_BASE_1, \
+ CONFIG_SYS_FLASH_BASE_2 }
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
@@ -193,7 +195,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
@@ -333,9 +334,10 @@
#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
-#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1) |\
- ORxG_CSNT | ORxG_ACS_DIV2 |\
- ORxG_SCY_5_CLK | ORxG_TRLX )
+#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
+ CONFIG_SYS_FLASH_SIZE_2) |\
+ ORxG_CSNT | ORxG_ACS_DIV2 |\
+ ORxG_SCY_5_CLK | ORxG_TRLX )
#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h
index 8ff2f8a..8f71664 100644
--- a/include/configs/mimc200.h
+++ b/include/configs/mimc200.h
@@ -82,6 +82,8 @@
#define CONFIG_DISABLE_CONSOLE 1 /* disable console */
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
+#define CONFIG_LCD 1
+
/*
* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
* data on the serial line may interrupt the boot sequence.
@@ -127,6 +129,20 @@
#define CONFIG_MMC 1
#define CONFIG_ATMEL_MCI 1
+#if defined(CONFIG_LCD)
+#define CONFIG_CMD_BMP
+#define CONFIG_ATMEL_LCD 1
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_BMP_16BPP 1
+#define CONFIG_FB_ADDR 0x10600000
+#define CONFIG_WHITE_ON_BLACK 1
+#define CONFIG_VIDEO_BMP_GZIP 1
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE 262144
+#define CONFIG_ATMEL_LCD_BGR555 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+#define CONFIG_SPLASH_SCREEN 1
+#endif
+
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_SYS_ICACHE_LINESZ 32
diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index 3225ce7..0c2ee60 100644
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -49,11 +49,6 @@
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
@@ -216,7 +211,7 @@
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */
+#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */
diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h
new file mode 100644
index 0000000..96b4d1c
--- /dev/null
+++ b/include/configs/mv88f6281gtw_ge.h
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_MV88F6281GTW_GE_H
+#define _CONFIG_MV88F6281GTW_GE_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nMarvell-MV88F6281GTW_GE"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL 1
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+#define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */
+
+#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
+
+/*
+ * CLKs configurations
+ */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+ 115200,230400, 460800, 921600 }
+/* auto boot */
+#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_USB
+
+/*
+ * Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH 1
+#define CONFIG_HARD_SPI 1
+#define CONFIG_KIRKWOOD_SPI 1
+#define CONFIG_SPI_FLASH_MACRONIX 1
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */
+#endif
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */
+#else
+#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#endif
+#define CONFIG_ENV_SIZE 0x1000 /* 4k */
+#define CONFIG_ENV_ADDR 0x30000
+#define CONFIG_ENV_OFFSET 0x30000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
+ "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
+ "${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define CONFIG_MTDPARTS "spi0.0:512k(uboot)," \
+ "512k@512k(psm),2m@1m(kernel),13m@3m(rootfs)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
+ "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
+ "x_bootcmd_kernel=cp.b 0xE8100000 0x6400000 0x200000\0" \
+ "x_bootcmd_usb=usb start\0" \
+ "x_bootargs_root=root=/dev/mtdblock3 ro rootfstype=squashfs\0"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
+#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
+#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Marvell 88Exxxx Switch configurations
+ */
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init phy/swtich */
+#define CONFIG_MV88E61XX_SWITCH /* Enable mv88e61xx switch driver */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+#endif /* _CONFIG_MV88F6281GTW_GE_H */
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index a4862c6..fb61432 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -106,9 +106,10 @@
"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
"tftpboot 0x81000000 uImage-mx31; bootm\0"
-#define CONFIG_DRIVER_SMC911X 1
-#define CONFIG_DRIVER_SMC911X_BASE 0xB6000000
-#define CONFIG_DRIVER_SMC911X_32_BIT 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE 0xB6000000
+#define CONFIG_SMC911X_32_BIT 1
/*
* Miscellaneous configurable options
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index 5062cdb..f0b4207 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -110,6 +110,8 @@
#define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23)
#define NAND_ALLOW_ERASE_ALL 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h
index 3e2e09f..8a83d92 100644
--- a/include/configs/nhk8815.h
+++ b/include/configs/nhk8815.h
@@ -93,7 +93,7 @@
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
#define CONFIG_SYS_64BIT_VSPRINTF /* mtd desires this */
-#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */
+#define BOARD_LATE_INIT /* call board_late_init during start up */
/* timing informazion */
#define CONFIG_SYS_HZ 1000 /* Mandatory... */
@@ -110,6 +110,22 @@
#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
#define CONFIG_PL011_CLOCK 48000000
+/* i2c, for the port extenders (uses gpio.c in board directory) */
+#ifndef __ASSEMBLY__
+#include <asm/arch/gpio.h>
+#define CONFIG_CMD_I2C
+#define CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#define __SDA 63
+#define __SCL 62
+#define I2C_SDA(x) nmk_gpio_set(__SDA, x)
+#define I2C_SCL(x) nmk_gpio_set(__SCL, x)
+#define I2C_READ (nmk_gpio_get(__SDA)!=0)
+#define I2C_ACTIVE nmk_gpio_dir(__SDA, 1)
+#define I2C_TRISTATE nmk_gpio_dir(__SDA, 0)
+#define I2C_DELAY (udelay(2))
+#endif /* __ASSEMBLY__ */
+
/* Ethernet */
#define PCI_MEMORY_VADDR 0xe8000000
#define PCI_IO_VADDR 0xee000000
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
index 1803b13..9c18842 100644
--- a/include/configs/omap2420h4.h
+++ b/include/configs/omap2420h4.h
@@ -147,42 +147,6 @@
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
-#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
-#define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
-#define NAND_WAIT_READY(nand) udelay(10)
-
-#define NAND_NO_RB 1
-
-#define CONFIG_SYS_NAND_WP
-#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
-#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
-
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-
#define CONFIG_BOOTDELAY 3
#ifdef NFS_BOOT_DEFAULTS
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index c2bd7e6..8fc6fb2 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -130,6 +130,12 @@
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+#define CONFIG_TWL4030_LED 1
+
+/*
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
@@ -142,6 +148,7 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index e205c01..809198b 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -128,6 +128,11 @@
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/*
* Board NAND Info.
*/
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
@@ -138,6 +143,7 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
@@ -301,9 +307,10 @@ extern unsigned int boot_flash_type;
*/
#if defined(CONFIG_CMD_NET)
-#define CONFIG_DRIVER_SMC911X
-#define CONFIG_DRIVER_SMC911X_32_BIT
-#define CONFIG_DRIVER_SMC911X_BASE 0x2C000000
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE 0x2C000000
#endif /* (CONFIG_CMD_NET) */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 8902312..c359c60 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -116,6 +116,12 @@
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+#define CONFIG_TWL4030_LED 1
+
+/*
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
@@ -128,6 +134,8 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index dbd4dcc..d7b1cc1 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -119,6 +119,12 @@
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+#define CONFIG_TWL4030_LED 1
+
+/*
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
@@ -132,6 +138,8 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 9e000ed..676b425 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -126,6 +126,12 @@
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+#define CONFIG_TWL4030_LED 1
+
+/*
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
@@ -138,6 +144,9 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index c2ad5bf..3f6f545 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -147,6 +147,12 @@
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+#define CONFIG_TWL4030_LED 1
+
+/*
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
@@ -158,6 +164,8 @@
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/* Environment information */
#define CONFIG_BOOTDELAY 10
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index 1255f21..2612165 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -265,7 +265,8 @@
* NAND-FLASH stuff
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
+#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 4784c40..203a14c 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -236,6 +236,8 @@
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/* NOR flash */
#define CONFIG_SYS_FLASH_CFI 1
@@ -366,7 +368,6 @@
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 94e1eb9..a6ff28c 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -258,6 +258,8 @@
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
#define CONFIG_CMD_JFFS2 1
@@ -395,7 +397,6 @@
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
-#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
/*
* Size of malloc() pool
*/
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 8444462..cbacdf9 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -163,6 +163,8 @@
#undef CONFIG_MEMSIZE_IN_BYTES
+#define CONFIG_LZMA
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
index 3ea854b..d63c43e 100644
--- a/include/configs/quad100hd.h
+++ b/include/configs/quad100hd.h
@@ -225,6 +225,8 @@
#define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */
#define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*-----------------------------------------------------------------------
diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h
new file mode 100644
index 0000000..3d8e25c
--- /dev/null
+++ b/include/configs/rd6281a.h
@@ -0,0 +1,198 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_RD6281A_H
+#define _CONFIG_RD6281A_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nMarvell-RD6281A"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL 1
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+#define CONFIG_MACH_RD6281A /* Machine type */
+
+#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
+
+/*
+ * CLKs configurations
+ */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+ 115200,230400, 460800, 921600 }
+/* auto boot */
+#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL 1
+#endif
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE 0x20000 /* 128k */
+#define CONFIG_ENV_ADDR 0x40000
+#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
+ "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
+ "${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \
+ "3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
+ "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
+ "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
+ "x_bootcmd_usb=usb start\0" \
+ "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
+#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
+#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
+#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
+#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
+#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */
+#define CONFIG_PHY_BASE_ADR 0x0A
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init switch and PHY */
+#define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+#endif /* _CONFIG_RD6281A_H */
diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h
index 36e4c01..9aa71b4 100644
--- a/include/configs/rsk7203.h
+++ b/include/configs/rsk7203.h
@@ -105,8 +105,9 @@
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
/* Network interface */
-#define CONFIG_DRIVER_SMC911X
-#define CONFIG_DRIVER_SMC911X_16_BIT
-#define CONFIG_DRIVER_SMC911X_BASE (0x24000000)
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE (0x24000000)
#endif /* __RSK7203_H */
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index eab9629..f3dc7fe 100644
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -201,29 +201,6 @@
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_S3C2410
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#define NAND_WAIT_READY(nand) NF_WaitRB()
-#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
-#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
-#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
-#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
-#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
-#define WRITE_NAND(d, adr) NF_Write(d)
-#define READ_NAND(adr) NF_Read()
-/* the following functions are NOP's because S3C24X0 handles this in hardware */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
#endif /* CONFIG_CMD_NAND */
#define CONFIG_SETUP_MEMORY_TAGS
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 84a251a..868bd54 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -651,8 +651,8 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
- "update=protect off fff00000 fff3ffff; " \
- "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
+ "update=protect off ff800000 ff83ffff; " \
+ "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
"upd=run load update\0" \
"fdtaddr=400000\0" \
"fdtfile=sbc8349.dtb\0" \
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index 97e1da2..7e00ab8 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -426,6 +426,7 @@ extern unsigned long offsetOfEnvironment;
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x77D00000
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
new file mode 100644
index 0000000..fc401a8
--- /dev/null
+++ b/include/configs/sheevaplug.h
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_SHEEVAPLUG_H
+#define _CONFIG_SHEEVAPLUG_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nMarvell-Sheevaplug"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL 1
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+#define CONFIG_MACH_SHEEVAPLUG /* Machine type */
+
+#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
+
+/*
+ * CLKs configurations
+ */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+ 115200,230400, 460800, 921600 }
+/* auto boot */
+#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL 1
+#endif
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE 0x20000 /* 128k */
+#define CONFIG_ENV_ADDR 0x40000
+#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
+ "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
+ "${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \
+ "3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
+ "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
+ "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
+ "x_bootcmd_usb=usb start\0" \
+ "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
+#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
+#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 0
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+#endif /* _CONFIG_SHEEVAPLUG_H */
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index 018f576..ddc8e71 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -269,6 +269,8 @@
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63}
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/* Boot configuration (define only one of next 3) */
#define CONFIG_BOOT_NAND
/* None of these are currently implemented. Left from the original Samsung
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 5b91b4d..35feed0 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -188,6 +188,8 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_CMD_NAND
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/* LIME GDC */
#define CONFIG_SYS_LIME_BASE 0xc8000000
#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index 147233d..d16262b 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -118,7 +118,6 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
@@ -446,90 +445,9 @@
#define NAND_SIZE 0x00010000 /* 64K */
#define NAND_BASE 0xF1000000
-/****************************************************************/
-
-/* NAND */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_NAND_BASE NAND_BASE
-#define CONFIG_MTD_NAND_ECC_JFFS2
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_MTD_NAND_UNSAFE
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#undef NAND_NO_RB
-
-#define SECTORSIZE 512
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
-#define NAND_DISABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \
- } while(0)
-
-#define NAND_ENABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
- } while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
- } while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \
- } while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
- } while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \
- } while(0)
-
-#ifndef NAND_NO_RB
-#define NAND_WAIT_READY(nand) \
- do { \
- int _tries = 0; \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
- if (++_tries > 100000) \
- break; \
- } while (0)
-#else
-#define NAND_WAIT_READY(nand) udelay(12)
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define READ_NAND(adr) \
- ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
/*****************************************************************************/
#define CONFIG_SYS_DIRECT_FLASH_TFTP
-#define CONFIG_SYS_DIRECT_NAND_TFTP
/*****************************************************************************/
diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
index 3917a1b..425f472 100644
--- a/include/configs/svm_sc8xx.h
+++ b/include/configs/svm_sc8xx.h
@@ -147,12 +147,8 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DOC
#define CONFIG_CMD_DATE
-
-#define CONFIG_NAND_LEGACY
-
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/vct.h b/include/configs/vct.h
index e72b504..20bf481 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -89,10 +89,11 @@
/*
* SMSC91C11x Network Card
*/
-#define CONFIG_DRIVER_SMC911X
-#define CONFIG_DRIVER_SMC911X_BASE 0x00000000
-#define CONFIG_DRIVER_SMC911X_32_BIT
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE 0x00000000
+#define CONFIG_SMC911X_32_BIT
#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_NET_MULTI
#endif
/*
@@ -342,7 +343,7 @@ int vct_gpio_get(int pin);
#undef CONFIG_CMD_TERMINAL
#undef CONFIG_CMD_USB
-#undef CONFIG_DRIVER_SMC911X
+#undef CONFIG_SMC911X
#undef CONFIG_SOFT_I2C
#undef CONFIG_SOURCE
#undef CONFIG_SYS_LONGHELP
diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h
index 9ebafcc..f7813a1 100644
--- a/include/configs/virtlab2.h
+++ b/include/configs/virtlab2.h
@@ -38,8 +38,8 @@
#define CONFIG_TQM8xxL 1
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
new file mode 100644
index 0000000..1477552
--- /dev/null
+++ b/include/configs/vme8349.h
@@ -0,0 +1,608 @@
+/*
+ * esd vme8349 U-Boot configuration file
+ * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
+ *
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * reinhard.arlt@esd-electronics.de
+ * Based on the MPC8349EMDS config.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * vme8349 board configuration file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+#define CONFIG_MPC83xx 1 /* MPC83xx family */
+#define CONFIG_MPC834x 1 /* MPC834x family */
+#define CONFIG_MPC8349 1 /* MPC8349 specific */
+#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
+
+#define CONFIG_PCI
+/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
+#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
+
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
+#else
+#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef PCI_66M
+#define CONFIG_SYS_CLK_FREQ 66000000
+#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
+#else
+#define CONFIG_SYS_CLK_FREQ 33000000
+#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
+#endif
+#endif
+
+#define CONFIG_SYS_IMMR 0xE0000000
+
+#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
+#undef CONFIG_SPD_EEPROM /* dont use SPD EEPROM for DDR setup*/
+#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_DDR_2T_TIMING
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE 512 /* MB */
+
+#if (CONFIG_SYS_DDR_SIZE == 512)
+#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
+ CSCONFIG_COL_BIT_10 | \
+ CSCONFIG_BANK_BIT_3)
+#endif
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_TIMING_0 0x00220802
+#define CONFIG_SYS_DDR_TIMING_1 0x39377322
+#define CONFIG_SYS_DDR_TIMING_2 0x2f9848ca /* P9-45, tuning? */
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuf,no DYN_PWR */
+#define CONFIG_SYS_DDR_MODE 0x07940242
+#define CONFIG_SYS_DDR_MODE2 0x00000000
+/* autocharge,no open page */
+#define CONFIG_SYS_DDR_INTERVAL 0x04060100
+#define CONFIG_SYS_DDR_SDRAM_CFG 0x63000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x04061000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
+ (2 << BR_PS_SHIFT) | /* 32bit */ \
+ BR_V) /* valid */
+
+#define CONFIG_SYS_OR0_PRELIM 0xF8006FF7 /* 128 MB flash size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001A /* 128 MB window size */
+
+#define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801)
+#define CONFIG_SYS_OR1_PRELIM (0xffff8000 | 0x00000200)
+#define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000
+#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x0000000e)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
+
+#define CONFIG_SYS_MID_FLASH_JUMP 0x7F000000
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_END 0x1000 /* size */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* size init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Malloc size */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ * LCRR: DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LBC_LBCR 0x00000000
+
+#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
+
+#define CONFIG_CMDLINE_EDITING /* add command line history */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* I2C */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES {{0, 0x69}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C1_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
+
+#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define PCI_64BIT
+#define PCI_ONE_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#define CONFIG_NET_MULTI
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xFIXME
+ #define PCI_ENET0_MEMADDR 0xFIXME
+ #define PCI_IDSEL_NUMBER 0xFIXME
+#endif
+
+#endif /* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+
+#if defined(CONFIG_TSEC_ENET)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+
+#define CONFIG_GMII /* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define CONFIG_PHY_M88E1111
+#define TSEC1_PHY_ADDR 0x08
+#define TSEC2_PHY_ADDR 0x10
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+ #define CONFIG_ENV_IS_IN_FLASH
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
+ #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+ #define CONFIG_ENV_SIZE 0x2000
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#else
+ #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
+ #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+ #define CONFIG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_SYS_RTC_BUS_NUM 0x01
+#define CONFIG_SYS_I2C_RTC_ADDR 0x32
+#define CONFIG_RTC_RX8025
+#define CONFIG_CMD_TSI148
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMD_ELF
+/* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max num of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
+#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Init Memory map for Linux*/
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+#define CONFIG_SYS_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN |\
+ HRCWL_VCO_1X2 |\
+ HRCWL_CORE_TO_CSB_2X1)
+
+#if defined(PCI_64BIT)
+#define CONFIG_SYS_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_64_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_DISABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII)
+#else
+#define CONFIG_SYS_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_32_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII)
+#endif
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+
+#define CONFIG_SYS_HID2 HID2_HBE
+
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR 0x00100000
+#define CONFIG_SYS_GPIO1_DAT 0x00100000
+
+#define CONFIG_SYS_GPIO2_PRELIM
+#define CONFIG_SYS_GPIO2_DIR 0x78900000
+#define CONFIG_SYS_GPIO2_DAT 0x70100000
+
+#define CONFIG_HIGH_BATS /* High BATs supported */
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#else
+#define CONFIG_SYS_IBAT1L (0)
+#define CONFIG_SYS_IBAT1U (0)
+#define CONFIG_SYS_IBAT2L (0)
+#define CONFIG_SYS_IBAT2U (0)
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#else
+#define CONFIG_SYS_IBAT3L (0)
+#define CONFIG_SYS_IBAT3U (0)
+#define CONFIG_SYS_IBAT4L (0)
+#define CONFIG_SYS_IBAT4U (0)
+#endif
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#if (CONFIG_SYS_DDR_SIZE == 512)
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
+ BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
+ BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CONFIG_SYS_IBAT7L (0)
+#define CONFIG_SYS_IBAT7U (0)
+#endif
+
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_HOSTNAME VME8349
+#define CONFIG_ROOTPATH /tftpboot/rootfs
+#define CONFIG_BOOTFILE uImage
+
+#define CONFIG_LOADADDR 500000 /* def location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=vme8349\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
+ "update=protect off fff00000 fff3ffff; " \
+ "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
+ "upd=run load update\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=vme8349.dtb\0" \
+ ""
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
index 15c3708..86b6ea1 100644
--- a/include/configs/zylonite.h
+++ b/include/configs/zylonite.h
@@ -193,7 +193,6 @@
/*
* NAND Flash
*/
-#define CONFIG_NEW_NAND_CODE
#define CONFIG_SYS_NAND0_BASE 0x0
#undef CONFIG_SYS_NAND1_BASE
@@ -206,6 +205,8 @@
#define CONFIG_SYS_NAND_SENDCMD_RETRY 3
#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
/* NAND Timing Parameters (in ns) */
#define NAND_TIMING_tCH 10
#define NAND_TIMING_tCS 0
@@ -227,13 +228,6 @@
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 1
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_ENV_IS_IN_NAND 1
diff --git a/include/elf.h b/include/elf.h
index f640388..29f276d 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -33,15 +33,7 @@
#ifndef _ELF_H
#define _ELF_H
-#if defined(__BEOS__) || \
- defined(__NetBSD__) || \
- defined(__FreeBSD__) || \
- defined(__sun__) || \
- defined(__APPLE__)
-#include <inttypes.h>
-#elif (defined(__linux__) && defined(USE_HOSTCC)) || defined(__WIN32__)
-#include <stdint.h>
-#endif
+#include "compiler.h"
/*
* This version doesn't work for 64-bit ABIs - Erik.
diff --git a/include/environment.h b/include/environment.h
index 507e832..5bed32f 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -96,11 +96,7 @@
# endif
#endif /* CONFIG_ENV_IS_IN_MG_DISK */
-#ifdef USE_HOSTCC
-# include <stdint.h>
-#else
-# include <linux/types.h>
-#endif
+#include "compiler.h"
#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
# define ENV_HEADER_SIZE (sizeof(uint32_t) + 1)
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 0a5c5d6..89b8304 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -26,6 +26,8 @@
#ifndef __FSL_ESDHC_H__
#define __FSL_ESDHC_H__
+#include <asm/errno.h>
+
/* FSL eSDHC-specific constants */
#define SYSCTL 0x0002e02c
#define SYSCTL_INITA 0x08000000
@@ -140,6 +142,12 @@
#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
#define ESDHC_HOSTCAPBLT_HSS 0x00200000
+#ifdef CONFIG_FSL_ESDHC
int fsl_esdhc_mmc_init(bd_t *bis);
+void fdt_fixup_esdhc(void *blob, bd_t *bd);
+#else
+static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
+static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
+#endif /* CONFIG_FSL_ESDHC */
#endif /* __FSL_ESDHC_H__ */
diff --git a/include/hwconfig.h b/include/hwconfig.h
new file mode 100644
index 0000000..d517f78
--- /dev/null
+++ b/include/hwconfig.h
@@ -0,0 +1,69 @@
+/*
+ * An inteface for configuring a hardware via u-boot environment.
+ *
+ * Copyright (c) 2009 MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef _HWCONFIG_H
+#define _HWCONFIG_H
+
+#include <linux/types.h>
+#include <asm/errno.h>
+
+#ifdef CONFIG_HWCONFIG
+
+extern int hwconfig(const char *opt);
+extern const char *hwconfig_arg(const char *opt, size_t *arglen);
+extern int hwconfig_arg_cmp(const char *opt, const char *arg);
+extern int hwconfig_sub(const char *opt, const char *subopt);
+extern const char *hwconfig_subarg(const char *opt, const char *subopt,
+ size_t *subarglen);
+extern int hwconfig_subarg_cmp(const char *opt, const char *subopt,
+ const char *subarg);
+
+#else
+
+static inline int hwconfig(const char *opt)
+{
+ return -ENOSYS;
+}
+
+static inline const char *hwconfig_arg(const char *opt, size_t *arglen)
+{
+ *arglen = 0;
+ return "";
+}
+
+static inline int hwconfig_arg_cmp(const char *opt, const char *arg)
+{
+ return -ENOSYS;
+}
+
+static inline int hwconfig_sub(const char *opt, const char *subopt)
+{
+ return -ENOSYS;
+}
+
+static inline const char *hwconfig_subarg(const char *opt, const char *subopt,
+ size_t *subarglen)
+{
+ *subarglen = 0;
+ return "";
+}
+
+static inline int hwconfig_subarg_cmp(const char *opt, const char *subopt,
+ const char *subarg)
+{
+ return -ENOSYS;
+}
+
+#endif /* CONFIG_HWCONFIG */
+
+#endif /* _HWCONFIG_H */
diff --git a/include/i2c.h b/include/i2c.h
index 668e754..b754769 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -47,7 +47,9 @@
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
#if defined(CONFIG_I2C_MULTI_BUS)
+#if !defined(CONFIG_SYS_MAX_I2C_BUS)
#define CONFIG_SYS_MAX_I2C_BUS 2
+#endif
#define I2C_GET_BUS() i2c_get_bus_num()
#define I2C_SET_BUS(a) i2c_set_bus_num(a)
#else
diff --git a/include/image.h b/include/image.h
index f183757..beb3a16 100644
--- a/include/image.h
+++ b/include/image.h
@@ -33,10 +33,9 @@
#ifndef __IMAGE_H__
#define __IMAGE_H__
-#if USE_HOSTCC
-#ifndef __MINGW32__
-#include <endian.h>
-#endif
+#include "compiler.h"
+
+#ifdef USE_HOSTCC
/* new uImage format support enabled on host */
#define CONFIG_FIT 1
@@ -46,9 +45,7 @@
#else
#include <lmb.h>
-#include <linux/string.h>
#include <asm/u-boot.h>
-#include <asm/byteorder.h>
#endif /* USE_HOSTCC */
@@ -284,8 +281,8 @@ typedef struct bootm_headers {
#define CHUNKSZ_SHA1 (64 * 1024)
#endif
-#define uimage_to_cpu(x) ntohl(x)
-#define cpu_to_uimage(x) htonl(x)
+#define uimage_to_cpu(x) be32_to_cpu(x)
+#define cpu_to_uimage(x) cpu_to_be32(x)
const char *genimg_get_os_name (uint8_t os);
const char *genimg_get_arch_name (uint8_t arch);
diff --git a/include/iomux.h b/include/iomux.h
index 257c1f7..e38a81e 100644
--- a/include/iomux.h
+++ b/include/iomux.h
@@ -24,7 +24,7 @@
#ifndef _IO_MUX_H
#define _IO_MUX_H
-#include <devices.h>
+#include <stdio_dev.h>
/*
* Stuff required to support console multiplexing.
@@ -34,7 +34,7 @@
* Pointers to devices used for each file type. Defined in console.c
* but storage is allocated in iomux.c.
*/
-extern device_t **console_devices[MAX_FILES];
+extern struct stdio_dev **console_devices[MAX_FILES];
/*
* The count of devices assigned to each FILE. Defined in console.c
* and populated in iomux.c.
@@ -43,6 +43,6 @@ extern int cd_count[MAX_FILES];
int iomux_doenv(const int, const char *);
void iomux_printdevs(const int);
-device_t *search_device(int, char *);
+struct stdio_dev *search_device(int, char *);
#endif /* _IO_MUX_H */
diff --git a/include/lcd.h b/include/lcd.h
index f054cac..1f85daa 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -43,6 +43,18 @@ extern void *lcd_console_address; /* Start of console buffer */
extern short console_col;
extern short console_row;
+extern struct vidinfo panel_info;
+
+extern void lcd_ctrl_init (void *lcdbase);
+extern void lcd_enable (void);
+
+/* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */
+extern void lcd_setcolreg (ushort regno,
+ ushort red, ushort green, ushort blue);
+extern void lcd_initcolregs (void);
+
+/* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */
+extern struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp);
#if defined CONFIG_MPC823
/*
@@ -75,8 +87,6 @@ typedef struct vidinfo {
u_char vl_wbf; /* Wait between frames */
} vidinfo_t;
-extern vidinfo_t panel_info;
-
#elif defined CONFIG_PXA250
/*
* PXA LCD DMA descriptor
@@ -146,8 +156,6 @@ typedef struct vidinfo {
struct pxafb_info pxa;
} vidinfo_t;
-extern vidinfo_t panel_info;
-
#elif defined(CONFIG_ATMEL_LCD)
typedef struct vidinfo {
@@ -173,8 +181,6 @@ typedef struct vidinfo {
u_long mmio; /* Memory mapped registers */
} vidinfo_t;
-extern vidinfo_t panel_info;
-
#else
typedef struct vidinfo {
@@ -190,6 +196,8 @@ typedef struct vidinfo {
#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */
+extern vidinfo_t panel_info;
+
/* Video functions */
#if defined(CONFIG_RBC823)
@@ -314,7 +322,7 @@ void lcd_show_board_info(void);
#if LCD_BPP == LCD_MONOCHROME
# define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \
(c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
-#elif LCD_BPP == LCD_COLOR8
+#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
# define COLOR_MASK(c) (c)
#else
# error Unsupported LCD BPP.
diff --git a/include/libfdt_env.h b/include/libfdt_env.h
index 1c67015..bf63583 100644
--- a/include/libfdt_env.h
+++ b/include/libfdt_env.h
@@ -21,56 +21,13 @@
#ifndef _LIBFDT_ENV_H
#define _LIBFDT_ENV_H
-#ifdef USE_HOSTCC
-#include <stdint.h>
-#include <string.h>
-#ifdef __MINGW32__
-#include <linux/types.h>
-#include <linux/byteorder/swab.h>
-#else
-#include <endian.h>
-#include <byteswap.h>
-#endif /* __MINGW32__ */
-#else
-#include <linux/string.h>
-#include <linux/types.h>
-#include <asm/byteorder.h>
-#endif /* USE_HOSTCC */
+#include "compiler.h"
-#include <stddef.h>
extern struct fdt_header *working_fdt; /* Pointer to the working fdt */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-#ifdef __MINGW32__
-#define fdt32_to_cpu(x) ___swab32(x)
-#define cpu_to_fdt32(x) ___swab32(x)
-#define fdt64_to_cpu(x) ___swab64(x)
-#define cpu_to_fdt64(x) ___swab64(x)
-#else
-#define fdt32_to_cpu(x) bswap_32(x)
-#define cpu_to_fdt32(x) bswap_32(x)
-#define fdt64_to_cpu(x) bswap_64(x)
-#define cpu_to_fdt64(x) bswap_64(x)
-#endif
-#else
-#define fdt32_to_cpu(x) (x)
-#define cpu_to_fdt32(x) (x)
-#define fdt64_to_cpu(x) (x)
-#define cpu_to_fdt64(x) (x)
-#endif
-
-#ifndef USE_HOSTCC
-/*
- * Types for `void *' pointers.
- *
- * Note: libfdt uses this definition from /usr/include/stdint.h.
- * Define it here rather than pulling in all of stdint.h.
- */
-#if __WORDSIZE == 64
-typedef unsigned long int uintptr_t;
-#else
-typedef unsigned int uintptr_t;
-#endif
-#endif /* not USE_HOSTCC */
+#define fdt32_to_cpu(x) be32_to_cpu(x)
+#define cpu_to_fdt32(x) cpu_to_be32(x)
+#define fdt64_to_cpu(x) be64_to_cpu(x)
+#define cpu_to_fdt64(x) cpu_to_be64(x)
#endif /* _LIBFDT_ENV_H */
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index a4ad571..3e0044b 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -50,7 +50,7 @@ extern void nand_wait_ready(struct mtd_info *mtd);
* is supported now. If you add a chip with bigger oobsize/page
* adjust this accordingly.
*/
-#define NAND_MAX_OOBSIZE 128
+#define NAND_MAX_OOBSIZE 218
#define NAND_MAX_PAGESIZE 4096
/*
diff --git a/include/linux/mtd/nand_ids.h b/include/linux/mtd/nand_ids.h
deleted file mode 100644
index e7aa26d..0000000
--- a/include/linux/mtd/nand_ids.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * u-boot/include/linux/mtd/nand_ids.h
- *
- * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
- * Steven J. Hill <sjhill@cotw.com>
- *
- * $Id: nand_ids.h,v 1.1 2000/10/13 16:16:26 mdeans Exp $
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Info:
- * Contains standard defines and IDs for NAND flash devices
- *
- * Changelog:
- * 01-31-2000 DMW Created
- * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
- * so it can be used by other NAND flash device
- * drivers. I also changed the copyright since none
- * of the original contents of this file are specific
- * to DoC devices. David can whack me with a baseball
- * bat later if I did something naughty.
- * 10-11-2000 SJH Added private NAND flash structure for driver
- * 2000-10-13 BE Moved out of 'nand.h' - avoids duplication.
- */
-
-#ifndef __LINUX_MTD_NAND_IDS_H
-#define __LINUX_MTD_NAND_IDS_H
-
-#ifndef CONFIG_NAND_LEGACY
-#error This module is for the legacy NAND support
-#endif
-
-static struct nand_flash_dev nand_flash_ids[] = {
- {"Toshiba TC5816BDC", NAND_MFR_TOSHIBA, 0x64, 21, 1, 2, 0x1000, 0},
- {"Toshiba TC5832DC", NAND_MFR_TOSHIBA, 0x6b, 22, 0, 2, 0x2000, 0},
- {"Toshiba TH58V128DC", NAND_MFR_TOSHIBA, 0x73, 24, 0, 2, 0x4000, 0},
- {"Toshiba TC58256FT/DC", NAND_MFR_TOSHIBA, 0x75, 25, 0, 2, 0x4000, 0},
- {"Toshiba TH58512FT", NAND_MFR_TOSHIBA, 0x76, 26, 0, 3, 0x4000, 0},
- {"Toshiba TC58V32DC", NAND_MFR_TOSHIBA, 0xe5, 22, 0, 2, 0x2000, 0},
- {"Toshiba TC58V64AFT/DC", NAND_MFR_TOSHIBA, 0xe6, 23, 0, 2, 0x2000, 0},
- {"Toshiba TC58V16BDC", NAND_MFR_TOSHIBA, 0xea, 21, 1, 2, 0x1000, 0},
- {"Toshiba TH58100FT", NAND_MFR_TOSHIBA, 0x79, 27, 0, 3, 0x4000, 0},
- {"Samsung KM29N16000", NAND_MFR_SAMSUNG, 0x64, 21, 1, 2, 0x1000, 0},
- {"Samsung unknown 4Mb", NAND_MFR_SAMSUNG, 0x6b, 22, 0, 2, 0x2000, 0},
- {"Samsung KM29U128T", NAND_MFR_SAMSUNG, 0x73, 24, 0, 2, 0x4000, 0},
- {"Samsung KM29U256T", NAND_MFR_SAMSUNG, 0x75, 25, 0, 2, 0x4000, 0},
- {"Samsung unknown 64Mb", NAND_MFR_SAMSUNG, 0x76, 26, 0, 3, 0x4000, 0},
- {"Samsung KM29W32000", NAND_MFR_SAMSUNG, 0xe3, 22, 0, 2, 0x2000, 0},
- {"Samsung unknown 4Mb", NAND_MFR_SAMSUNG, 0xe5, 22, 0, 2, 0x2000, 0},
- {"Samsung KM29U64000", NAND_MFR_SAMSUNG, 0xe6, 23, 0, 2, 0x2000, 0},
- {"Samsung KM29W16000", NAND_MFR_SAMSUNG, 0xea, 21, 1, 2, 0x1000, 0},
- {"Samsung K9F5616Q0C", NAND_MFR_SAMSUNG, 0x45, 25, 0, 2, 0x4000, 1},
- {"Samsung K9K1216Q0C", NAND_MFR_SAMSUNG, 0x46, 26, 0, 3, 0x4000, 1},
- {"Samsung K9F1G08U0M", NAND_MFR_SAMSUNG, 0xf1, 27, 0, 2, 0, 0},
- {NULL,}
-};
-
-#endif /* __LINUX_MTD_NAND_IDS_H */
diff --git a/include/linux/mtd/nand_legacy.h b/include/linux/mtd/nand_legacy.h
deleted file mode 100644
index 4334448..0000000
--- a/include/linux/mtd/nand_legacy.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * linux/include/linux/mtd/nand.h
- *
- * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
- * Steven J. Hill <sjhill@cotw.com>
- * Thomas Gleixner <gleixner@autronix.de>
- *
- * $Id: nand.h,v 1.7 2003/07/24 23:30:46 a0384864 Exp $
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Info:
- * Contains standard defines and IDs for NAND flash devices
- *
- * Changelog:
- * 01-31-2000 DMW Created
- * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
- * so it can be used by other NAND flash device
- * drivers. I also changed the copyright since none
- * of the original contents of this file are specific
- * to DoC devices. David can whack me with a baseball
- * bat later if I did something naughty.
- * 10-11-2000 SJH Added private NAND flash structure for driver
- * 10-24-2000 SJH Added prototype for 'nand_scan' function
- * 10-29-2001 TG changed nand_chip structure to support
- * hardwarespecific function for accessing control lines
- * 02-21-2002 TG added support for different read/write adress and
- * ready/busy line access function
- * 02-26-2002 TG added chip_delay to nand_chip structure to optimize
- * command delay times for different chips
- * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate
- * defines in jffs2/wbuf.c
- */
-#ifndef __LINUX_MTD_NAND_LEGACY_H
-#define __LINUX_MTD_NAND_LEGACY_H
-
-#ifndef CONFIG_NAND_LEGACY
-#error This module is for the legacy NAND support
-#endif
-
-/* The maximum number of NAND chips in an array */
-#ifndef CONFIG_SYS_NAND_MAX_CHIPS
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
-#endif
-
-/*
- * Standard NAND flash commands
- */
-#define NAND_CMD_READ0 0
-#define NAND_CMD_READ1 1
-#define NAND_CMD_PAGEPROG 0x10
-#define NAND_CMD_READOOB 0x50
-#define NAND_CMD_ERASE1 0x60
-#define NAND_CMD_STATUS 0x70
-#define NAND_CMD_SEQIN 0x80
-#define NAND_CMD_READID 0x90
-#define NAND_CMD_ERASE2 0xd0
-#define NAND_CMD_RESET 0xff
-
-/*
- * NAND Private Flash Chip Data
- *
- * Structure overview:
- *
- * IO_ADDR - address to access the 8 I/O lines of the flash device
- *
- * hwcontrol - hardwarespecific function for accesing control-lines
- *
- * dev_ready - hardwarespecific function for accesing device ready/busy line
- *
- * chip_lock - spinlock used to protect access to this structure
- *
- * wq - wait queue to sleep on if a NAND operation is in progress
- *
- * state - give the current state of the NAND device
- *
- * page_shift - number of address bits in a page (column address bits)
- *
- * data_buf - data buffer passed to/from MTD user modules
- *
- * data_cache - data cache for redundant page access and shadow for
- * ECC failure
- *
- * ecc_code_buf - used only for holding calculated or read ECCs for
- * a page read or written when ECC is in use
- *
- * reserved - padding to make structure fall on word boundary if
- * when ECC is in use
- */
-struct Nand {
- char floor, chip;
- unsigned long curadr;
- unsigned char curmode;
- /* Also some erase/write/pipeline info when we get that far */
-};
-
-struct nand_chip {
- int page_shift;
- u_char *data_buf;
- u_char *data_cache;
- int cache_page;
- u_char ecc_code_buf[6];
- u_char reserved[2];
- char ChipID; /* Type of DiskOnChip */
- struct Nand *chips;
- int chipshift;
- char* chips_name;
- unsigned long erasesize;
- unsigned long mfr; /* Flash IDs - only one type of flash per device */
- unsigned long id;
- char* name;
- int numchips;
- char page256;
- char pageadrlen;
- unsigned long IO_ADDR; /* address to access the 8 I/O lines to the flash device */
- unsigned long totlen;
- uint oobblock; /* Size of OOB blocks (e.g. 512) */
- uint oobsize; /* Amount of OOB data per block (e.g. 16) */
- uint eccsize;
- int bus16;
-};
-
-/*
- * NAND Flash Manufacturer ID Codes
- */
-#define NAND_MFR_TOSHIBA 0x98
-#define NAND_MFR_SAMSUNG 0xec
-
-/*
- * NAND Flash Device ID Structure
- *
- * Structure overview:
- *
- * name - Complete name of device
- *
- * manufacture_id - manufacturer ID code of device.
- *
- * model_id - model ID code of device.
- *
- * chipshift - total number of address bits for the device which
- * is used to calculate address offsets and the total
- * number of bytes the device is capable of.
- *
- * page256 - denotes if flash device has 256 byte pages or not.
- *
- * pageadrlen - number of bytes minus one needed to hold the
- * complete address into the flash array. Keep in
- * mind that when a read or write is done to a
- * specific address, the address is input serially
- * 8 bits at a time. This structure member is used
- * by the read/write routines as a loop index for
- * shifting the address out 8 bits at a time.
- *
- * erasesize - size of an erase block in the flash device.
- */
-struct nand_flash_dev {
- char * name;
- int manufacture_id;
- int model_id;
- int chipshift;
- char page256;
- char pageadrlen;
- unsigned long erasesize;
- int bus16;
-};
-
-/*
-* Constants for oob configuration
-*/
-#define NAND_NOOB_ECCPOS0 0
-#define NAND_NOOB_ECCPOS1 1
-#define NAND_NOOB_ECCPOS2 2
-#define NAND_NOOB_ECCPOS3 3
-#define NAND_NOOB_ECCPOS4 6
-#define NAND_NOOB_ECCPOS5 7
-#define NAND_NOOB_BADBPOS -1
-#define NAND_NOOB_ECCVPOS -1
-
-#define NAND_JFFS2_OOB_ECCPOS0 0
-#define NAND_JFFS2_OOB_ECCPOS1 1
-#define NAND_JFFS2_OOB_ECCPOS2 2
-#define NAND_JFFS2_OOB_ECCPOS3 3
-#define NAND_JFFS2_OOB_ECCPOS4 6
-#define NAND_JFFS2_OOB_ECCPOS5 7
-#define NAND_JFFS2_OOB_BADBPOS 5
-#define NAND_JFFS2_OOB_ECCVPOS 4
-
-#define NAND_JFFS2_OOB8_FSDAPOS 6
-#define NAND_JFFS2_OOB16_FSDAPOS 8
-#define NAND_JFFS2_OOB8_FSDALEN 2
-#define NAND_JFFS2_OOB16_FSDALEN 8
-
-unsigned long nand_probe(unsigned long physadr);
-#endif /* __LINUX_MTD_NAND_LEGACY_H */
diff --git a/include/lzma/LzmaDecode.h b/include/lzma/LzmaDec.h
index 8fdb2c0..967cdd1 100644
--- a/include/lzma/LzmaDecode.h
+++ b/include/lzma/LzmaDec.h
@@ -1,7 +1,7 @@
/*
- * Fake include for LzmaDecode.h
+ * Fake include for LzmaDec.h
*
- * Copyright (C) 2007-2008 Industrie Dial Face S.p.A.
+ * Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
*
* See file CREDITS for list of people who contributed to this
@@ -23,9 +23,9 @@
* MA 02111-1307 USA
*/
-#ifndef __LZMADECODE_H__FAKE__
-#define __LZMADECODE_H__FAKE__
+#ifndef __LZMADEC_H__FAKE__
+#define __LZMADEC_H__FAKE__
-#include "../../lib_generic/lzma/LzmaDecode.h"
+#include "../../lib_generic/lzma/LzmaDec.h"
#endif
diff --git a/include/lzma/LzmaTools.h b/include/lzma/LzmaTools.h
index 7c5eea1..87943c0 100644
--- a/include/lzma/LzmaTools.h
+++ b/include/lzma/LzmaTools.h
@@ -1,7 +1,7 @@
/*
* Fake include for LzmaTools.h
*
- * Copyright (C) 2007-2008 Industrie Dial Face S.p.A.
+ * Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
*
* See file CREDITS for list of people who contributed to this
diff --git a/include/lzma/LzmaTypes.h b/include/lzma/LzmaTypes.h
index 02daa59..86160a4 100644
--- a/include/lzma/LzmaTypes.h
+++ b/include/lzma/LzmaTypes.h
@@ -1,7 +1,7 @@
/*
- * Fake include for LzmaTypes.h
+ * Fake include for Types.h
*
- * Copyright (C) 2007-2008 Industrie Dial Face S.p.A.
+ * Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
*
* See file CREDITS for list of people who contributed to this
@@ -23,9 +23,14 @@
* MA 02111-1307 USA
*/
-#ifndef __LZMATYPES_H__FAKE__
-#define __LZMATYPES_H__FAKE__
+#ifndef __TYPES_H__FAKE__
+#define __TYPES_H__FAKE__
-#include "../../lib_generic/lzma/LzmaTypes.h"
+/*
+ *This avoids the collition with zlib.h Byte definition
+ */
+#define Byte LZByte
+
+#include "../../lib_generic/lzma/Types.h"
#endif
diff --git a/include/malloc.h b/include/malloc.h
index 47154b0..a38464e 100644
--- a/include/malloc.h
+++ b/include/malloc.h
@@ -216,7 +216,8 @@
*/
-
+#ifndef __MALLOC_H__
+#define __MALLOC_H__
/* Preliminaries */
@@ -940,3 +941,5 @@ struct mallinfo mALLINFo();
#ifdef __cplusplus
}; /* end of extern "C" */
#endif
+
+#endif /* __MALLOC_H__ */
diff --git a/include/mb862xx.h b/include/mb862xx.h
index 164305f..43f01e7 100644
--- a/include/mb862xx.h
+++ b/include/mb862xx.h
@@ -32,6 +32,75 @@
#define PCI_DEVICE_ID_CORAL_P 0x2019
#define PCI_DEVICE_ID_CORAL_PA 0x201E
+#define GC_HOST_BASE 0x01fc0000
+#define GC_DISP_BASE 0x01fd0000
+#define GC_DRAW_BASE 0x01ff0000
+
+/* Host interface registers */
+#define GC_SRST 0x0000002c
+#define GC_CCF 0x00000038
+#define GC_MMR 0x0000fffc
+
+/*
+ * Display Controller registers
+ * _A means the offset is aligned, we use these for boards
+ * with 8-/16-bit GDC access not working or buggy.
+ */
+#define GC_DCM0 0x00000000
+#define GC_HTP_A 0x00000004
+#define GC_HTP 0x00000006
+#define GC_HDB_HDP_A 0x00000008
+#define GC_HDP 0x00000008
+#define GC_HDB 0x0000000a
+#define GC_VSW_HSW_HSP_A 0x0000000c
+#define GC_HSP 0x0000000c
+#define GC_HSW 0x0000000e
+#define GC_VSW 0x0000000f
+#define GC_VTR_A 0x00000010
+#define GC_VTR 0x00000012
+#define GC_VDP_VSP_A 0x00000014
+#define GC_VSP 0x00000014
+#define GC_VDP 0x00000016
+#define GC_WY_WX 0x00000018
+#define GC_WH_WW 0x0000001c
+#define GC_L0M 0x00000020
+#define GC_L0OA0 0x00000024
+#define GC_L0DA0 0x00000028
+#define GC_L0DY_L0DX 0x0000002c
+#define GC_L2M 0x00000040
+#define GC_L2OA0 0x00000044
+#define GC_L2DA0 0x00000048
+#define GC_L2OA1 0x0000004c
+#define GC_L2DA1 0x00000050
+#define GC_L2DX 0x00000054
+#define GC_L2DY 0x00000056
+#define GC_DCM1 0x00000100
+#define GC_DCM2 0x00000104
+#define GC_DCM3 0x00000108
+#define GC_L0EM 0x00000110
+#define GC_L0WY_L0WX 0x00000114
+#define GC_L0WH_L0WW 0x00000118
+#define GC_L2EM 0x00000130
+#define GC_L2WX 0x00000134
+#define GC_L2WY 0x00000136
+#define GC_L2WW 0x00000138
+#define GC_L2WH 0x0000013a
+#define GC_L0PAL0 0x00000400
+
+/* Drawing registers */
+#define GC_CTR 0x00000400
+#define GC_IFCNT 0x00000408
+#define GC_FBR 0x00000440
+#define GC_XRES 0x00000444
+#define GC_CXMIN 0x00000454
+#define GC_CXMAX 0x00000458
+#define GC_CYMIN 0x0000045c
+#define GC_CYMAX 0x00000460
+#define GC_FC 0x00000480
+#define GC_BC 0x00000484
+#define GC_FIFO 0x000004a0
+#define GC_GEO_FIFO 0x00008400
+
typedef struct {
unsigned int index;
unsigned int value;
diff --git a/include/nand.h b/include/nand.h
index 23f3ca1..2a81597 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -26,7 +26,6 @@
extern void nand_init(void);
-#ifndef CONFIG_NAND_LEGACY
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
@@ -130,5 +129,4 @@ void board_nand_select_device(struct nand_chip *nand, int chip);
__attribute__((noreturn)) void nand_boot(void);
-#endif /* !CONFIG_NAND_LEGACY */
#endif
diff --git a/include/net.h b/include/net.h
index 5a1d36e..4a03717 100644
--- a/include/net.h
+++ b/include/net.h
@@ -331,8 +331,8 @@ extern IPaddr_t NetOurIP; /* Our IP addr (0 = unknown) */
extern IPaddr_t NetServerIP; /* Server IP addr (0 = unknown) */
extern volatile uchar * NetTxPacket; /* THE transmit packet */
extern volatile uchar * NetRxPackets[PKTBUFSRX];/* Receive packets */
-extern volatile uchar * NetRxPkt; /* Current receive packet */
-extern int NetRxPktLen; /* Current rx packet length */
+extern volatile uchar * NetRxPacket; /* Current receive packet */
+extern int NetRxPacketLen; /* Current rx packet length */
extern unsigned NetIPID; /* IP ID (counting) */
extern uchar NetBcastAddr[6]; /* Ethernet boardcast address */
extern uchar NetEtherNullAddr[6];
@@ -361,6 +361,11 @@ typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP
/* from net/net.c */
extern char BootFile[128]; /* Boot File name */
+#if defined(CONFIG_CMD_DNS)
+extern char *NetDNSResolve; /* The host to resolve */
+extern char *NetDNSenvvar; /* the env var to put the ip into */
+#endif
+
#if defined(CONFIG_CMD_PING)
extern IPaddr_t NetPingIP; /* the ip address to ping */
#endif
diff --git a/include/netdev.h b/include/netdev.h
index aed5c4c..3e66586 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -50,6 +50,7 @@ int e1000_initialize(bd_t *bis);
int eepro100_initialize(bd_t *bis);
int eth_3com_initialize (bd_t * bis);
int fec_initialize (bd_t *bis);
+int fecmxc_initialize (bd_t *bis);
int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
int inca_switch_initialize(bd_t *bis);
@@ -71,8 +72,10 @@ int rtl8139_initialize(bd_t *bis);
int rtl8169_initialize(bd_t *bis);
int scc_initialize(bd_t *bis);
int skge_initialize(bd_t *bis);
+int smc911x_initialize(u8 dev_num, int base_addr);
int tsi108_eth_initialize(bd_t *bis);
int uec_initialize(int index);
+int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
int sh_eth_initialize(bd_t *bis);
int dm9000_initialize(bd_t *bis);
diff --git a/include/ppc405.h b/include/ppc405.h
index 917afec..a17dd35 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -32,61 +32,6 @@
#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */
#endif
-/*--------------------------------------------------------------------- */
-/* Special Purpose Registers */
-/*--------------------------------------------------------------------- */
- #define srr2 0x3de /* save/restore register 2 */
- #define srr3 0x3df /* save/restore register 3 */
-
- /*
- * 405 does not really have CSRR0/1 but SRR2/3 are used during critical
- * exception for the exact same purposes - let's alias them and have a
- * common handling in crit_return() and CRIT_EXCEPTION
- */
- #define csrr0 srr2
- #define csrr1 srr3
-
- #define dbsr 0x3f0 /* debug status register */
- #define dbcr0 0x3f2 /* debug control register 0 */
- #define dbcr1 0x3bd /* debug control register 1 */
- #define iac1 0x3f4 /* instruction address comparator 1 */
- #define iac2 0x3f5 /* instruction address comparator 2 */
- #define iac3 0x3b4 /* instruction address comparator 3 */
- #define iac4 0x3b5 /* instruction address comparator 4 */
- #define dac1 0x3f6 /* data address comparator 1 */
- #define dac2 0x3f7 /* data address comparator 2 */
- #define dccr 0x3fa /* data cache control register */
- #define iccr 0x3fb /* instruction cache control register */
- #define esr 0x3d4 /* execption syndrome register */
- #define dear 0x3d5 /* data exeption address register */
- #define evpr 0x3d6 /* exeption vector prefix register */
- #define tsr 0x3d8 /* timer status register */
- #define tcr 0x3da /* timer control register */
- #define pit 0x3db /* programmable interval timer */
- #define sgr 0x3b9 /* storage guarded reg */
- #define dcwr 0x3ba /* data cache write-thru reg*/
- #define sler 0x3bb /* storage little-endian reg */
- #define cdbcr 0x3d7 /* cache debug cntrl reg */
- #define icdbdr 0x3d3 /* instr cache dbug data reg*/
- #define ccr0 0x3b3 /* core configuration register */
- #define dvc1 0x3b6 /* data value compare register 1 */
- #define dvc2 0x3b7 /* data value compare register 2 */
- #define pid 0x3b1 /* process ID */
- #define su0r 0x3bc /* storage user-defined register 0 */
- #define zpr 0x3b0 /* zone protection regsiter */
-
- #define tbl 0x11c /* time base lower - privileged write */
- #define tbu 0x11d /* time base upper - privileged write */
-
- #define sprg4r 0x104 /* Special purpose general 4 - read only */
- #define sprg5r 0x105 /* Special purpose general 5 - read only */
- #define sprg6r 0x106 /* Special purpose general 6 - read only */
- #define sprg7r 0x107 /* Special purpose general 7 - read only */
- #define sprg4w 0x114 /* Special purpose general 4 - write only */
- #define sprg5w 0x115 /* Special purpose general 5 - write only */
- #define sprg6w 0x116 /* Special purpose general 6 - write only */
- #define sprg7w 0x117 /* Special purpose general 7 - write only */
-
/******************************************************************************
* Special for PPC405GP
******************************************************************************/
diff --git a/include/ppc440.h b/include/ppc440.h
index 01f6eaf..e6dc740 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -48,99 +48,6 @@
#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
-/*--------------------------------------------------------------------- */
-/* Special Purpose Registers */
-/*--------------------------------------------------------------------- */
-#define xer_reg 0x001
-#define lr_reg 0x008
-#define dec 0x016 /* decrementer */
-#define srr0 0x01a /* save/restore register 0 */
-#define srr1 0x01b /* save/restore register 1 */
-#define pid 0x030 /* process id */
-#define decar 0x036 /* decrementer auto-reload */
-#define csrr0 0x03a /* critical save/restore register 0 */
-#define csrr1 0x03b /* critical save/restore register 1 */
-#define dear 0x03d /* data exception address register */
-#define esr 0x03e /* exception syndrome register */
-#define ivpr 0x03f /* interrupt prefix register */
-#define usprg0 0x100 /* user special purpose register general 0 */
-#define usprg1 0x110 /* user special purpose register general 1 */
-#define tblr 0x10c /* time base lower, read only */
-#define tbur 0x10d /* time base upper, read only */
-#define sprg1 0x111 /* special purpose register general 1 */
-#define sprg2 0x112 /* special purpose register general 2 */
-#define sprg3 0x113 /* special purpose register general 3 */
-#define sprg4 0x114 /* special purpose register general 4 */
-#define sprg5 0x115 /* special purpose register general 5 */
-#define sprg6 0x116 /* special purpose register general 6 */
-#define sprg7 0x117 /* special purpose register general 7 */
-#define tbl 0x11c /* time base lower (supervisor)*/
-#define tbu 0x11d /* time base upper (supervisor)*/
-#define pir 0x11e /* processor id register */
-#define dbsr 0x130 /* debug status register */
-#define dbcr0 0x134 /* debug control register 0 */
-#define dbcr1 0x135 /* debug control register 1 */
-#define dbcr2 0x136 /* debug control register 2 */
-#define iac1 0x138 /* instruction address compare 1 */
-#define iac2 0x139 /* instruction address compare 2 */
-#define iac3 0x13a /* instruction address compare 3 */
-#define iac4 0x13b /* instruction address compare 4 */
-#define dac1 0x13c /* data address compare 1 */
-#define dac2 0x13d /* data address compare 2 */
-#define dvc1 0x13e /* data value compare 1 */
-#define dvc2 0x13f /* data value compare 2 */
-#define tsr 0x150 /* timer status register */
-#define tcr 0x154 /* timer control register */
-#define ivor0 0x190 /* interrupt vector offset register 0 */
-#define ivor1 0x191 /* interrupt vector offset register 1 */
-#define ivor2 0x192 /* interrupt vector offset register 2 */
-#define ivor3 0x193 /* interrupt vector offset register 3 */
-#define ivor4 0x194 /* interrupt vector offset register 4 */
-#define ivor5 0x195 /* interrupt vector offset register 5 */
-#define ivor6 0x196 /* interrupt vector offset register 6 */
-#define ivor7 0x197 /* interrupt vector offset register 7 */
-#define ivor8 0x198 /* interrupt vector offset register 8 */
-#define ivor9 0x199 /* interrupt vector offset register 9 */
-#define ivor10 0x19a /* interrupt vector offset register 10 */
-#define ivor11 0x19b /* interrupt vector offset register 11 */
-#define ivor12 0x19c /* interrupt vector offset register 12 */
-#define ivor13 0x19d /* interrupt vector offset register 13 */
-#define ivor14 0x19e /* interrupt vector offset register 14 */
-#define ivor15 0x19f /* interrupt vector offset register 15 */
-#if defined(CONFIG_440)
-#define mcsrr0 0x23a /* machine check save/restore register 0 */
-#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
-#define mcsr 0x23c /* machine check status register */
-#endif
-#define inv0 0x370 /* instruction cache normal victim 0 */
-#define inv1 0x371 /* instruction cache normal victim 1 */
-#define inv2 0x372 /* instruction cache normal victim 2 */
-#define inv3 0x373 /* instruction cache normal victim 3 */
-#define itv0 0x374 /* instruction cache transient victim 0 */
-#define itv1 0x375 /* instruction cache transient victim 1 */
-#define itv2 0x376 /* instruction cache transient victim 2 */
-#define itv3 0x377 /* instruction cache transient victim 3 */
-#define dnv0 0x390 /* data cache normal victim 0 */
-#define dnv1 0x391 /* data cache normal victim 1 */
-#define dnv2 0x392 /* data cache normal victim 2 */
-#define dnv3 0x393 /* data cache normal victim 3 */
-#define dtv0 0x394 /* data cache transient victim 0 */
-#define dtv1 0x395 /* data cache transient victim 1 */
-#define dtv2 0x396 /* data cache transient victim 2 */
-#define dtv3 0x397 /* data cache transient victim 3 */
-#define dvlim 0x398 /* data cache victim limit */
-#define ivlim 0x399 /* instruction cache victim limit */
-#define rstcfg 0x39b /* reset configuration */
-#define dcdbtrl 0x39c /* data cache debug tag register low */
-#define dcdbtrh 0x39d /* data cache debug tag register high */
-#define icdbtrl 0x39e /* instruction cache debug tag register low */
-#define icdbtrh 0x39f /* instruction cache debug tag register high */
-#define mmucr 0x3b2 /* mmu control register */
-#define ccr0 0x3b3 /* core configuration register 0 */
-#define ccr1 0x378 /* core configuration for 440x5 only */
-#define icdbdr 0x3d3 /* instruction cache debug data register */
-#define dbdr 0x3f3 /* debug data register */
-
/******************************************************************************
* DCRs & Related
******************************************************************************/
@@ -1249,6 +1156,11 @@
#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
+#define SDR0_ECID0 0x0080
+#define SDR0_ECID1 0x0081
+#define SDR0_ECID2 0x0082
+#define SDR0_ECID3 0x0083
+
/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */
#define SDR0_ETH_PLL 0x4102
#define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/
diff --git a/include/serial.h b/include/serial.h
index 57223372..821b583 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -55,7 +55,7 @@ extern struct serial_device serial_btuart_device;
extern struct serial_device serial_stuart_device;
extern void serial_initialize(void);
-extern void serial_devices_init(void);
+extern void serial_stdio_init(void);
extern int serial_assign(char * name);
extern void serial_reinit_all(void);
diff --git a/include/devices.h b/include/stdio_dev.h
index 3a9881b..83da4cd 100644
--- a/include/devices.h
+++ b/include/stdio_dev.h
@@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -21,13 +21,13 @@
* MA 02111-1307 USA
*/
-#include <linux/list.h>
+#ifndef _STDIO_DEV_H_
+#define _STDIO_DEV_H_
-#ifndef _DEVICES_H_
-#define _DEVICES_H_
+#include <linux/list.h>
/*
- * CONSOLE DEVICES
+ * STDIO DEVICES
*/
#define DEV_FLAGS_INPUT 0x00000001 /* Device can be used as input console */
@@ -36,7 +36,7 @@
#define DEV_EXT_VIDEO 0x00000001 /* Video extensions supported */
/* Device information */
-typedef struct {
+struct stdio_dev {
int flags; /* Device flags: input/output/system */
int ext; /* Supported extensions */
char name[16]; /* Device name */
@@ -60,7 +60,7 @@ typedef struct {
void *priv; /* Private extensions */
struct list_head list;
-} device_t;
+};
/*
* VIDEO EXTENSIONS
@@ -83,20 +83,21 @@ typedef struct {
/*
* VARIABLES
*/
-extern device_t *stdio_devices[];
+extern struct stdio_dev *stdio_devices[];
extern char *stdio_names[MAX_FILES];
/*
* PROTOTYPES
*/
-int device_register (device_t * dev);
-int devices_init (void);
-#ifdef CONFIG_SYS_DEVICE_DEREGISTER
-int device_deregister(char *devname);
+int stdio_register (struct stdio_dev * dev);
+int stdio_init (void);
+void stdio_print_current_devices(void);
+#ifdef CONFIG_SYS_STDIO_DEREGISTER
+int stdio_deregister(char *devname);
#endif
-struct list_head* device_get_list(void);
-device_t* device_get_by_name(char* name);
-device_t* device_clone(device_t *dev);
+struct list_head* stdio_get_list(void);
+struct stdio_dev* stdio_get_by_name(char* name);
+struct stdio_dev* stdio_clone(struct stdio_dev *dev);
#ifdef CONFIG_ARM_DCC_MULTI
int drv_arm_dcc_init(void);
@@ -123,4 +124,4 @@ int drv_nc_init (void);
int drv_jtag_console_init (void);
#endif
-#endif /* _DEVICES_H_ */
+#endif
diff --git a/include/tsi148.h b/include/tsi148.h
new file mode 100644
index 0000000..8e8e12b
--- /dev/null
+++ b/include/tsi148.h
@@ -0,0 +1,218 @@
+/*
+ * (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com
+ *
+ * base on universe.h by
+ *
+ * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _tsi148_h
+#define _tsi148_h
+
+#ifndef PCI_DEVICE_ID_TUNDRA_TSI148
+#define PCI_DEVICE_ID_TUNDRA_TSI148 0x0148
+#endif
+
+typedef struct _TSI148 TSI148;
+typedef struct _OUTBOUND OUTBOUND;
+typedef struct _INBOUND INBOUND;
+typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET;
+
+struct _OUTBOUND {
+ unsigned int otsau; /* 0x000 Outbound start upper */
+ unsigned int otsal; /* 0x004 Outbouud start lower */
+ unsigned int oteau; /* 0x008 Outbound end upper */
+ unsigned int oteal; /* 0x00c Outbound end lower */
+ unsigned int otofu; /* 0x010 Outbound translation upper */
+ unsigned int otofl; /* 0x014 Outbound translation lower */
+ unsigned int otbs; /* 0x018 Outbound translation 2eSST */
+ unsigned int otat; /* 0x01c Outbound translation attr */
+};
+
+struct _INBOUND {
+ unsigned int itsau; /* 0x000 inbound start upper */
+ unsigned int itsal; /* 0x004 inbouud start lower */
+ unsigned int iteau; /* 0x008 inbound end upper */
+ unsigned int iteal; /* 0x00c inbound end lower */
+ unsigned int itofu; /* 0x010 inbound translation upper */
+ unsigned int itofl; /* 0x014 inbound translation lower */
+ unsigned int itat; /* 0x018 inbound translation attr */
+ unsigned int spare; /* 0x01c not used */
+};
+
+struct _TSI148 {
+ unsigned int pci_id; /* 0x000 */
+ unsigned int pci_csr; /* 0x004 */
+ unsigned int pci_class; /* 0x008 */
+ unsigned int pci_misc0; /* 0x00c */
+ unsigned int pci_mbarl; /* 0x010 */
+ unsigned int pci_mbarh; /* 0x014 */
+ unsigned int spare0[(0x03c-0x018)/4]; /* 0x018 */
+ unsigned int pci_misc1; /* 0x03c */
+ unsigned int pci_pcixcap; /* 0x040 */
+ unsigned int pci_pcixstat; /* 0x044 */
+ unsigned int spare1[(0x100-0x048)/4]; /* 0x048 */
+ OUTBOUND outbound[8]; /* 0x100 */
+ unsigned int viack[8]; /* 0x204 */
+ unsigned int rmwau; /* 0x220 */
+ unsigned int rmwal; /* 0x224 */
+ unsigned int rmwen; /* 0x228 */
+ unsigned int rmwc; /* 0x22c */
+ unsigned int rmws; /* 0x230 */
+ unsigned int vmctrl; /* 0x234 */
+ unsigned int vctrl; /* 0x238 */
+ unsigned int vstat; /* 0x23c */
+ unsigned int pcsr; /* 0x240 */
+ unsigned int spare2[3]; /* 0x244 - 0x24c */
+ unsigned int vmefl; /* 0x250 */
+ unsigned int spare3[3]; /* 0x254 - 0x25c */
+ unsigned int veau; /* 0x260 */
+ unsigned int veal; /* 0x264 */
+ unsigned int veat; /* 0x268 */
+ unsigned int spare4[1]; /* 0x26c */
+ unsigned int edpau; /* 0x270 */
+ unsigned int edpal; /* 0x274 */
+ unsigned int edpxa; /* 0x278 */
+ unsigned int edpxs; /* 0x27c */
+ unsigned int edpat; /* 0x280 */
+ unsigned int spare5[31]; /* 0x284 - 0x2fc */
+ INBOUND inbound[8]; /* 0x100 */
+ unsigned int gbau; /* 0x400 */
+ unsigned int gbal; /* 0x404 */
+ unsigned int gcsrat; /* 0x408 */
+ unsigned int cbau; /* 0x40c */
+ unsigned int cbal; /* 0x410 */
+ unsigned int crgat; /* 0x414 */
+ unsigned int crou; /* 0x418 */
+ unsigned int crol; /* 0x41c */
+ unsigned int crat; /* 0x420 */
+ unsigned int lmbau; /* 0x424 */
+ unsigned int lmbal; /* 0x428 */
+ unsigned int lmat; /* 0x42c */
+ unsigned int r64bcu; /* 0x430 */
+ unsigned int r64bcl; /* 0x434 */
+ unsigned int bpgtr; /* 0x438 */
+ unsigned int bpctr; /* 0x43c */
+ unsigned int vicr; /* 0x440 */
+ unsigned int spare6[1]; /* 0x444 */
+ unsigned int inten; /* 0x448 */
+ unsigned int inteo; /* 0x44c */
+ unsigned int ints; /* 0x450 */
+ unsigned int intc; /* 0x454 */
+ unsigned int intm1; /* 0x458 */
+ unsigned int intm2; /* 0x45c */
+ unsigned int spare7[40]; /* 0x460 - 0x4fc */
+ unsigned int dctl0; /* 0x500 */
+ unsigned int dsta0; /* 0x504 */
+ unsigned int dcsau0; /* 0x508 */
+ unsigned int dcsal0; /* 0x50c */
+ unsigned int dcdau0; /* 0x510 */
+ unsigned int dcdal0; /* 0x514 */
+ unsigned int dclau0; /* 0x518 */
+ unsigned int dclal0; /* 0x51c */
+ unsigned int dsau0; /* 0x520 */
+ unsigned int dsal0; /* 0x524 */
+ unsigned int ddau0; /* 0x528 */
+ unsigned int ddal0; /* 0x52c */
+ unsigned int dsat0; /* 0x530 */
+ unsigned int ddat0; /* 0x534 */
+ unsigned int dnlau0; /* 0x538 */
+ unsigned int dnlal0; /* 0x53c */
+ unsigned int dcnt0; /* 0x540 */
+ unsigned int ddbs0; /* 0x544 */
+ unsigned int r20[14]; /* 0x548 - 0x57c */
+ unsigned int dctl1; /* 0x580 */
+ unsigned int dsta1; /* 0x584 */
+ unsigned int dcsau1; /* 0x588 */
+ unsigned int dcsal1; /* 0x58c */
+ unsigned int dcdau1; /* 0x590 */
+ unsigned int dcdal1; /* 0x594 */
+ unsigned int dclau1; /* 0x598 */
+ unsigned int dclal1; /* 0x59c */
+ unsigned int dsau1; /* 0x5a0 */
+ unsigned int dsal1; /* 0x5a4 */
+ unsigned int ddau1; /* 0x5a8 */
+ unsigned int ddal1; /* 0x5ac */
+ unsigned int dsat1; /* 0x5b0 */
+ unsigned int ddat1; /* 0x5b4 */
+ unsigned int dnlau1; /* 0x5b8 */
+ unsigned int dnlal1; /* 0x5bc */
+ unsigned int dcnt1; /* 0x5c0 */
+ unsigned int ddbs1; /* 0x5c4 */
+ unsigned int r21[14]; /* 0x5c8 - 0x5fc */
+ unsigned int devi_veni_2; /* 0x600 */
+ unsigned int gctrl_ga_revid; /* 0x604 */
+ unsigned int semaphore0_1_2_3; /* 0x608 */
+ unsigned int semaphore4_5_6_7; /* 0x60c */
+ unsigned int mbox0; /* 0x610 */
+ unsigned int mbox1; /* 0x614 */
+ unsigned int mbox2; /* 0x618 */
+ unsigned int mbox3; /* 0x61c */
+ unsigned int r22[629]; /* 0x620 - 0xff0 */
+ unsigned int csrbcr; /* 0xff4 */
+ unsigned int csrbsr; /* 0xff8 */
+ unsigned int cbar; /* 0xffc */
+};
+
+#define IRQ_VOWN 0x0001
+#define IRQ_VIRQ1 0x0002
+#define IRQ_VIRQ2 0x0004
+#define IRQ_VIRQ3 0x0008
+#define IRQ_VIRQ4 0x0010
+#define IRQ_VIRQ5 0x0020
+#define IRQ_VIRQ6 0x0040
+#define IRQ_VIRQ7 0x0080
+#define IRQ_DMA 0x0100
+#define IRQ_LERR 0x0200
+#define IRQ_VERR 0x0400
+#define IRQ_res 0x0800
+#define IRQ_IACK 0x1000
+#define IRQ_SWINT 0x2000
+#define IRQ_SYSFAIL 0x4000
+#define IRQ_ACFAIL 0x8000
+
+struct _TDMA_CMD_PACKET {
+ unsigned int dctl; /* DMA Control */
+ unsigned int dtbc; /* Transfer Byte Count */
+ unsigned int dlv; /* PCI Address */
+ unsigned int res1; /* Reserved */
+ unsigned int dva; /* Vme Address */
+ unsigned int res2; /* Reserved */
+ unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */
+ unsigned int res3; /* Reserved */
+};
+
+#define VME_AM_A16 0x01
+#define VME_AM_A24 0x02
+#define VME_AM_A32 0x03
+#define VME_AM_Axx 0x03
+#define VME_AM_USR 0x04
+#define VME_AM_SUP 0x08
+#define VME_AM_DATA 0x10
+#define VME_AM_PROG 0x20
+#define VME_AM_Mxx (VME_AM_DATA | VME_AM_PROG)
+
+#define VME_FLAG_D8 0x01
+#define VME_FLAG_D16 0x02
+#define VME_FLAG_D32 0x03
+#define VME_FLAG_Dxx 0x03
+
+#endif
diff --git a/include/twl4030.h b/include/twl4030.h
new file mode 100644
index 0000000..f260ecb
--- /dev/null
+++ b/include/twl4030.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix at windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Derived from code on omapzoom, git://git.omapzoom.com/repo/u-boot.git
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ */
+
+#ifndef TWL4030_H
+#define TWL4030_H
+
+#include <common.h>
+#include <i2c.h>
+
+/* I2C chip addresses */
+
+/* USB */
+#define TWL4030_CHIP_USB 0x48
+/* AUD */
+#define TWL4030_CHIP_AUDIO_VOICE 0x49
+#define TWL4030_CHIP_GPIO 0x49
+#define TWL4030_CHIP_INTBR 0x49
+#define TWL4030_CHIP_PIH 0x49
+#define TWL4030_CHIP_TEST 0x49
+/* AUX */
+#define TWL4030_CHIP_KEYPAD 0x4a
+#define TWL4030_CHIP_MADC 0x4a
+#define TWL4030_CHIP_INTERRUPTS 0x4a
+#define TWL4030_CHIP_LED 0x4a
+#define TWL4030_CHIP_MAIN_CHARGE 0x4a
+#define TWL4030_CHIP_PRECHARGE 0x4a
+#define TWL4030_CHIP_PWM0 0x4a
+#define TWL4030_CHIP_PWM1 0x4a
+#define TWL4030_CHIP_PWMA 0x4a
+#define TWL4030_CHIP_PWMB 0x4a
+/* POWER */
+#define TWL4030_CHIP_BACKUP 0x4b
+#define TWL4030_CHIP_INT 0x4b
+#define TWL4030_CHIP_PM_MASTER 0x4b
+#define TWL4030_CHIP_PM_RECEIVER 0x4b
+#define TWL4030_CHIP_RTC 0x4b
+#define TWL4030_CHIP_SECURED_REG 0x4b
+
+/* Register base addresses */
+
+/* USB */
+#define TWL4030_BASEADD_USB 0x0000
+/* AUD */
+#define TWL4030_BASEADD_AUDIO_VOICE 0x0000
+#define TWL4030_BASEADD_GPIO 0x0098
+#define TWL4030_BASEADD_INTBR 0x0085
+#define TWL4030_BASEADD_PIH 0x0080
+#define TWL4030_BASEADD_TEST 0x004C
+/* AUX */
+#define TWL4030_BASEADD_INTERRUPTS 0x00B9
+#define TWL4030_BASEADD_LED 0x00EE
+#define TWL4030_BASEADD_MADC 0x0000
+#define TWL4030_BASEADD_MAIN_CHARGE 0x0074
+#define TWL4030_BASEADD_PRECHARGE 0x00AA
+#define TWL4030_BASEADD_PWM0 0x00F8
+#define TWL4030_BASEADD_PWM1 0x00FB
+#define TWL4030_BASEADD_PWMA 0x00EF
+#define TWL4030_BASEADD_PWMB 0x00F1
+#define TWL4030_BASEADD_KEYPAD 0x00D2
+/* POWER */
+#define TWL4030_BASEADD_BACKUP 0x0014
+#define TWL4030_BASEADD_INT 0x002E
+#define TWL4030_BASEADD_PM_MASTER 0x0036
+#define TWL4030_BASEADD_PM_RECIEVER 0x005B
+#define TWL4030_BASEADD_RTC 0x001C
+#define TWL4030_BASEADD_SECURED_REG 0x0000
+
+/*
+ * Power Management Master
+ */
+#define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x36
+#define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x37
+#define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x38
+#define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x39
+#define TWL4030_PM_MASTER_STS_BOOT 0x3A
+#define TWL4030_PM_MASTER_CFG_BOOT 0x3B
+#define TWL4030_PM_MASTER_SHUNDAN 0x3C
+#define TWL4030_PM_MASTER_BOOT_BCI 0x3D
+#define TWL4030_PM_MASTER_CFG_PWRANA1 0x3E
+#define TWL4030_PM_MASTER_CFG_PWRANA2 0x3F
+#define TWL4030_PM_MASTER_BGAP_TRIM 0x40
+#define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x41
+#define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x42
+#define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x43
+#define TWL4030_PM_MASTER_PROTECT_KEY 0x44
+#define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x45
+#define TWL4030_PM_MASTER_P1_SW_EVENTS 0x46
+#define TWL4030_PM_MASTER_P2_SW_EVENTS 0x47
+#define TWL4030_PM_MASTER_P3_SW_EVENTS 0x48
+#define TWL4030_PM_MASTER_STS_P123_STATE 0x49
+#define TWL4030_PM_MASTER_PB_CFG 0x4A
+#define TWL4030_PM_MASTER_PB_WORD_MSB 0x4B
+#define TWL4030_PM_MASTER_PB_WORD_LSB 0x4C
+#define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x52
+#define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x53
+#define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x54
+#define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x55
+#define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x56
+#define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x57
+#define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x58
+#define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x59
+#define TWL4030_PM_MASTER_MEMORY_DATA 0x5A
+#define TWL4030_PM_MASTER_SC_CONFIG 0x5B
+#define TWL4030_PM_MASTER_SC_DETECT1 0x5C
+#define TWL4030_PM_MASTER_SC_DETECT2 0x5D
+#define TWL4030_PM_MASTER_WATCHDOG_CFG 0x5E
+#define TWL4030_PM_MASTER_IT_CHECK_CFG 0x5F
+#define TWL4030_PM_MASTER_VIBRATOR_CFG 0x60
+#define TWL4030_PM_MASTER_DCDC_GLOBAL_CFG 0x61
+#define TWL4030_PM_MASTER_VDD1_TRIM1 0x62
+#define TWL4030_PM_MASTER_VDD1_TRIM2 0x63
+#define TWL4030_PM_MASTER_VDD2_TRIM1 0x64
+#define TWL4030_PM_MASTER_VDD2_TRIM2 0x65
+#define TWL4030_PM_MASTER_VIO_TRIM1 0x66
+#define TWL4030_PM_MASTER_VIO_TRIM2 0x67
+#define TWL4030_PM_MASTER_MISC_CFG 0x68
+#define TWL4030_PM_MASTER_LS_TST_A 0x69
+#define TWL4030_PM_MASTER_LS_TST_B 0x6A
+#define TWL4030_PM_MASTER_LS_TST_C 0x6B
+#define TWL4030_PM_MASTER_LS_TST_D 0x6C
+#define TWL4030_PM_MASTER_BB_CFG 0x6D
+#define TWL4030_PM_MASTER_MISC_TST 0x6E
+#define TWL4030_PM_MASTER_TRIM1 0x6F
+/* P[1-3]_SW_EVENTS */
+#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON (1 << 6)
+#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN (1 << 5)
+#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET (1 << 4)
+#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP (1 << 3)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT (1 << 2)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0)
+
+/* Power Managment Receiver */
+#define TWL4030_PM_RECEIVER_SC_CONFIG 0x5B
+#define TWL4030_PM_RECEIVER_SC_DETECT1 0x5C
+#define TWL4030_PM_RECEIVER_SC_DETECT2 0x5D
+#define TWL4030_PM_RECEIVER_WATCHDOG_CFG 0x5E
+#define TWL4030_PM_RECEIVER_IT_CHECK_CFG 0x5F
+#define TWL4030_PM_RECEIVER_VIBRATOR_CFG 0x5F
+#define TWL4030_PM_RECEIVER_DC_TO_DC_CFG 0x61
+#define TWL4030_PM_RECEIVER_VDD1_TRIM1 0x62
+#define TWL4030_PM_RECEIVER_VDD1_TRIM2 0x63
+#define TWL4030_PM_RECEIVER_VDD2_TRIM1 0x64
+#define TWL4030_PM_RECEIVER_VDD2_TRIM2 0x65
+#define TWL4030_PM_RECEIVER_VIO_TRIM1 0x66
+#define TWL4030_PM_RECEIVER_VIO_TRIM2 0x67
+#define TWL4030_PM_RECEIVER_MISC_CFG 0x68
+#define TWL4030_PM_RECEIVER_LS_TST_A 0x69
+#define TWL4030_PM_RECEIVER_LS_TST_B 0x6A
+#define TWL4030_PM_RECEIVER_LS_TST_C 0x6B
+#define TWL4030_PM_RECEIVER_LS_TST_D 0x6C
+#define TWL4030_PM_RECEIVER_BB_CFG 0x6D
+#define TWL4030_PM_RECEIVER_MISC_TST 0x6E
+#define TWL4030_PM_RECEIVER_TRIM1 0x6F
+#define TWL4030_PM_RECEIVER_TRIM2 0x70
+#define TWL4030_PM_RECEIVER_DC_DC_TIMEOUT 0x71
+#define TWL4030_PM_RECEIVER_VAUX1_DEV_GRP 0x72
+#define TWL4030_PM_RECEIVER_VAUX1_TYPE 0x73
+#define TWL4030_PM_RECEIVER_VAUX1_REMAP 0x74
+#define TWL4030_PM_RECEIVER_VAUX1_DEDICATED 0x75
+#define TWL4030_PM_RECEIVER_VAUX2_DEV_GRP 0x76
+#define TWL4030_PM_RECEIVER_VAUX2_TYPE 0x77
+#define TWL4030_PM_RECEIVER_VAUX2_REMAP 0x78
+#define TWL4030_PM_RECEIVER_VAUX2_DEDICATED 0x79
+#define TWL4030_PM_RECEIVER_VAUX3_DEV_GRP 0x7A
+#define TWL4030_PM_RECEIVER_VAUX3_TYPE 0x7B
+#define TWL4030_PM_RECEIVER_VAUX3_REMAP 0x7C
+#define TWL4030_PM_RECEIVER_VAUX3_DEDICATED 0x7D
+#define TWL4030_PM_RECEIVER_VAUX4_DEV_GRP 0x7E
+#define TWL4030_PM_RECEIVER_VAUX4_TYPE 0x7F
+#define TWL4030_PM_RECEIVER_VAUX4_REMAP 0x80
+#define TWL4030_PM_RECEIVER_VAUX4_DEDICATED 0x81
+#define TWL4030_PM_RECEIVER_VMMC1_DEV_GRP 0x82
+#define TWL4030_PM_RECEIVER_VMMC1_TYPE 0x83
+#define TWL4030_PM_RECEIVER_VMMC1_REMAP 0x84
+#define TWL4030_PM_RECEIVER_VMMC1_DEDICATED 0x85
+#define TWL4030_PM_RECEIVER_VMMC2_DEV_GRP 0x86
+#define TWL4030_PM_RECEIVER_VMMC2_TYPE 0x87
+#define TWL4030_PM_RECEIVER_VMMC2_REMAP 0x88
+#define TWL4030_PM_RECEIVER_VMMC2_DEDICATED 0x89
+#define TWL4030_PM_RECEIVER_VPLL1_DEV_GRP 0x8A
+#define TWL4030_PM_RECEIVER_VPLL1_TYPE 0x8B
+#define TWL4030_PM_RECEIVER_VPLL1_REMAP 0x8C
+#define TWL4030_PM_RECEIVER_VPLL1_DEDICATED 0x8D
+#define TWL4030_PM_RECEIVER_VPLL2_DEV_GRP 0x8E
+#define TWL4030_PM_RECEIVER_VPLL2_TYPE 0x8F
+#define TWL4030_PM_RECEIVER_VPLL2_REMAP 0x90
+#define TWL4030_PM_RECEIVER_VPLL2_DEDICATED 0x91
+#define TWL4030_PM_RECEIVER_VSIM_DEV_GRP 0x92
+#define TWL4030_PM_RECEIVER_VSIM_TYPE 0x93
+#define TWL4030_PM_RECEIVER_VSIM_REMAP 0x94
+#define TWL4030_PM_RECEIVER_VSIM_DEDICATED 0x95
+#define TWL4030_PM_RECEIVER_VDAC_DEV_GRP 0x96
+#define TWL4030_PM_RECEIVER_VDAC_TYPE 0x97
+#define TWL4030_PM_RECEIVER_VDAC_REMAP 0x98
+#define TWL4030_PM_RECEIVER_VDAC_DEDICATED 0x99
+#define TWL4030_PM_RECEIVER_VINTANA1_DEV_GRP 0x9A
+#define TWL4030_PM_RECEIVER_VINTANA1_TYP 0x9B
+#define TWL4030_PM_RECEIVER_VINTANA1_REMAP 0x9C
+#define TWL4030_PM_RECEIVER_VINTANA1_DEDICATED 0x9D
+#define TWL4030_PM_RECEIVER_VINTANA2_DEV_GRP 0x9E
+#define TWL4030_PM_RECEIVER_VINTANA2_TYPE 0x9F
+#define TWL4030_PM_RECEIVER_VINTANA2_REMAP 0xA0
+#define TWL4030_PM_RECEIVER_VINTANA2_DEDICATED 0xA1
+#define TWL4030_PM_RECEIVER_VINTDIG_DEV_GRP 0xA2
+#define TWL4030_PM_RECEIVER_VINTDIG_TYPE 0xA3
+#define TWL4030_PM_RECEIVER_VINTDIG_REMAP 0xA4
+#define TWL4030_PM_RECEIVER_VINTDIG_DEDICATED 0xA5
+#define TWL4030_PM_RECEIVER_VIO_DEV_GRP 0xA6
+#define TWL4030_PM_RECEIVER_VIO_TYPE 0xA7
+#define TWL4030_PM_RECEIVER_VIO_REMAP 0xA8
+#define TWL4030_PM_RECEIVER_VIO_CFG 0xA9
+#define TWL4030_PM_RECEIVER_VIO_MISC_CFG 0xAA
+#define TWL4030_PM_RECEIVER_VIO_TEST1 0xAB
+#define TWL4030_PM_RECEIVER_VIO_TEST2 0xAC
+#define TWL4030_PM_RECEIVER_VIO_OSC 0xAD
+#define TWL4030_PM_RECEIVER_VIO_RESERVED 0xAE
+#define TWL4030_PM_RECEIVER_VIO_VSEL 0xAF
+#define TWL4030_PM_RECEIVER_VDD1_DEV_GRP 0xB0
+#define TWL4030_PM_RECEIVER_VDD1_TYPE 0xB1
+#define TWL4030_PM_RECEIVER_VDD1_REMAP 0xB2
+#define TWL4030_PM_RECEIVER_VDD1_CFG 0xB3
+#define TWL4030_PM_RECEIVER_VDD1_MISC_CFG 0xB4
+#define TWL4030_PM_RECEIVER_VDD1_TEST1 0xB5
+#define TWL4030_PM_RECEIVER_VDD1_TEST2 0xB6
+#define TWL4030_PM_RECEIVER_VDD1_OSC 0xB7
+#define TWL4030_PM_RECEIVER_VDD1_RESERVED 0xB8
+#define TWL4030_PM_RECEIVER_VDD1_VSEL 0xB9
+#define TWL4030_PM_RECEIVER_VDD1_VMODE_CFG 0xBA
+#define TWL4030_PM_RECEIVER_VDD1_VFLOOR 0xBB
+#define TWL4030_PM_RECEIVER_VDD1_VROOF 0xBC
+#define TWL4030_PM_RECEIVER_VDD1_STEP 0xBD
+#define TWL4030_PM_RECEIVER_VDD2_DEV_GRP 0xBE
+#define TWL4030_PM_RECEIVER_VDD2_TYPE 0xBF
+#define TWL4030_PM_RECEIVER_VDD2_REMAP 0xC0
+#define TWL4030_PM_RECEIVER_VDD2_CFG 0xC1
+#define TWL4030_PM_RECEIVER_VDD2_MISC_CFG 0xC2
+#define TWL4030_PM_RECEIVER_VDD2_TEST1 0xC3
+#define TWL4030_PM_RECEIVER_VDD2_TEST2 0xC4
+#define TWL4030_PM_RECEIVER_VDD2_OSC 0xC5
+#define TWL4030_PM_RECEIVER_VDD2_RESERVED 0xC6
+#define TWL4030_PM_RECEIVER_VDD2_VSEL 0xC7
+#define TWL4030_PM_RECEIVER_VDD2_VMODE_CFG 0xC8
+#define TWL4030_PM_RECEIVER_VDD2_VFLOOR 0xC9
+#define TWL4030_PM_RECEIVER_VDD2_VROOF 0xCA
+#define TWL4030_PM_RECEIVER_VDD2_STEP 0xCB
+#define TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP 0xCC
+#define TWL4030_PM_RECEIVER_VUSB1V5_TYPE 0xCD
+#define TWL4030_PM_RECEIVER_VUSB1V5_REMAP 0xCE
+#define TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP 0xCF
+#define TWL4030_PM_RECEIVER_VUSB1V8_TYPE 0xD0
+#define TWL4030_PM_RECEIVER_VUSB1V8_REMAP 0xD1
+#define TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP 0xD2
+#define TWL4030_PM_RECEIVER_VUSB3V1_TYPE 0xD3
+#define TWL4030_PM_RECEIVER_VUSB3V1_REMAP 0xD4
+#define TWL4030_PM_RECEIVER_VUSBCP_DEV_GRP 0xD5
+#define TWL4030_PM_RECEIVER_VUSBCP_TYPE 0xD6
+#define TWL4030_PM_RECEIVER_VUSBCP_REMAP 0xD7
+#define TWL4030_PM_RECEIVER_VUSB_DEDICATED1 0xD8
+#define TWL4030_PM_RECEIVER_VUSB_DEDICATED2 0xD9
+#define TWL4030_PM_RECEIVER_REGEN_DEV_GRP 0xDA
+#define TWL4030_PM_RECEIVER_REGEN_TYPE 0xDB
+#define TWL4030_PM_RECEIVER_REGEN_REMAP 0xDC
+#define TWL4030_PM_RECEIVER_NRESPWRON_DEV_GRP 0xDD
+#define TWL4030_PM_RECEIVER_NRESPWRON_TYPE 0xDE
+#define TWL4030_PM_RECEIVER_NRESPWRON_REMAP 0xDF
+#define TWL4030_PM_RECEIVER_CLKEN_DEV_GRP 0xE0
+#define TWL4030_PM_RECEIVER_CLKEN_TYPE 0xE1
+#define TWL4030_PM_RECEIVER_CLKEN_REMAP 0xE2
+#define TWL4030_PM_RECEIVER_SYSEN_DEV_GRP 0xE3
+#define TWL4030_PM_RECEIVER_SYSEN_TYPE 0xE4
+#define TWL4030_PM_RECEIVER_SYSEN_REMAP 0xE5
+#define TWL4030_PM_RECEIVER_HFCLKOUT_DEV_GRP 0xE6
+#define TWL4030_PM_RECEIVER_HFCLKOUT_TYPE 0xE7
+#define TWL4030_PM_RECEIVER_HFCLKOUT_REMAP 0xE8
+#define TWL4030_PM_RECEIVER_32KCLKOUT_DEV_GRP 0xE9
+#define TWL4030_PM_RECEIVER_32KCLKOUT_TYPE 0xEA
+#define TWL4030_PM_RECEIVER_32KCLKOUT_REMAP 0xEB
+#define TWL4030_PM_RECEIVER_TRITON_RESET_DEV_GRP 0xEC
+#define TWL4030_PM_RECEIVER_TRITON_RESET_TYPE 0xED
+#define TWL4030_PM_RECEIVER_TRITON_RESET_REMAP 0xEE
+#define TWL4030_PM_RECEIVER_MAINREF_DEV_GRP 0xEF
+#define TWL4030_PM_RECEIVER_MAINREF_TYPE 0xF0
+#define TWL4030_PM_RECEIVER_MAINREF_REMAP 0xF1
+
+/* LED */
+#define TWL4030_LED_LEDEN 0xEE
+
+/* Keypad */
+#define TWL4030_KEYPAD_KEYP_CTRL_REG 0xD2
+#define TWL4030_KEYPAD_KEY_DEB_REG 0xD3
+#define TWL4030_KEYPAD_LONG_KEY_REG1 0xD4
+#define TWL4030_KEYPAD_LK_PTV_REG 0xD5
+#define TWL4030_KEYPAD_TIME_OUT_REG1 0xD6
+#define TWL4030_KEYPAD_TIME_OUT_REG2 0xD7
+#define TWL4030_KEYPAD_KBC_REG 0xD8
+#define TWL4030_KEYPAD_KBR_REG 0xD9
+#define TWL4030_KEYPAD_KEYP_SMS 0xDA
+#define TWL4030_KEYPAD_FULL_CODE_7_0 0xDB
+#define TWL4030_KEYPAD_FULL_CODE_15_8 0xDC
+#define TWL4030_KEYPAD_FULL_CODE_23_16 0xDD
+#define TWL4030_KEYPAD_FULL_CODE_31_24 0xDE
+#define TWL4030_KEYPAD_FULL_CODE_39_32 0xDF
+#define TWL4030_KEYPAD_FULL_CODE_47_40 0xE0
+#define TWL4030_KEYPAD_FULL_CODE_55_48 0xE1
+#define TWL4030_KEYPAD_FULL_CODE_63_56 0xE2
+#define TWL4030_KEYPAD_KEYP_ISR1 0xE3
+#define TWL4030_KEYPAD_KEYP_IMR1 0xE4
+#define TWL4030_KEYPAD_KEYP_ISR2 0xE5
+#define TWL4030_KEYPAD_KEYP_IMR2 0xE6
+#define TWL4030_KEYPAD_KEYP_SIR 0xE7
+#define TWL4030_KEYPAD_KEYP_EDR 0xE8
+#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0xE9
+
+#define TWL4030_KEYPAD_CTRL_KBD_ON (1 << 6)
+#define TWL4030_KEYPAD_CTRL_RP_EN (1 << 5)
+#define TWL4030_KEYPAD_CTRL_TOLE_EN (1 << 4)
+#define TWL4030_KEYPAD_CTRL_TOE_EN (1 << 3)
+#define TWL4030_KEYPAD_CTRL_LK_EN (1 << 2)
+#define TWL4030_KEYPAD_CTRL_SOFTMODEN (1 << 1)
+#define TWL4030_KEYPAD_CTRL_SOFT_NRST (1 << 0)
+
+/* USB */
+#define TWL4030_USB_FUNC_CTRL (0x04)
+#define TWL4030_USB_OPMODE_MASK (3 << 3)
+#define TWL4030_USB_XCVRSELECT_MASK (3 << 0)
+#define TWL4030_USB_IFC_CTRL (0x07)
+#define TWL4030_USB_CARKITMODE (1 << 2)
+#define TWL4030_USB_POWER_CTRL (0xAC)
+#define TWL4030_USB_OTG_ENAB (1 << 5)
+#define TWL4030_USB_PHY_PWR_CTRL (0xFD)
+#define TWL4030_USB_PHYPWD (1 << 0)
+#define TWL4030_USB_PHY_CLK_CTRL (0xFE)
+#define TWL4030_USB_CLOCKGATING_EN (1 << 2)
+#define TWL4030_USB_CLK32K_EN (1 << 1)
+#define TWL4030_USB_REQ_PHY_DPLL_CLK (1 << 0)
+#define TWL4030_USB_PHY_CLK_CTRL_STS (0xFF)
+#define TWL4030_USB_PHY_DPLL_CLK (1 << 0)
+
+/*
+ * Convience functions to read and write from TWL4030
+ *
+ * chip_no is the i2c address, it must be one of the chip addresses
+ * defined at the top of this file with the prefix TWL4030_CHIP_
+ * examples are TWL4030_CHIP_PM_RECEIVER and TWL4030_CHIP_KEYPAD
+ *
+ * val is the data either written to or read from the twl4030
+ *
+ * reg is the register to act on, it must be one of the defines
+ * above and with the format TWL4030_<chip suffix>_<register name>
+ * examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and
+ * TWL4030_LED_LEDEN.
+ */
+static inline int twl4030_i2c_write_u8(u8 chip_no, u8 val, u8 reg)
+{
+ return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int twl4030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg)
+{
+ return i2c_read(chip_no, reg, 1, val, 1);
+}
+
+/*
+ * Power
+ */
+
+/* For hardware resetting */
+void twl4030_power_reset_init(void);
+/* For initializing power device */
+void twl4030_power_init(void);
+/* For initializing mmc power */
+void twl4030_power_mmc_init(void);
+
+/*
+ * LED
+ */
+void twl4030_led_init(void);
+
+#endif /* TWL4030_H */
diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h
index 8b44a7f..08924cc 100644
--- a/include/u-boot/md5.h
+++ b/include/u-boot/md5.h
@@ -6,7 +6,7 @@
#ifndef _MD5_H
#define _MD5_H
-#include <linux/types.h>
+#include "compiler.h"
struct MD5Context {
__u32 buf[4];