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-rw-r--r--include/common.h5
-rw-r--r--include/configs/MPC8610HPCD.h10
-rw-r--r--include/configs/P1022DS.h8
-rw-r--r--include/configs/a320evb.h1
-rw-r--r--include/configs/ca9x4_ct_vxp.h6
-rw-r--r--include/configs/devkit8000.h2
-rw-r--r--include/configs/efikamx.h2
-rw-r--r--include/configs/igep0020.h2
-rw-r--r--include/configs/igep0030.h2
-rw-r--r--include/configs/keymile-common.h489
-rw-r--r--include/configs/km-powerpc.h92
-rw-r--r--include/configs/km82xx-common.h336
-rw-r--r--include/configs/km8321-common.h137
-rw-r--r--include/configs/km83xx-common.h325
-rw-r--r--include/configs/km_arm.h104
-rw-r--r--include/configs/kmeter1.h368
-rw-r--r--include/configs/kmsupx5.h91
-rw-r--r--include/configs/mgcoge.h309
-rw-r--r--include/configs/mgcoge2ne.h64
-rw-r--r--include/configs/mgcoge2un.h65
-rw-r--r--include/configs/mx51evk.h2
-rw-r--r--include/configs/mx53evk.h2
-rw-r--r--include/configs/omap3_overo.h2
-rw-r--r--include/configs/omap3_pandora.h2
-rw-r--r--include/configs/omap3_sdp3430.h2
-rw-r--r--include/configs/omap3_zoom1.h2
-rw-r--r--include/configs/omap3_zoom2.h2
-rw-r--r--include/configs/omap4_panda.h2
-rw-r--r--include/configs/omap4_sdp4430.h2
-rw-r--r--include/configs/pdm360ng.h2
-rw-r--r--include/configs/suen3.h45
-rw-r--r--include/configs/suen8.h65
-rw-r--r--include/configs/suvd3.h104
-rw-r--r--include/configs/tegra2-common.h1
-rw-r--r--include/configs/tuda1.h141
-rw-r--r--include/configs/tuxa1.h124
-rw-r--r--include/fsl_diu_fb.h43
-rw-r--r--include/i2c.h2
-rw-r--r--include/ide.h7
-rw-r--r--include/mmc.h46
40 files changed, 2099 insertions, 917 deletions
diff --git a/include/common.h b/include/common.h
index 21c05db..00e266e 100644
--- a/include/common.h
+++ b/include/common.h
@@ -449,6 +449,11 @@ void out16(unsigned int, unsigned short value);
#if defined (CONFIG_MPC83xx)
void ppcDWload(unsigned int *addr, unsigned int *ret);
void ppcDWstore(unsigned int *addr, unsigned int *value);
+void disable_addr_trans(void);
+void enable_addr_trans(void);
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
#endif
/* $(CPU)/cpu.c */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index efe0313..31dbc3b 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2007, 2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -23,6 +23,8 @@
/* video */
+#define CONFIG_FSL_DIU_FB
+
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
#define CONFIG_VIDEO
@@ -625,8 +627,6 @@
"diuregs=md e002c000 1d\0" \
"dium=mw e002c01c\0" \
"diuerr=md e002c014 1\0" \
- "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \
- "monitor=0-DVI\0" \
"pmregs=md e00e1000 2b\0" \
"lawregs=md e0000c08 4b\0" \
"lbcregs=md e0005000 36\0" \
@@ -646,9 +646,7 @@
"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
- "bdev=sda3\0" \
- "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\
- "monitor=0-DVI\0"
+ "bdev=sda3\0"
#endif
#define CONFIG_NFSBOOTCOMMAND \
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 362abe8..a118975 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -204,6 +204,8 @@
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/* Video */
+#define CONFIG_FSL_DIU_FB
+
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
#define CONFIG_VIDEO
@@ -221,7 +223,7 @@
#undef CONFIG_SYS_FLASH_EMPTY_INFO
#endif
-#ifndef CONFIG_DIU
+#ifndef CONFIG_FSL_DIU_FB
#define CONFIG_ATI
#endif
@@ -522,9 +524,7 @@
"diuregs=md e002c000 1d\0" \
"dium=mw e002c01c\0" \
"diuerr=md e002c014 1\0" \
- "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \
- "hwconfig=esdhc;audclk:12\0" \
- "monitor=0-DVI\0"
+ "hwconfig=esdhc;audclk:12\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h
index 4b297f0..0527822 100644
--- a/include/configs/a320evb.h
+++ b/include/configs/a320evb.h
@@ -197,7 +197,6 @@
{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
}
-#endif /* CONFIG_FTSMC020 */
/*-----------------------------------------------------------------------
* FLASH and environment organization
diff --git a/include/configs/ca9x4_ct_vxp.h b/include/configs/ca9x4_ct_vxp.h
index 2a87a79..7f83249 100644
--- a/include/configs/ca9x4_ct_vxp.h
+++ b/include/configs/ca9x4_ct_vxp.h
@@ -44,6 +44,8 @@
#define CONFIG_L2_OFF 1
#define CONFIG_INITRD_TAG 1
+#define CONFIG_OF_LIBFDT 1
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
@@ -87,6 +89,10 @@
#define CONFIG_MMC 1
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
+#define CONFIG_ARM_PL180_MMCI
+#define CONFIG_ARM_PL180_MMCI_BASE 0x10005000
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
+#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 4ba3d91..e02793d 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -61,6 +61,8 @@
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
+#define CONFIG_OF_LIBFDT 1
+
/* Size of malloc() pool */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
index 1424347..571c3cb 100644
--- a/include/configs/efikamx.h
+++ b/include/configs/efikamx.h
@@ -66,6 +66,8 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
+#define CONFIG_OF_LIBFDT 1
+
/*
* Size of malloc() pool
*/
diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h
index fc15a9c..5af9bec 100644
--- a/include/configs/igep0020.h
+++ b/include/configs/igep0020.h
@@ -53,6 +53,8 @@
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
+#define CONFIG_OF_LIBFDT 1
+
/*
* NS16550 Configuration
*/
diff --git a/include/configs/igep0030.h b/include/configs/igep0030.h
index 713b1b9..92144af 100644
--- a/include/configs/igep0030.h
+++ b/include/configs/igep0030.h
@@ -53,6 +53,8 @@
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
+#define CONFIG_OF_LIBFDT 1
+
/*
* NS16550 Configuration
*/
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h
index e3bd264..cb6d0fb 100644
--- a/include/configs/keymile-common.h
+++ b/include/configs/keymile-common.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2008
+ * (C) Copyright 2008-2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -25,7 +25,8 @@
#define __CONFIG_KEYMILE_H
/* Do boardspecific init for all boards */
-#define CONFIG_BOARD_EARLY_INIT_R 1
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_LAST_STAGE_INIT
#define CONFIG_BOOTCOUNT_LIMIT
@@ -39,13 +40,6 @@
#endif /* CONFIG_SYS_KWD_CONFIG */
/*
- * CONFIG_SYS_TEXT_BASE can be defined in board specific header file, if needed
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0x00400000
-#endif /* CONFIG_SYS_TEXT_BASE */
-
-/*
* Command line configuration.
*/
#include <config_cmd_default.h>
@@ -56,51 +50,46 @@
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
-#define CONFIG_JFFS2_CMDLINE
#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_SETEXPR
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
+#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
-#define CONFIG_HUSH_INIT_VAR 1
+#define CONFIG_HUSH_INIT_VAR
#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ 1000 /* decr. freq: 1 ms ticks */
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_SYS_BOARD_DRAM_INIT /* Used board specific dram_init */
/*
@@ -108,28 +97,28 @@
* to modify in a centralized location. This is used in the HDLC
* driver to set the MAC.
*/
-#define CONFIG_CHECK_ETHERNET_PRESENT 1
-#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE
+#define CONFIG_CHECK_ETHERNET_PRESENT
+#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_KMBEC_FPGA_BASE
#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */
#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */
-#define CONFIG_I2C_MULTI_BUS 1
+#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS 1
-#define CONFIG_SYS_I2C_INIT_BOARD 1
-#define CONFIG_I2C_MUX 1
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MUX
/* EEprom support */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/* Support the IVM EEprom */
#define CONFIG_SYS_IVM_EEPROM_ADR 0x50
#define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400
#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100
-#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_FLASH_PROTECTION
/*
* BOOTP options
@@ -139,139 +128,325 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */
-
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* UBI Support for all Keymile boards */
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_FLASH_CFI_MTD
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_CONCAT
-/* define this to use the keymile's io muxing feature */
-/*#define CONFIG_IO_MUXING */
-
-#ifdef CONFIG_IO_MUXING
-#define CONFIG_KM_DEF_ENV_IOMUX \
- "nc=setenv ethact HDLC \0" \
- "nce=setenv ethact SCC \0" \
- "stderr=serial,nc \0" \
- "stdin=serial,nc \0" \
- "stdout=serial,nc \0" \
- "tftpsrcp=69 \0" \
- "tftpdstp=69 \0"
-#else
-#define CONFIG_KM_DEF_ENV_IOMUX \
- "stderr=serial \0" \
- "stdin=serial \0" \
- "stdout=serial \0"
+/* common powerpc specific env settings */
+#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
+#define CONFIG_KM_DEF_ENV_BOOTPARAMS \
+ "bootparams=empty\0" \
+ "initial_boot_bank=0\0"
#endif
-#ifndef CONFIG_KM_DEF_ENV_PRIVATE
-#define CONFIG_KM_DEF_ENV_PRIVATE \
- "kmprivate=empty\0"
+#ifndef CONFIG_KM_DEF_NETDEV
+#define CONFIG_KM_DEF_NETDEV \
+ "netdev=eth0\0"
+#endif
+
+#ifndef CONFIG_KM_UBI_PARTITION_NAME
+#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
+#endif
+#ifndef CONFIG_KM_UBI_LINUX_MTD_NAME
+#define CONFIG_KM_UBI_LINUX_MTD_NAME "ubi0"
#endif
#define xstr(s) str(s)
#define str(s) #s
+/*
+ * bootrunner
+ * - run all commands in 'subbootcmds'
+ * - on error, stop running the remaing commands
+ */
+#define CONFIG_KM_DEF_ENV_BOOTRUNNER \
+ "bootrunner=" \
+ "break=0; " \
+ "for subbootcmd in ${subbootcmds}; do " \
+ "if test ${break} -eq 0; then; " \
+ "echo \"[INFO] running \\c\"; " \
+ "print ${subbootcmd}; " \
+ "run ${subbootcmd} || break=1; " \
+ "if test ${break} -eq 1; then; " \
+ "echo \"[ERR] failed \\c\"; " \
+ "print ${subbootcmd}; " \
+ "fi; " \
+ "fi; " \
+ "done\0" \
+ ""
+
+/*
+ * boottargets
+ * - set 'subbootcmds' for the bootrunner
+ * - set 'bootcmd' and 'altbootcmd'
+ * available targets:
+ * - 'release': for a standalone system kernel/rootfs from flash
+ * - 'develop': for development kernel(tftp)/rootfs(NFS)
+ * - 'ramfs': rootfilesystem in RAM kernel(tftp)/rootfs(RAM)
+ *
+ * - 'commonargs': bootargs common to all targets
+ */
+#define CONFIG_KM_DEF_ENV_BOOTTARGETS \
+ "commonargs=" \
+ "addip " \
+ "addtty " \
+ "addmem " \
+ "addinit " \
+ "addvar " \
+ "addmtdparts " \
+ "addbootcount " \
+ "\0" \
+ "develop=" \
+ "setenv subbootcmds \"" \
+ "tftpfdt tftpkernel " \
+ "nfsargs ${commonargs} " \
+ "printbootargs boot " \
+ "\" && " \
+ "setenv bootcmd \'" \
+ "run bootrunner" \
+ "\' && " \
+ "setenv altbootcmd \'" \
+ "run bootcmd" \
+ "\' && " \
+ "run setboardid && " \
+ "saveenv && " \
+ "reset\0" \
+ "ramfs=" \
+ "setenv actual_bank -1 && " \
+ "setenv subbootcmds \"" \
+ "tftpfdt tftpkernel " \
+ "setrootfsaddr tftpramfs " \
+ "flashargs ${commonargs} " \
+ "addpanic addramfs " \
+ "printbootargs boot " \
+ "\" && " \
+ "setenv bootcmd \'" \
+ "run bootrunner" \
+ "\' && " \
+ "setenv altbootcmd \'" \
+ "run bootcmd" \
+ "\' && " \
+ "run setboardid && " \
+ "run setramfspram && " \
+ "saveenv && " \
+ "reset\0" \
+ "release=" \
+ "setenv actual_bank ${initial_boot_bank} && " \
+ "setenv subbootcmds \"" \
+ "checkboardidlist " \
+ "checkboardid " \
+ "ubiattach ubicopy " \
+ "cramfsloadfdt cramfsloadkernel " \
+ "flashargs ${commonargs} " \
+ "addpanic " \
+ "printbootargs boot " \
+ "\" && " \
+ "setenv bootcmd \'" \
+ "run bootrunner; reset" \
+ "\' && " \
+ "setenv altbootcmd \'" \
+ "run actual0 bootcmd; reset" \
+ "\' && " \
+ "saveenv && " \
+ "reset\0" \
+ ""
+
+/*
+ * bootargs
+ * - modify 'bootargs'
+ *
+ * - 'addip': add ip configuration
+ * - 'addmem': limit kernel memory mem=
+ * - 'addpanic': add kernel panic options
+ * - 'addramfs': add phram device for the rootfilesysten in ram
+ * - 'addtty': add console=...
+ * - 'addvar': add phram device for /var
+ * - 'nfsargs': default arguments for nfs boot
+ * - 'flashargs': defaults arguments for flash base boot
+ *
+ * processor specific settings
+ * - 'addbootcount': add boot counter
+ * - 'addmtdparts': add mtd partition information
+ */
+#define CONFIG_KM_DEF_ENV_BOOTARGS \
+ "addinit=" \
+ "setenv bootargs ${bootargs} init=${init}\0" \
+ "addip=" \
+ "setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off\0" \
+ "addmem=" \
+ "setenv bootargs ${bootargs} mem=0x${pnvramaddr}\0" \
+ "addpanic=" \
+ "setenv bootargs ${bootargs} " \
+ "panic=1 panic_on_oops=1\0" \
+ "addramfs=" \
+ "setenv bootargs \"" \
+ "${bootargs} phram.phram=" \
+ "rootfs${actual_bank},${rootfsaddr},${rootfssize}\"\0" \
+ "addtty=" \
+ "setenv bootargs ${bootargs}" \
+ " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}\0" \
+ "addvar=" \
+ "setenv bootargs ${bootargs} phram.phram=phvar," \
+ "${varaddr},0x" xstr(CONFIG_KM_PHRAM) "\0" \
+ "nfsargs=" \
+ "setenv bootargs " \
+ "ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \
+ "root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "flashargs=" \
+ "setenv bootargs " \
+ "ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \
+ "root=mtdblock:rootfs${actual_bank} " \
+ "rootfstype=squashfs ro\0" \
+ ""
+
+/*
+ * compute_addr
+ * - compute addresses and sizes
+ * - addresses are calculated form the end of memory 'memsize'
+ *
+ * - 'setramfspram': compute PRAM size for ramfs target
+ * - 'setrootfsaddr': compute rootfilesystem address for phram
+ */
+#define CONFIG_KM_DEF_ENV_COMPUTE_ADDR \
+ "setboardid=" \
+ "if test \"x${boardId}\" = \"x\"; then; " \
+ "setenv boardId ${IVM_BoardId} && " \
+ "setenv hwKey ${IVM_HWKey}; " \
+ "else; " \
+ "echo \\\\c; " \
+ "fi\0" \
+ "setramfspram=" \
+ "setexpr value ${rootfssize} / 0x400 && " \
+ "setexpr value 0x${value} + ${pram} && " \
+ "setenv pram 0x${value}\0" \
+ "setrootfsaddr=" \
+ "setexpr value ${pnvramaddr} - ${rootfssize} && " \
+ "setenv rootfsaddr 0x${value}\0" \
+ ""
+
+/*
+ * flash_boot
+ * - commands for booting from flash
+ *
+ * - 'cramfsaddr': address to the cramfs (in ram)
+ * - 'cramfsloadkernel': copy kernel from a cramfs to ram
+ * - 'ubiattach': attach ubi partition
+ * - 'ubicopy': copy ubi volume to ram
+ * - volume names: bootfs0, bootfs1, bootfs2, ...
+ * - 'ubiparition': mtd parition name for ubi
+ *
+ * processor specific settings
+ * - 'cramfsloadfdt': copy fdt from a cramfs to ram
+ */
+#define CONFIG_KM_DEF_ENV_FLASH_BOOT \
+ "cramfsaddr="xstr(CONFIG_KM_CRAMFS_ADDR) "\0" \
+ "cramfsloadkernel=" \
+ "cramfsload ${kernel_addr_r} uImage && " \
+ "setenv actual_kernel_addr ${kernel_addr_r}\0" \
+ "ubiattach=ubi part ${ubipartition}\0" \
+ "ubicopy=ubi read ${cramfsaddr} bootfs${actual_bank}\0" \
+ "ubipartition=" CONFIG_KM_UBI_PARTITION_NAME "\0" \
+ ""
+
+/*
+ * net_boot
+ * - commands for booting over the network
+ *
+ * - 'tftpkernel': load a kernel with tftp into ram
+ * - 'tftpramfs': load rootfs with tftp into ram
+ *
+ * processor specific settings
+ * - 'tftpfdt': load fdt with tftp into ram
+ */
+#define CONFIG_KM_DEF_ENV_NET_BOOT \
+ "tftpkernel=" \
+ "tftpboot ${kernel_addr_r} ${kernel_file} && " \
+ "setenv actual_kernel_addr ${kernel_addr_r}\0" \
+ "tftpramfs=" \
+ "tftpboot ${rootfsaddr} \"\\\"${rootfsfile}\\\"\" && " \
+ "setenv loadaddr\0" \
+ ""
+
+/*
+ * constants
+ * - KM specific constants and commands
+ *
+ * - 'default': setup default environment
+ */
+#define CONFIG_KM_DEF_ENV_CONSTANTS \
+ "actual=setenv actual_bank ${initial_boot_bank}\0" \
+ "actual0=setenv actual_bank 0\0" \
+ "actual_bank=${initial_boot_bank}\0" \
+ "default=" \
+ "setenv default 'run newenv; reset' && " \
+ "run release && saveenv; reset\0" \
+ "checkboardidlist=" \
+ "if test \"x${boardIdListHex}\" != \"x\"; then " \
+ "IVMbidhwk=${IVM_BoardId}_${IVM_HWKey}; " \
+ "found=0; " \
+ "for bidhwk in \"${boardIdListHex}\"; do " \
+ "echo trying $bidhwk ...; " \
+ "if test \"x$bidhwk\" = \"x$IVMbidhwk\"; then " \
+ "found=1; " \
+ "echo match found for $bidhwk; " \
+ "if test \"x$bidhwk\" != \"x${boardId}_${hwKey}\";then "\
+ "setenv boardid ${IVM_BoardId}; " \
+ "setenv boardId ${IVM_BoardId}; " \
+ "setenv hwkey ${IVM_HWKey}; " \
+ "setenv hwKey ${IVM_HWKey}; " \
+ "echo \"boardId set to ${boardId}\"; " \
+ "echo \"hwKey set to ${hwKey}\"; " \
+ "saveenv; " \
+ "fi; " \
+ "fi; " \
+ "done; " \
+ "else " \
+ "echo \"boardIdListHex not set, not checked\"; "\
+ "found=1; " \
+ "fi; " \
+ "test \"$found\" = 1 \0" \
+ "checkboardid=" \
+ "test \"x${boardId}\" = \"x${IVM_BoardId}\" && " \
+ "test \"x${hwKey}\" = \"x${IVM_HWKey}\"\0" \
+ "printbootargs=print bootargs\0" \
+ "rootfsfile="xstr(CONFIG_HOSTNAME) "/rootfsImage\0" \
+ ""
+
#ifndef CONFIG_KM_DEF_ENV
#define CONFIG_KM_DEF_ENV \
- "netdev=eth0\0" \
- "u-boot_addr_r=100000\0" \
- "kernel_addr_r=200000\0" \
- "fdt_addr_r=600000\0" \
- "ram_ws=800000 \0" \
- "script_ws=780000 \0" \
- "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \
- xstr(CONFIG_HOSTNAME) ".dtb\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" \
- "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
- "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
- "update=protect off " xstr(BOOTFLASH_START) " +${filesize};" \
- "erase " xstr(BOOTFLASH_START) " +${filesize};" \
- "cp.b ${u-boot_addr_r} " xstr(BOOTFLASH_START) \
- " ${filesize};" \
- "protect on " xstr(BOOTFLASH_START) " +${filesize}\0" \
- "load_fdt=tftp ${fdt_addr_r} ${fdt_file}; " \
- "setenv actual_fdt_addr ${fdt_addr_r} \0" \
- "load_kernel=tftp ${kernel_addr_r} ${kernel_file}; " \
- "setenv actual_kernel_addr ${kernel_addr_r} \0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "mtdargs=setenv bootargs root=${actual_rootfs} rw " \
- "rootfstype=jffs2 \0" \
- "altmtdargs=setenv bootargs root=${backup_rootfs} rw " \
- "rootfstype=jffs2 \0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addboardid=setenv bootargs ${bootargs} " \
- "hwKey=${IVM_HWKey} boardId=0x${IVM_BoardId} \0" \
- "addpram=setenv bootargs ${bootargs} " \
- "mem=${mem} pram=${pram}\0" \
- "pram=" xstr(CONFIG_PRAM) "k\0" \
- "net_nfs=tftp ${kernel_addr_r} ${kernel_file}; " \
- "tftp ${fdt_addr_r} ${fdt_file}; " \
- "run nfsargs addip addcon addboardid addpram;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "net_self=tftp ${kernel_addr_r} ${kernel_file}; " \
- "tftp ${fdt_addr_r} ${fdt_file}; " \
- "tftp ${ramdisk_addr} ${ramdisk_file}; " \
- "run ramargs addip addboardid addpram; " \
- "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0"\
- "flash_nfs=run nfsargs addip addcon;" \
- "bootm ${kernel_addr} - ${fdt_addr}\0" \
- "flash_self=run ramargs addip addcon addboardid addpram;" \
- "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
- "bootcmd=run mtdargs addip addcon addboardid addpram; " \
- "bootm ${actual_kernel_addr} - ${actual_fdt_addr} \0" \
- "altbootcmd=run altmtdargs addip addcon addboardid addpram; " \
- "bootm ${backup_kernel_addr} - ${backup_fdt_addr} \0" \
- "actual0=setenv actual_bank 0; setenv actual_kernel_addr " \
- "${bank0_kernel_addr}; " \
- "setenv actual_fdt_addr ${bank0_fdt_addr}; " \
- "setenv actual_rootfs ${bank0_rootfs} \0" \
- "actual1=setenv actual_bank 1; setenv actual_kernel_addr " \
- "${bank1_kernel_addr}; " \
- "setenv actual_fdt_addr ${bank1_fdt_addr}; " \
- "setenv actual_rootfs ${bank1_rootfs} \0" \
- "backup0=setenv backup_bank 0; setenv backup_kernel_addr " \
- "${bank0_kernel_addr}; " \
- "setenv backup_fdt_addr ${bank0_fdt_addr}; " \
- "setenv backup_rootfs ${bank0_rootfs} \0" \
- "backup1=setenv backup_bank 1; setenv backup_kernel_addr " \
- "${bank1_kernel_addr}; " \
- "setenv backup_fdt_addr ${bank1_fdt_addr}; " \
- "setenv backup_rootfs ${bank1_rootfs} \0" \
- "setbank0=run actual0 backup1 \0" \
- "setbank1=run actual1 backup0 \0" \
- "release=setenv bootcmd " \
- "\'run mtdargs addip addcon addboardid addpram;" \
- "bootm ${actual_kernel_addr} - ${actual_fdt_addr} \'; " \
- "saveenv \0" \
- "develop=setenv bootcmd " \
- "\'run nfsargs addip addcon addboardid addpram;" \
- "bootm ${actual_kernel_addr} - ${actual_fdt_addr} \'; " \
- "saveenv \0" \
- "developall=setenv bootcmd " \
- "\'run load_fdt load_kernel nfsargs " \
- "addip addcon addboardid addpram; " \
- "bootm ${actual_kernel_addr} - ${actual_fdt_addr} \'; " \
- "saveenv \0" \
- "set_new_esw_script=setenv new_esw_script " \
- "new_esw_0x${IVM_BoardId}_0x${IVM_HWKey}.scr \0" \
- "new_esw=run set_new_esw_script; " \
- "tftp ${script_ws} ${new_esw_script}; " \
- "iminfo ${script_ws}; source ${script_ws} \0" \
- "bootlimit=0 \0" \
- CONFIG_KM_DEF_ENV_IOMUX \
- CONFIG_KM_DEF_ENV_PRIVATE \
+ CONFIG_KM_DEF_ENV_BOOTPARAMS \
+ CONFIG_KM_DEF_NETDEV \
+ CONFIG_KM_DEF_ENV_CPU \
+ CONFIG_KM_DEF_ENV_BOOTRUNNER \
+ CONFIG_KM_DEF_ENV_BOOTTARGETS \
+ CONFIG_KM_DEF_ENV_BOOTARGS \
+ CONFIG_KM_DEF_ENV_COMPUTE_ADDR \
+ CONFIG_KM_DEF_ENV_FLASH_BOOT \
+ CONFIG_KM_DEF_ENV_NET_BOOT \
+ CONFIG_KM_DEF_ENV_CONSTANTS \
+ "altbootcmd=run bootcmd\0" \
+ "bootcmd=run default\0" \
+ "bootlimit=2\0" \
+ "init=/sbin/init-overlay.sh\0" \
+ "kernel_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \
+ "kernel_file="xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "kernel_name=uImage\0" \
+ "load=tftpboot ${u-boot_addr_r} ${u-boot}\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "stderr=serial\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \
""
#endif /* CONFIG_KM_DEF_ENV */
diff --git a/include/configs/km-powerpc.h b/include/configs/km-powerpc.h
new file mode 100644
index 0000000..3351609
--- /dev/null
+++ b/include/configs/km-powerpc.h
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_KEYMILE_POWERPC_H
+#define __CONFIG_KEYMILE_POWERPC_H
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_CMD_DTT
+#define CONFIG_JFFS2_CMDLINE
+
+#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */
+#define CONFIG_FLASH_CFI_MTD
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
+
+#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+
+/******************************************************************************
+ * (PRAM usage)
+ * ... -------------------------------------------------------
+ * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
+ * ... |<------------------- pram -------------------------->|
+ * ... -------------------------------------------------------
+ * @END_OF_RAM:
+ * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
+ * @CONFIG_KM_PHRAM: address for /var
+ * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
+ * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
+ */
+
+/* size of rootfs in RAM */
+#define CONFIG_KM_ROOTFSSIZE 0x0
+/* pseudo-non volatile RAM [hex] */
+#define CONFIG_KM_PNVRAM 0x80000
+/* physical RAM MTD size [hex] */
+#define CONFIG_KM_PHRAM 0x100000
+/* resereved pram area at the end of memroy [hex] */
+#define CONFIG_KM_RESERVED_PRAM 0x0
+/* enable protected RAM */
+#define CONFIG_PRAM 0
+
+#define CONFIG_KM_CRAMFS_ADDR 0x800000
+#define CONFIG_KM_KERNEL_ADDR 0x400000 /* 3968Kbytes */
+#define CONFIG_KM_FDT_ADDR 0x7E0000 /* 128Kbytes */
+
+#define CONFIG_KM_DEF_ENV_CPU \
+ "addbootcount=echo \\\\c\0" \
+ "addmtdparts=echo \\\\c\0" \
+ "boot=bootm ${actual_kernel_addr} - ${actual_fdt_addr}\0" \
+ "cramfsloadfdt=" \
+ "cramfsload ${fdt_addr_r} " \
+ "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb && " \
+ "setenv actual_fdt_addr ${fdt_addr_r}\0" \
+ "fdt_addr_r=" xstr(CONFIG_KM_FDT_ADDR) "\0" \
+ "fdt_file=" \
+ xstr(CONFIG_HOSTNAME) "/" \
+ xstr(CONFIG_HOSTNAME) ".dtb\0" \
+ "tftpfdt=" \
+ "tftpboot ${fdt_addr_r} ${fdt_file} && " \
+ "setenv actual_fdt_addr ${fdt_addr_r} \0" \
+ "update=" \
+ "protect off " xstr(BOOTFLASH_START) " +${filesize} && "\
+ "erase " xstr(BOOTFLASH_START) " +${filesize} && " \
+ "cp.b ${u-boot_addr_r} " xstr(BOOTFLASH_START) \
+ " ${filesize} && " \
+ "protect on " xstr(BOOTFLASH_START) " +${filesize}\0" \
+ ""
+
+#endif /* __CONFIG_KEYMILE_POWERPC_H */
diff --git a/include/configs/km82xx-common.h b/include/configs/km82xx-common.h
new file mode 100644
index 0000000..345212c
--- /dev/null
+++ b/include/configs/km82xx-common.h
@@ -0,0 +1,336 @@
+/*
+ * (C) Copyright 2007-2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __KM82XX_COMMON
+#define __KM82XX_COMMON
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define CONFIG_CONS_ON_SMC /* Console is on SMC */
+#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
+#undef CONFIG_CONS_NONE /* It's not on external UART */
+#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
+ */
+#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
+#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
+#undef CONFIG_ETHER_NONE /* No external Ethernet */
+#define CONFIG_NET_MULTI
+
+#define CONFIG_ETHER_INDEX 4
+#define CONFIG_HAS_ETH0
+#define CONFIG_SYS_SCC_TOUT_LOOP 10000000
+
+#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN 66000000 /* in Hz */
+#endif
+
+#define BOOTFLASH_START 0xFE000000
+
+#define CONFIG_KM_CONSOLE_TTY "ttyCPM0"
+
+#define MTDPARTS_DEFAULT "mtdparts=" \
+ "app:" \
+ "768k(u-boot)," \
+ "128k(env)," \
+ "128k(envred)," \
+ "3072k(free)," \
+ "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+
+/*
+ * Default environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
+ "EEprom_ivm=pca9544a:70:4 \0" \
+ "unlock=yes\0" \
+ "newenv=" \
+ "prot off 0xFE0C0000 +0x40000 && " \
+ "era 0xFE0C0000 +0x40000\0" \
+ "rootpath=/opt/eldk/ppc_82xx\0" \
+ ""
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN (768 << 10)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/* enable I2C and select the hardware/software driver */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed */
+#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+
+#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE (iop->pdir |= 0x00010000)
+#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
+#define I2C_READ ((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit) do { \
+ if (bit) \
+ iop->pdat |= 0x00010000; \
+ else \
+ iop->pdat &= ~0x00010000; \
+ } while (0)
+#define I2C_SCL(bit) do { \
+ if (bit) \
+ iop->pdat |= 0x00020000; \
+ else \
+ iop->pdat &= ~0x00020000; \
+ } while (0)
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */
+#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CONFIG_SYS_DTT_MAX_TEMP 70
+#define CONFIG_SYS_DTT_LOW_TEMP -30
+#define CONFIG_SYS_DTT_HYSTERESIS 3
+#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+#define CONFIG_SYS_IMMR 0xF0000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/* Hard reset configuration word */
+#define CONFIG_SYS_HRCW_MASTER 0x0604b211
+
+/* No slaves */
+#define CONFIG_SYS_HRCW_SLAVE1 0
+#define CONFIG_SYS_HRCW_SLAVE2 0
+#define CONFIG_SYS_HRCW_SLAVE3 0
+#define CONFIG_SYS_HRCW_SLAVE4 0
+#define CONFIG_SYS_HRCW_SLAVE5 0
+#define CONFIG_SYS_HRCW_SLAVE6 0
+#define CONFIG_SYS_HRCW_SLAVE7 0
+
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+#define CONFIG_SYS_HID0_INIT 0
+#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
+
+#define CONFIG_SYS_HID2 0
+
+#define CONFIG_SYS_SIUMCR 0x4020c200
+#define CONFIG_SYS_SYPCR 0xFFFFFFC3
+#define CONFIG_SYS_BCR 0x10000000
+#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
+
+/*
+ *-----------------------------------------------------------------------
+ * RMR - Reset Mode Register 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CONFIG_SYS_RMR 0
+
+/*
+ *-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*
+ *-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*
+ *-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration 13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR 0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus Machine PortSz Device
+ * ---- --- ------- ------ ------
+ * 0 60x GPCM 8 bit FLASH
+ * 1 60x SDRAM 32 bit SDRAM
+ * 3 60x GPCM 8 bit GPIO/PIGGY
+ * 5 60x GPCM 16 bit CFG-Flash
+ *
+ */
+/* Bank 0 - FLASH
+ */
+#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
+ BRx_PS_8 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
+ ORxG_CSNT |\
+ ORxG_ACS_DIV2 |\
+ ORxG_SCY_5_CLK |\
+ ORxG_TRLX)
+
+
+/*
+ * Bank 1 - 60x bus SDRAM
+ */
+#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
+
+#define CONFIG_SYS_MPTPR 0x1800
+
+/*
+ *-----------------------------------------------------------------------------
+ * Address for Mode Register Set (MRS) command
+ *-----------------------------------------------------------------------------
+ */
+#define CONFIG_SYS_MRS_OFFS 0x00000110
+#define CONFIG_SYS_PSRT 0x0e
+
+#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
+ BRx_PS_64 |\
+ BRx_MS_SDRAM_P |\
+ BRx_V)
+
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
+
+/*
+ * SDRAM initialization values
+ */
+
+#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+ ORxS_BPD_8 |\
+ ORxS_ROWST_PBI0_A7 |\
+ ORxS_NUMR_13)
+
+#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
+ PSDMR_BSMA_A14_A16 |\
+ PSDMR_SDA10_PBI0_A9 |\
+ PSDMR_RFRC_5_CLK |\
+ PSDMR_PRETOACT_2W |\
+ PSDMR_ACTTORW_2W |\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_1C |\
+ PSDMR_CL_2)
+
+/*
+ * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
+ */
+#define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
+
+#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
+ BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
+
+#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
+ ORxG_CSNT | ORxG_ACS_DIV2 |\
+ ORxG_SCY_3_CLK | ORxG_TRLX)
+
+/*
+ * BFTICU board FPGA on CS4 initialization values
+ */
+#define CONFIG_SYS_FPGA_BASE 0x40000000
+#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
+
+#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
+ BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
+
+#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
+ ORxG_CSNT | ORxG_ACS_DIV2 |\
+ ORxG_SCY_3_CLK | ORxG_TRLX)
+
+/*
+ * CFG-Flash on CS5 initialization values
+ */
+#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
+ BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
+
+#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
+ CONFIG_SYS_FLASH_SIZE_2) |\
+ ORxG_CSNT | ORxG_ACS_DIV2 |\
+ ORxG_SCY_5_CLK | ORxG_TRLX)
+
+#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
+
+/* pass open firmware flat tree */
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
+
+#endif /* __KM82XX_COMMON */
diff --git a/include/configs/km8321-common.h b/include/configs/km8321-common.h
new file mode 100644
index 0000000..6fab45e
--- /dev/null
+++ b/include/configs/km8321-common.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ *
+ * (C) Copyright 2010-2011
+ * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_KM8321_COMMON_H
+#define __CONFIG_KM8321_COMMON_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_QE /* Has QE */
+#define CONFIG_MPC832x /* MPC832x CPU specific */
+#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
+
+#define CONFIG_KM_DEF_ROOTPATH \
+ "rootpath=/opt/eldk/ppc_8xx\0"
+
+/* include common defines/options for all 83xx Keymile boards */
+#include "km83xx-common.h"
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRL SICRL_IRQ_CKS
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
+ HRCWL_DDR_TO_SCB_CLK_2X1 | \
+ HRCWL_CSB_TO_CLKIN_2X1 | \
+ HRCWL_CORE_TO_CSB_2_5X1 | \
+ HRCWL_CE_PLL_VCO_DIV_2 | \
+ HRCWL_CE_TO_PLL_1X3)
+
+#define CONFIG_SYS_HRCW_HIGH (\
+ HRCWH_PCI_AGENT | \
+ HRCWH_PCI_ARBITER_DISABLE | \
+ HRCWH_CORE_ENABLE | \
+ HRCWH_FROM_0X00000100 | \
+ HRCWH_BOOTSEQ_DISABLE | \
+ HRCWH_SW_WATCHDOG_DISABLE | \
+ HRCWH_ROM_LOC_LOCAL_16BIT | \
+ HRCWH_BIG_ENDIAN | \
+ HRCWH_LALE_NORMAL)
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+ SDRAM_CFG_32_BE | \
+ SDRAM_CFG_SREN)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+ (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
+ CSCONFIG_ODT_WR_CFG | \
+ CSCONFIG_ROW_BIT_13 | \
+ CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_MODE 0x47860252
+#define CONFIG_SYS_DDR_MODE2 0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+ (0 << TIMING_CFG0_WWT_SHIFT) | \
+ (0 << TIMING_CFG0_RRT_SHIFT) | \
+ (0 << TIMING_CFG0_WRT_SHIFT) | \
+ (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
+ (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+ (2 << TIMING_CFG1_WRREC_SHIFT) | \
+ (6 << TIMING_CFG1_REFREC_SHIFT) | \
+ (2 << TIMING_CFG1_ACTTORW_SHIFT) | \
+ (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+ (2 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+ (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+ (5 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+
+#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LBC_LBCR 0x00000000
+
+/*
+ * MMU Setup
+ */
+#define CONFIG_SYS_IBAT7L (0)
+#define CONFIG_SYS_IBAT7U (0)
+#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
+
+#endif /* __CONFIG_KM8321_COMMON_H */
diff --git a/include/configs/km83xx-common.h b/include/configs/km83xx-common.h
new file mode 100644
index 0000000..85b6ed2
--- /dev/null
+++ b/include/configs/km83xx-common.h
@@ -0,0 +1,325 @@
+/*
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_KM83XX_H
+#define __CONFIG_KM83XX_H
+
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
+#include "km-powerpc.h"
+
+#define MTDIDS_DEFAULT "nor0=boot"
+#define MTDPARTS_DEFAULT "mtdparts=" \
+ "boot:" \
+ "768k(u-boot)," \
+ "128k(env)," \
+ "128k(envred)," \
+ "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+
+#define CONFIG_MISC_INIT_R
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN 66000000
+#define CONFIG_SYS_CLK_FREQ 66000000
+#define CONFIG_83XX_PCICLK 66000000
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR 0xE0000000
+
+/*
+ * Bus Arbitration Configuration Register (ACR)
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
+#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
+#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CFG_83XX_DDR_USES_CS0
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_DDR_II
+#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_FLASH_BASE 0xF0000000
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+/* Reserve 768 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus Machine PortSz Size Device
+ * ---- --- ------- ------ ----- ------
+ * 0 Local GPCM 16 bit 256MB FLASH
+ * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
+ *
+ */
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
+
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
+ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+ BR_V)
+
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
+ OR_GPCM_SCY_5 | \
+ OR_GPCM_TRLX | OR_GPCM_EAD)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+/*
+ * PRIO1/PIGGY on the local bus CS1
+ */
+/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
+
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
+ (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
+ BR_V)
+#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
+ OR_GPCM_SCY_2 | \
+ OR_GPCM_TRLX | OR_GPCM_EAD)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME "UEC0"
+
+#define CONFIG_UEC_ETH1 /* GETH1 */
+#define UEC_VERBOSE_DEBUG 1
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
+#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR 0
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+#endif
+
+/*
+ * Environment
+ */
+
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#else /* CFG_SYS_RAMBOOT */
+#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
+#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE 0x2000
+#endif /* CFG_SYS_RAMBOOT */
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_FSL_I2C
+#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */
+#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
+#define CONFIG_SYS_DTT_MAX_TEMP 70
+#define CONFIG_SYS_DTT_LOW_TEMP -30
+#define CONFIG_SYS_DTT_HYSTERESIS 3
+#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
+#endif
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
+#define CONFIG_SYS_HID2 HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+
+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
+
+/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define BOOTFLASH_START 0xF0000000
+
+#define CONFIG_KM_CONSOLE_TTY "ttyS0"
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
+#endif
+
+#ifndef CONFIG_KM_DEF_ROOTPATH
+#define CONFIG_KM_DEF_ROOTPATH \
+ "rootpath=/opt/eldk/ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
+ CONFIG_KM_DEF_ROOTPATH \
+ "dtt_bus=pca9547:70:a\0" \
+ "EEprom_ivm=pca9547:70:9\0" \
+ "newenv=" \
+ "prot off 0xF00C0000 +0x40000 && " \
+ "era 0xF00C0000 +0x40000\0" \
+ "unlock=yes\0" \
+ ""
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#endif
+
+#endif /* __CONFIG_KM83XX_H */
diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h
index bf77cc0..70113d4 100644
--- a/include/configs/km_arm.h
+++ b/include/configs/km_arm.h
@@ -6,6 +6,9 @@
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
+ * (C) Copyright 2010-2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -25,7 +28,10 @@
* MA 02110-1301 USA
*/
-/* for linking errors see http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
+/*
+ * for linking errors see
+ * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
+ */
#ifndef _CONFIG_KM_ARM_H
#define _CONFIG_KM_ARM_H
@@ -38,12 +44,34 @@
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
#define CONFIG_KIRKWOOD /* SOC Family Name */
#define CONFIG_KW88F6281 /* SOC Name */
-#define CONFIG_MACH_SUEN3 /* Machine type */
+#define CONFIG_MACH_KM_KIRKWOOD /* Machine type */
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
-#undef CONFIG_CMD_DTT
-#undef CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_SYS_TEXT_BASE 0x04000000 /* code address after reloc */
+#define CONFIG_ENV_SIZE (128 << 10) /* NAND chip block size */
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
+#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
+#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
+
+/* pseudo-non volatile RAM [hex] */
+#define CONFIG_KM_PNVRAM 0x80000
+/* physical RAM MTD size [hex] */
+#define CONFIG_KM_PHRAM 0x17F000
+
+#define CONFIG_KM_CRAMFS_ADDR 0x2400000
+#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */
+
+#define CONFIG_KM_DEF_ENV_CPU \
+ "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "boot=bootm ${actual_kernel_addr} - -\0" \
+ "cramfsloadfdt=echo \\\\c\0" \
+ "tftpfdt=echo \\\\c\0" \
+ CONFIG_KM_DEF_ENV_UPDATE \
+ ""
+
+
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
@@ -152,15 +180,15 @@ void set_sda (int state);
void set_scl (int state);
int get_sda (void);
int get_scl (void);
-#define SUEN3_SDA_PIN 8
-#define SUEN3_SCL_PIN 9
-#define SUEN3_ENV_WP 38
-
-#define I2C_ACTIVE __set_direction(SUEN3_SDA_PIN, 0)
-#define I2C_TRISTATE __set_direction(SUEN3_SDA_PIN, 1)
-#define I2C_READ (kw_gpio_get_value(SUEN3_SDA_PIN) ? 1 : 0)
-#define I2C_SDA(bit) kw_gpio_set_value(SUEN3_SDA_PIN, bit);
-#define I2C_SCL(bit) kw_gpio_set_value(SUEN3_SCL_PIN, bit);
+#define KM_KIRKWOOD_SDA_PIN 8
+#define KM_KIRKWOOD_SCL_PIN 9
+#define KM_KIRKWOOD_ENV_WP 38
+
+#define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0)
+#define I2C_TRISTATE __set_direction(KM_KIRKWOOD_SDA_PIN, 1)
+#define I2C_READ (kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0)
+#define I2C_SDA(bit) kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit)
+#define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit)
#endif
#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
@@ -173,6 +201,47 @@ int get_scl (void);
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */
+#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_EEPROM_WREN
+#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET)
+#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0"
+
+/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#define CONFIG_CMD_SF
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_HARD_SPI
+#define CONFIG_KIRKWOOD_SPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50Mhz */
+
+#define FLASH_GPIO_PIN 0x00010000
+
+#define MTDIDS_DEFAULT "nand0=orion_nand"
+/* test-only: partitioning needs some tuning, this is just for tests */
+#define MTDPARTS_DEFAULT "mtdparts=" \
+ "orion_nand:" \
+ "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+
+#define CONFIG_KM_DEF_ENV_UPDATE \
+ "update=" \
+ "spi on;sf probe 0;sf erase 0 50000;" \
+ "sf write ${u-boot_addr_r} 0 ${filesize};" \
+ "spi off\0"
+
#if defined(CONFIG_SYS_NO_FLASH)
#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
#undef CONFIG_FLASH_CFI_MTD
@@ -185,4 +254,13 @@ int get_scl (void);
#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
/* Do early setups now in board_init_f() */
#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
+ * resereved pram area at the end of memroy [hex]
+ * 8Mbytes for switch + 4Kbytes for bootcount
+ */
+#define CONFIG_KM_RESERVED_PRAM 0x801000
+/* address for the bootcount (taken from end of RAM) */
+#define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM)
+
#endif /* _CONFIG_KM_ARM_H */
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index b98e6a1..2fcecaf 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -8,7 +8,7 @@
* Copyright (C) 2007 MontaVista Software, Inc.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
- * (C) Copyright 2008
+ * (C) Copyright 2008-2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* This program is free software; you can redistribute it and/or
@@ -23,32 +23,24 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
-#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
-#define CONFIG_KMETER1 1 /* KMETER1 board specific */
+#define CONFIG_QE /* Has QE */
+#define CONFIG_MPC8360 /* MPC8360 CPU specific */
+#define CONFIG_KMETER1 /* KMETER1 board specific */
#define CONFIG_HOSTNAME kmeter1
+#define CONFIG_KM_BOARD_NAME "kmeter1"
#define CONFIG_SYS_TEXT_BASE 0xF0000000
+#define CONFIG_KM_DEF_NETDEV \
+ "netdev=eth2\0" \
-/* include common defines/options for all Keymile boards */
-#include "keymile-common.h"
+/* include common defines/options for all 83xx Keymile boards */
+#include "km83xx-common.h"
-#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
-
-#define MTDIDS_DEFAULT "nor0=boot"
-#define MTDPARTS_DEFAULT \
- "mtdparts=boot:768k(u-boot),128k(env),128k(envred)," \
- "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
-
-#define CONFIG_MISC_INIT_R 1
+#define CONFIG_MISC_INIT_R
/*
- * System Clock Setup
+ * System IO Setup
*/
-#define CONFIG_83XX_CLKIN 66000000
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define CONFIG_83XX_PCICLK 66000000
+#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
/*
* Hardware Reset Configuration Word
@@ -69,54 +61,7 @@
HRCWH_LALE_EARLY | \
HRCWH_LDP_CLEAR )
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH 0x00000006
-#define CONFIG_SYS_SICRL 0x00000000
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-
-#define CFG_83XX_DDR_USES_CS0
-
-#undef CONFIG_DDR_ECC
-
-/*
- * DDRCDR - DDR Control Driver Register
- */
-
-#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
-
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_DDR_II
-#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
- CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
-
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
SDRAM_CFG_SREN)
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
@@ -124,6 +69,11 @@
#define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
(0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
+ CSCONFIG_ROW_BIT_13 | \
+ CSCONFIG_COL_BIT_10 | \
+ CSCONFIG_ODT_WR_ACS)
+
#define CONFIG_SYS_DDRCDR 0x40000001
#define CONFIG_SYS_DDR_MODE 0x47860452
#define CONFIG_SYS_DDR_MODE2 0x8080c000
@@ -137,14 +87,14 @@
(0 << TIMING_CFG0_WRT_SHIFT) | \
(0 << TIMING_CFG0_RWT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_50) | \
- ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
- ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
- ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
- ( 7 << TIMING_CFG1_REFREC_SHIFT) | \
- ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
- ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
- ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
+#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
+ (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+ (3 << TIMING_CFG1_WRREC_SHIFT) | \
+ (7 << TIMING_CFG1_REFREC_SHIFT) | \
+ (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+ (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+ (3 << TIMING_CFG1_PRETOACT_SHIFT))
#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
@@ -156,31 +106,15 @@
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_FLASH_BASE 0xF0000000
-#define CONFIG_SYS_PIGGY_BASE 0xE8000000
-#define CONFIG_SYS_PIGGY_SIZE 128
-#define CONFIG_SYS_PAXE_BASE 0xA0000000
+/* PRIO FPGA */
+#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
+/* PAXE FPGA */
+#define CONFIG_SYS_PAXE_BASE 0xA0000000
#define CONFIG_SYS_PAXE_SIZE 512
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*
* Local Bus Configuration & Clock Setup
@@ -194,56 +128,14 @@
*
* Bank Bus Machine PortSz Size Device
* ---- --- ------- ------ ----- ------
- * 0 Local GPCM 16 bit 256MB FLASH
- * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
* 3 Local GPCM 8 bit 512MB PAXE
*
*/
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_FLASH_PROTECTION 1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
- BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
- OR_GPCM_SCY_5 | \
- OR_GPCM_TRLX | OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * PRIO1/PIGGY on the local bus CS1
- */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \
- (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
- BR_V)
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
- OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX | OR_GPCM_EAD)
/*
* PAXE on the local bus CS3
*/
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
@@ -255,165 +147,14 @@
OR_GPCM_TRLX | OR_GPCM_EAD)
/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#undef CONFIG_PCI /* No PCI */
-
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
-#endif
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "UEC0"
-
-#define CONFIG_UEC_ETH1 /* GETH1 */
-#define UEC_VERBOSE_DEBUG 1
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 0
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif
-
-/*
- * Environment
- */
-
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#else /* CFG_RAMBOOT */
-#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
-#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE 0x2000
-#endif /* CFG_RAMBOOT */
-
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_I2C_MULTI_BUS 1
-#define CONFIG_I2C_MUX 1
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE
-#endif
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-#if defined(CFG_RAMBOOT)
-#undef CONFIG_CMD_SAVEENV
-#undef CONFIG_CMD_LOADS
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
* MMU Setup
*/
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
/* PAXE: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
@@ -441,39 +182,4 @@
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif /* CONFIG_PCI */
-#define BOOTFLASH_START F0000000
-
-#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
-#define CONFIG_KM_DEF_ENV "km-common=empty\0"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_KM_DEF_ENV \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \
- "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \
- "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
- "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0" \
- "unlock=yes\0" \
- "fdt_addr=F0080000\0" \
- "kernel_addr=F00a0000\0" \
- "ramdisk_addr=F03a0000\0" \
- "ramdisk_addr_r=F10000\0" \
- "EEprom_ivm=pca9547:70:9\0" \
- "dtt_bus=pca9547:70:a\0" \
- "mtdids=nor0=app \0" \
- "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
- ""
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
-#endif
-
#endif /* __CONFIG_H */
diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
new file mode 100644
index 0000000..55ed3f6
--- /dev/null
+++ b/include/configs/kmsupx5.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ *
+ * (C) Copyright 2010-2011
+ * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KMSUPX5 1 /* Keymile PBEC8321 board specific */
+#define CONFIG_HOSTNAME supx5
+#define CONFIG_KM_BOARD_NAME "supx5"
+
+#define CONFIG_SYS_TEXT_BASE 0xF0000000
+
+/* include common defines/options for all 8321 Keymile boards */
+#include "km8321-common.h"
+
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus Machine PortSz Size Device
+ * ---- --- ------- ------ ----- ------
+ * 2 Local GPCM 8 bit 256MB LPXF
+ * 3 Local not used
+ *
+ */
+
+/*
+ * LPXF on the local bus CS2
+ * Window base at flash base
+ * Window size: 256 MB
+ */
+
+#define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */
+#define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */
+
+#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
+
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \
+ BR_PS_8 | \
+ BR_MS_GPCM | \
+ BR_V)
+
+#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \
+ OR_GPCM_CSNT | \
+ OR_GPCM_ACS_DIV4 | \
+ OR_GPCM_SCY_2 | \
+ (OR_GPCM_TRLX & \
+ (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
+ OR_GPCM_EAD)
+
+/* LPXF: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
+
+/* Bank 3 not used */
+#define CONFIG_SYS_IBAT6L (0)
+#define CONFIG_SYS_IBAT6U (0)
+#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h
index f1bd32a..dcde76c 100644
--- a/include/configs/mgcoge.h
+++ b/include/configs/mgcoge.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -29,92 +29,24 @@
* (easy to change)
*/
-#define CONFIG_MPC8247 1
-#define CONFIG_MPC8272_FAMILY 1
-#define CONFIG_MGCOGE 1
+#define CONFIG_MPC8247
+#define CONFIG_MGCOGE
#define CONFIG_HOSTNAME mgcoge
#define CONFIG_SYS_TEXT_BASE 0xFE000000
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
-
-/*
- * Select serial console configuration
- *
- * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- */
-#define CONFIG_CONS_ON_SMC /* Console is on SMC */
-#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
-#undef CONFIG_CONS_NONE /* It's not on external UART */
-#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
-#define CONFIG_SYS_SMC_RXBUFLEN 128
-#define CONFIG_SYS_MAXIDLE 10
-
-/*
- * Select ethernet configuration
- *
- * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
- * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
- * SCC, 1-3 for FCC)
- *
- * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
- * must be unset.
- */
-#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
-#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
-#undef CONFIG_ETHER_NONE /* No external Ethernet */
-#define CONFIG_NET_MULTI 1
-
-#define CONFIG_ETHER_INDEX 4
-#define CONFIG_HAS_ETH0
-#define CONFIG_SYS_SCC_TOUT_LOOP 10000000
-
-# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
-
-#ifndef CONFIG_8260_CLKIN
-#define CONFIG_8260_CLKIN 66000000 /* in Hz */
-#endif
-
-#define BOOTFLASH_START FE000000
-#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
-
-#define MTDIDS_DEFAULT "nor0=boot,nor1=app"
-#define MTDPARTS_DEFAULT \
- "mtdparts=boot:384k(u-boot),128k(env),128k(envred),3456k(free);" \
- "app:3m(esw0),10m(rootfs0),3m(esw1),10m(rootfs1),1m(var),5m(cfg)"
-
-#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
-#define CONFIG_KM_DEF_ENV "km-common=empty\0"
-#endif
-/*
- * Default environment settings
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_KM_DEF_ENV \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- "addcon=setenv bootargs ${bootargs} " \
- "console=ttyCPM0,${baudrate}\0" \
- "mtdids=nor0=boot,nor1=app \0" \
- "partition=nor1,5 \0" \
- "new_env=prot off FE060000 FE09FFFF; era FE060000 FE09FFFF \0" \
- "EEprom_ivm=pca9544a:70:4 \0" \
- "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
- "unlock=yes\0" \
- ""
+#include "km-powerpc.h"
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFE000000
#define CONFIG_SYS_FLASH_SIZE 32
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 3
+/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
#define CONFIG_SYS_FLASH_BASE_1 0x50000000
#define CONFIG_SYS_FLASH_SIZE_1 32
@@ -124,232 +56,11 @@
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
CONFIG_SYS_FLASH_BASE_1, \
CONFIG_SYS_FLASH_BASE_2 }
+#define MTDIDS_DEFAULT "nor3=app"
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384KB for Monitor */
-
-#define CONFIG_ENV_IS_IN_FLASH
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-#define CONFIG_ENV_BUFFER_PRINT 1
-
-/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-#define CONFIG_SYS_IMMR 0xF0000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* Hard reset configuration word */
-#define CONFIG_SYS_HRCW_MASTER 0x0604b211
-
-/* No slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
-
-#define CONFIG_SYS_HID2 0
-
-#define CONFIG_SYS_SIUMCR 0x4020c200
-#define CONFIG_SYS_SYPCR 0xFFFFFFC3
-#define CONFIG_SYS_BCR 0x10000000
-#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR 0
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 8 bit FLASH
- * 1 60x SDRAM 32 bit SDRAM
- * 3 60x GPCM 8 bit GPIO/PIGGY
- * 5 60x GPCM 16 bit CFG-Flash
- *
- */
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV2 |\
- ORxG_SCY_5_CLK |\
- ORxG_TRLX )
-
-
-/* Bank 1 - 60x bus SDRAM
- */
-#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
-
-#define CONFIG_SYS_MPTPR 0x1800
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MRS_OFFS 0x00000110
-#define CONFIG_SYS_PSRT 0x0e
-
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
-
-/* SDRAM initialization values
-*/
-
-#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_8 |\
- ORxS_ROWST_PBI0_A7 |\
- ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A14_A16 |\
- PSDMR_SDA10_PBI0_A9 |\
- PSDMR_RFRC_5_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-
-/* GPIO/PIGGY on CS3 initialization values
-*/
-#define CONFIG_SYS_PIGGY_BASE 0x30000000
-#define CONFIG_SYS_PIGGY_SIZE 128
-
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\
- BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
-
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\
- ORxG_CSNT | ORxG_ACS_DIV2 |\
- ORxG_SCY_3_CLK | ORxG_TRLX )
-
-/* Board FPGA on CS4 initialization values
-*/
-#define CONFIG_SYS_FPGA_BASE 0x40000000
-#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
-
-#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
- BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
-
-#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
- ORxG_CSNT | ORxG_ACS_DIV2 |\
- ORxG_SCY_3_CLK | ORxG_TRLX )
-
-/* CFG-Flash on CS5 initialization values
-*/
-#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
- BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
-
-#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
- CONFIG_SYS_FLASH_SIZE_2) |\
- ORxG_CSNT | ORxG_ACS_DIV2 |\
- ORxG_SCY_5_CLK | ORxG_TRLX )
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
-
-/* pass open firmware flat tree */
-#define CONFIG_FIT 1
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
+/* include further common stuff for all keymile 82xx boards */
+#include "km82xx-common.h"
-/* enable last_stage_init */
-#define CONFIG_LAST_STAGE_INIT 1
/* bfticu address */
#define CONFIG_SYS_BFTICU_BASE 0x40000000
diff --git a/include/configs/mgcoge2ne.h b/include/configs/mgcoge2ne.h
new file mode 100644
index 0000000..287b717
--- /dev/null
+++ b/include/configs/mgcoge2ne.h
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2007-2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MGCOGE2NE
+#define __MGCOGE2NE
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC8247
+#define CONFIG_MGCOGE
+#define CONFIG_HOSTNAME mgcoge2ne
+
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
+#include "km-powerpc.h"
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_FLASH_BASE 0xFE000000
+#define CONFIG_SYS_FLASH_SIZE 32
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /*
+ * max num of sects on one
+ * chip
+ */
+
+#define CONFIG_SYS_FLASH_BASE_1 0x50000000
+#define CONFIG_SYS_FLASH_SIZE_1 64
+#define CONFIG_SYS_FLASH_SIZE_2 0
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_FLASH_BASE_1 }
+
+#define MTDIDS_DEFAULT "nor2=app"
+
+/* include further common stuff for all keymile 82xx boards */
+#include "km82xx-common.h"
+
+#endif /* __MGCOGE2NE */
diff --git a/include/configs/mgcoge2un.h b/include/configs/mgcoge2un.h
new file mode 100644
index 0000000..d3c7bdc
--- /dev/null
+++ b/include/configs/mgcoge2un.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2010-2011
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* for linking errors see
+ * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
+
+#ifndef _CONFIG_MGCOGE2UN_H
+#define _CONFIG_MGCOGE2UN_H
+
+/* include common defines/options for all arm based Keymile boards */
+#include "km_arm.h"
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nKeymile MGCOGE2UN"
+
+#define CONFIG_HOSTNAME mgcoge2un
+
+#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
+#define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
+ "newenv=setenv addr 0x100000 && " \
+ "i2c dev 1; mw.b ${addr} 0 4 && " \
+ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
+ " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
+ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
+ " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \
+ "rootpath=/opt/eldk/arm\0" \
+ "EEprom_ivm=" KM_IVM_BUS "\0" \
+ ""
+
+#endif /* _CONFIG_MGCOGE2UN_H */
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 50caacd..6a785f8 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -48,6 +48,8 @@
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
+#define CONFIG_OF_LIBFDT 1
+
/*
* Size of malloc() pool
*/
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index 6ac910b..5749a08 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -38,6 +38,8 @@
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
+#define CONFIG_OF_LIBFDT 1
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 44a6eb7..c5e997c 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -52,6 +52,8 @@
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
+#define CONFIG_OF_LIBFDT 1
+
/*
* Size of malloc() pool
*/
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 7b6883c..39c87a8 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -55,6 +55,8 @@
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
+#define CONFIG_OF_LIBFDT 1
+
/*
* Size of malloc() pool
*/
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index 5ddf920..1d6ba7f 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -71,6 +71,8 @@
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
+#define CONFIG_OF_LIBFDT 1
+
/*
* Size of malloc() pool
* Total Size Environment - 256k
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 2bfda4b..5adffb5 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -61,6 +61,8 @@
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
+#define CONFIG_OF_LIBFDT 1
+
/*
* Size of malloc() pool
*/
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index dadca28..747c69d 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -62,6 +62,8 @@
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
+#define CONFIG_OF_LIBFDT 1
+
/*
* Size of malloc() pool
*/
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 2b03b0f..ffcc9aa 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -60,6 +60,8 @@
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
+#define CONFIG_OF_LIBFDT 1
+
/*
* Size of malloc() pool
* Total Size Environment - 256k
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 9a8bb73..8d04d07 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -56,6 +56,8 @@
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
+#define CONFIG_OF_LIBFDT 1
+
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
index 37a22a7..831af6a 100644
--- a/include/configs/pdm360ng.h
+++ b/include/configs/pdm360ng.h
@@ -64,8 +64,6 @@
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_VIDEO_XRES 800
-#define CONFIG_VIDEO_YRES 480
#endif
#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
diff --git a/include/configs/suen3.h b/include/configs/suen3.h
index b2730a3..2b6f19e 100644
--- a/include/configs/suen3.h
+++ b/include/configs/suen3.h
@@ -43,53 +43,14 @@
#define CONFIG_HOSTNAME suen3
-/*
- * Environment variables configurations
- */
-#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */
-#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50
-#define CONFIG_ENV_EEPROM_IS_ON_I2C 1
-#define CONFIG_SYS_EEPROM_WREN 1
-#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */
-#undef CONFIG_ENV_SIZE
-#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET)
-#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0"
-
-/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#define CONFIG_CMD_SF
-
-#define CONFIG_SPI_FLASH
-#define CONFIG_HARD_SPI
-#define CONFIG_KIRKWOOD_SPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50Mhz */
-
-#define FLASH_GPIO_PIN 0x00010000
-
-#define MTDIDS_DEFAULT "nand0=orion_nand"
-/* test-only: partitioning needs some tuning, this is just for tests */
-#define MTDPARTS_DEFAULT "mtdparts=" \
- "orion_nand:" \
- "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
-
-#define CONFIG_KM_DEF_ENV_UPDATE \
- "update=" \
- "spi on;sf probe 0;sf erase 0 50000;" \
- "sf write ${u-boot_addr_r} 0 ${filesize};" \
- "spi off\0"
+#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
- "memsize=0x8000000\0" \
"newenv=setenv addr 0x100000 && " \
"i2c dev 1; mw.b ${addr} 0 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
@@ -97,7 +58,7 @@
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \
"rootpath=/opt/eldk/arm\0" \
- "EEprom_ivm=pca9544a:70:9\0" \
+ "EEprom_ivm=" KM_IVM_BUS "\0" \
""
#endif /* _CONFIG_SUEN3_H */
diff --git a/include/configs/suen8.h b/include/configs/suen8.h
new file mode 100644
index 0000000..3f60bc3
--- /dev/null
+++ b/include/configs/suen8.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2010-2011
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* for linking errors see
+ * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
+
+#ifndef _CONFIG_SUEN8_H
+#define _CONFIG_SUEN8_H
+
+/* include common defines/options for all arm based Keymile boards */
+#include "km_arm.h"
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nKeymile SUEN8"
+
+#define CONFIG_HOSTNAME suen8
+
+#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
+ "newenv=setenv addr 0x100000 && " \
+ "i2c dev 1; mw.b ${addr} 0 4 && " \
+ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
+ " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
+ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
+ " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \
+ "rootpath=/opt/eldk/arm\0" \
+ "EEprom_ivm=" KM_IVM_BUS "\0" \
+ ""
+
+#endif /* _CONFIG_SUEN8_H */
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
new file mode 100644
index 0000000..d9eb201
--- /dev/null
+++ b/include/configs/suvd3.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SUVD3 /* SUVD3 board specific */
+#define CONFIG_HOSTNAME suvd3
+#define CONFIG_KM_BOARD_NAME "suvd3"
+
+#define CONFIG_SYS_TEXT_BASE 0xF0000000
+
+/* include common defines/options for all 8321 Keymile boards */
+#include "km8321-common.h"
+
+#define CONFIG_SYS_APP1_BASE 0xA0000000
+#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
+#define CONFIG_SYS_APP2_BASE 0xB0000000
+#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus Machine PortSz Size Device
+ * ---- --- ------- ------ ----- ------
+ * 2 Local UPMA 16 bit 256MB APP1
+ * 3 Local GPCM 16 bit 256MB APP2
+ *
+ */
+
+/*
+ * APP1 on the local bus CS2
+ */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
+
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
+ BR_PS_16 | \
+ BR_MS_UPMA | \
+ BR_V)
+#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
+
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
+ BR_PS_16 | \
+ BR_V)
+
+#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+ OR_GPCM_CSNT | \
+ OR_GPCM_ACS_DIV4 | \
+ OR_GPCM_SCY_3 | \
+ OR_GPCM_TRLX)
+
+#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
+ 0x0000c000 | \
+ MxMR_WLFx_2X)
+
+#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
+
+/*
+ * MMU Setup
+ */
+
+
+/* APP1: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
+
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index 2924325..febce35 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -47,6 +47,7 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
/* Environment */
#define CONFIG_ENV_IS_NOWHERE
diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h
new file mode 100644
index 0000000..1c0b3e0
--- /dev/null
+++ b/include/configs/tuda1.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2011
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_TUDA1 /* TUDA1 board specific */
+#define CONFIG_HOSTNAME tuda1
+#define CONFIG_KM_BOARD_NAME "tuda1"
+
+#define CONFIG_SYS_TEXT_BASE 0xF0000000
+
+/* include common defines/options for all 8321 Keymile boards */
+#include "km8321-common.h"
+
+#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
+#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
+#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */
+#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LBC_LBCR 0x00000000
+
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus Machine PortSz Size Device
+ * ---- --- ------- ------ ----- ------
+ * 2 Local GPCM 8 bit 256MB PAXG
+ * 3 Local GPCM 8 bit 256MB PINC3
+ *
+ */
+
+/*
+ * PAXG on the local bus CS2
+ */
+/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
+/* Window size: 256 MB */
+#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
+
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
+ BR_PS_8 | \
+ BR_MS_GPCM | \
+ BR_V)
+
+#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
+ OR_GPCM_CSNT | \
+ OR_GPCM_ACS_DIV4 | \
+ OR_GPCM_SCY_2 | \
+ (OR_GPCM_TRLX & \
+ (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
+ OR_GPCM_EAD)
+/*
+ * PINC3 on the local bus CS3
+ */
+/* Access window base at PINC3 base */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
+/* Window size: 256 MB */
+#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
+
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
+ BR_PS_8 | \
+ BR_MS_GPCM | \
+ BR_V)
+
+#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+ OR_GPCM_CSNT | \
+ (OR_GPCM_ACS_DIV2 & /* ACS = 11 */\
+ (~OR_GPCM_XACS)) | /* XACS = 0 */\
+ (OR_GPCM_SCY_2 & \
+ (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
+ OR_GPCM_TRLX)
+
+#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
+ 0x0000c000 | \
+ MxMR_WLFx_2X)
+
+/*
+ * MMU Setup
+ */
+/* PAXG: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \
+ BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+/* 512M should also include APP2... */
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \
+ BATU_BL_256M | \
+ BATU_VS | \
+ BATU_VP)
+#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \
+ BATL_PP_10 | \
+ BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
+
+/* PINC3: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \
+ BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \
+ BATU_BL_256M | \
+ BATU_VS | \
+ BATU_VP)
+#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \
+ BATL_PP_10 | \
+ BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
+
+#define CONFIG_SYS_IBAT7L (0)
+#define CONFIG_SYS_IBAT7U (0)
+#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h
new file mode 100644
index 0000000..012db96
--- /dev/null
+++ b/include/configs/tuxa1.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010
+ * Yan Bin, Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_TUXA1 /* TUXA1 board specific */
+#define CONFIG_HOSTNAME tuxa1
+#define CONFIG_KM_BOARD_NAME "tuxa1"
+
+#define CONFIG_SYS_TEXT_BASE 0xF0000000
+
+/* include common defines/options for all 8321 Keymile boards */
+#include "km8321-common.h"
+
+#define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */
+#define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */
+#define CONFIG_SYS_PINC2_BASE 0xB0000000 /* PINC2 */
+#define CONFIG_SYS_PINC2_SIZE 256 /* Megabytes */
+
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus Machine PortSz Size Device
+ * ---- --- ------- ------ ----- ------
+ * 2 Local GPCM 8 bit 256MB LPXF
+ * 3 Local GPCM 8 bit 256MB PINC2
+ *
+ */
+
+/*
+ * LPXF on the local bus CS2
+ * Window base at flash base
+ * Window size: 256 MB
+ */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
+
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \
+ BR_PS_8 | \
+ BR_MS_GPCM | \
+ BR_V)
+
+#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \
+ OR_GPCM_CSNT | \
+ OR_GPCM_ACS_DIV4 | \
+ OR_GPCM_SCY_2 | \
+ (OR_GPCM_TRLX & \
+ (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
+ OR_GPCM_EAD)
+/*
+ * PINC2 on the local bus CS3
+ * Access window base at PINC2 base
+ * Window size: 256 MB
+ */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PINC2_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
+
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PINC2_BASE | \
+ BR_PS_8 | \
+ BR_MS_GPCM | \
+ BR_V)
+
+#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \
+ OR_GPCM_CSNT | \
+ (OR_GPCM_ACS_DIV2 & /* ACS = 11 */ \
+ (~OR_GPCM_XACS)) | /* XACS = 0 */ \
+ (OR_GPCM_SCY_2 & \
+ (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
+ OR_GPCM_TRLX)
+
+#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
+ 0x0000c000 | \
+ MxMR_WLFx_2X)
+
+/*
+ * MMU Setup
+ */
+/* LPXF: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
+
+/* PINC2: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
+
+#define CONFIG_SYS_IBAT7L (0)
+#define CONFIG_SYS_IBAT7U (0)
+#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
+
+#endif /* __CONFIG_H */
diff --git a/include/fsl_diu_fb.h b/include/fsl_diu_fb.h
index 87443e1..4c89f4b 100644
--- a/include/fsl_diu_fb.h
+++ b/include/fsl_diu_fb.h
@@ -1,6 +1,7 @@
/*
- * Copyright 2007 Freescale Semiconductor, Inc.
- * York Sun <yorksun@freescale.com>
+ * Copyright 2007, 2011 Freescale Semiconductor, Inc.
+ * Authors: York Sun <yorksun@freescale.com>
+ * Timur Tabi <timur@freescale.com>
*
* FSL DIU Framebuffer driver
*
@@ -23,38 +24,8 @@
* MA 02111-1307 USA
*/
-struct fb_var_screeninfo {
- unsigned int xres; /* visible resolution */
- unsigned int yres;
+int fsl_diu_init(int xres, u32 pixel_format, int gamma_fix);
- unsigned int bits_per_pixel; /* guess what */
-
- /* Timing: All values in pixclocks, except pixclock (of course) */
- unsigned int pixclock; /* pixel clock in ps (pico seconds) */
- unsigned int left_margin; /* time from sync to picture */
- unsigned int right_margin; /* time from picture to sync */
- unsigned int upper_margin; /* time from sync to picture */
- unsigned int lower_margin;
- unsigned int hsync_len; /* length of horizontal sync */
- unsigned int vsync_len; /* length of vertical sync */
- unsigned int sync; /* see FB_SYNC_* */
- unsigned int vmode; /* see FB_VMODE_* */
- unsigned int rotate; /* angle we rotate counter clockwise */
-};
-
-struct fb_info {
- struct fb_var_screeninfo var; /* Current var */
- unsigned long smem_start; /* Start of frame buffer mem */
- /* (physical address) */
- unsigned int smem_len; /* Length of frame buffer mem */
- unsigned int type; /* see FB_TYPE_* */
- unsigned int line_length; /* length of a line in bytes */
-
- char *screen_base;
- unsigned long screen_size;
-};
-
-
-extern char *fsl_fb_open(struct fb_info **info);
-int fsl_diu_init(int xres, unsigned int pixel_format, int gamma_fix);
-int platform_diu_init(unsigned int *xres, unsigned int *yres);
+/* Prototypes for external board-specific functions */
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port);
+void diu_set_pixel_clock(unsigned int pixclock);
diff --git a/include/i2c.h b/include/i2c.h
index cd23c8a..8ceb4c8 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -108,9 +108,7 @@
* repeatedly to change the speed and slave addresses.
*/
void i2c_init(int speed, int slaveaddr);
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
void i2c_init_board(void);
-#endif
#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
void i2c_board_late_init(void);
#endif
diff --git a/include/ide.h b/include/ide.h
index 6a1b7ae..80a10f4 100644
--- a/include/ide.h
+++ b/include/ide.h
@@ -57,4 +57,11 @@ ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, void *buffer);
#if defined(CONFIG_OF_IDE_FIXUP)
int ide_device_present(int dev);
#endif
+
+#if defined(CONFIG_IDE_AHB)
+unsigned char ide_read_register(int dev, unsigned int port);
+void ide_write_register(int dev, unsigned int port, unsigned char val);
+void ide_read_data(int dev, ulong *sect_buf, int words);
+void ide_write_data(int dev, ulong *sect_buf, int words);
+#endif
#endif /* _IDE_H */
diff --git a/include/mmc.h b/include/mmc.h
index e0a56d9..f7f2286 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -14,7 +14,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -94,14 +94,14 @@
#define MMC_HS_TIMING 0x00000100
#define MMC_HS_52MHZ 0x2
-#define OCR_BUSY 0x80000000
-#define OCR_HCS 0x40000000
+#define OCR_BUSY 0x80000000
+#define OCR_HCS 0x40000000
#define OCR_VOLTAGE_MASK 0x007FFF80
#define OCR_ACCESS_MODE 0x60000000
#define MMC_STATUS_MASK (~0x0206BF7F)
-#define MMC_STATUS_RDY_FOR_DATA (1<<8)
-#define MMC_STATUS_CURR_STATE (0xf<<9)
+#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
+#define MMC_STATUS_CURR_STATE (0xf << 9)
#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
@@ -147,12 +147,12 @@
* EXT_CSD field definitions
*/
-#define EXT_CSD_CMD_SET_NORMAL (1<<0)
-#define EXT_CSD_CMD_SET_SECURE (1<<1)
-#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
+#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
+#define EXT_CSD_CMD_SET_SECURE (1 << 1)
+#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
-#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
-#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
@@ -162,21 +162,21 @@
#define R1_APP_CMD (1 << 5)
#define MMC_RSP_PRESENT (1 << 0)
-#define MMC_RSP_136 (1 << 1) /* 136 bit response */
-#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
-#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
-#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
+#define MMC_RSP_136 (1 << 1) /* 136 bit response */
+#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
+#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
+#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
-#define MMC_RSP_NONE (0)
-#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_NONE (0)
+#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
MMC_RSP_BUSY)
-#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
-#define MMC_RSP_R3 (MMC_RSP_PRESENT)
-#define MMC_RSP_R4 (MMC_RSP_PRESENT)
-#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
-#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
-#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
+#define MMC_RSP_R3 (MMC_RSP_PRESENT)
+#define MMC_RSP_R4 (MMC_RSP_PRESENT)
+#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
struct mmc_cid {
@@ -283,9 +283,7 @@ struct mmc {
struct mmc_cmd *cmd, struct mmc_data *data);
void (*set_ios)(struct mmc *mmc);
int (*init)(struct mmc *mmc);
-#ifdef CONFIG_MMC_MBLOCK
uint b_max;
-#endif
};
int mmc_register(struct mmc *mmc);