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-rw-r--r--include/configs/MPC8536DS.h95
1 files changed, 77 insertions, 18 deletions
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 9d45648..af36986 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -31,6 +31,12 @@
#define CONFIG_PHYS_64BIT 1
#endif
+#ifdef CONFIG_MK_NAND
+#define CONFIG_NAND_U_BOOT 1
+#define CONFIG_RAMBOOT_NAND 1
+#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
@@ -91,10 +97,21 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE (512 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
@@ -103,6 +120,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
+#else
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#endif
+
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
@@ -190,10 +213,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
-#define CONFIG_SYS_BR0_PRELIM \
+#define CONFIG_FLASH_BR_PRELIM \
(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
| BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
+#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
#define CONFIG_SYS_BR1_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
@@ -213,6 +236,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
@@ -265,6 +294,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define PIXIS_VWATCH 0x24 /* Watchdog Register */
#define PIXIS_LED 0x25 /* LED Register */
+#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
+
/* old pixis referenced names */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
@@ -282,12 +313,21 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+#ifndef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE 0xffa00000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
+#else
+#define CONFIG_SYS_NAND_BASE 0xfff00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#endif
+#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
CONFIG_SYS_NAND_BASE + 0x40000, \
CONFIG_SYS_NAND_BASE + 0x80000, \
@@ -298,6 +338,16 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START \
+ (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
/* NAND flash config */
#define CONFIG_NAND_BR_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
@@ -314,8 +364,17 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
| OR_FCM_TRLX \
| OR_FCM_EHTR)
+#ifdef CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
+#endif
#define CONFIG_SYS_BR4_PRELIM \
(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
@@ -536,15 +595,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_CMD_EXT2
#endif
-/*
- * USB
- */
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
@@ -579,14 +629,23 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR 0xfff80000
+
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+ #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+ #define CONFIG_ENV_IS_IN_FLASH 1
+ #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+ #define CONFIG_ENV_ADDR 0xfff80000
+ #else
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+ #endif
+ #define CONFIG_ENV_SIZE 0x2000
+ #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */