diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/ATUM8548.h | 3 | ||||
| -rw-r--r-- | include/configs/MPC8536DS.h | 6 | ||||
| -rw-r--r-- | include/configs/MPC8544DS.h | 5 | ||||
| -rw-r--r-- | include/configs/MPC8548CDS.h | 4 | ||||
| -rw-r--r-- | include/configs/MPC8568MDS.h | 3 | ||||
| -rw-r--r-- | include/configs/MPC8569MDS.h | 3 | ||||
| -rw-r--r-- | include/configs/MPC8572DS.h | 4 | ||||
| -rw-r--r-- | include/configs/MPC8610HPCD.h | 4 | ||||
| -rw-r--r-- | include/configs/MPC8641HPCN.h | 83 | ||||
| -rw-r--r-- | include/configs/P1022DS.h | 5 | ||||
| -rw-r--r-- | include/configs/P1_P2_RDB.h | 3 | ||||
| -rw-r--r-- | include/configs/P2020DS.h | 4 | ||||
| -rw-r--r-- | include/configs/TQM85xx.h | 4 | ||||
| -rw-r--r-- | include/configs/XPEDITE5170.h | 2 | ||||
| -rw-r--r-- | include/configs/XPEDITE5200.h | 1 | ||||
| -rw-r--r-- | include/configs/XPEDITE5370.h | 2 | ||||
| -rw-r--r-- | include/configs/sbc8548.h | 4 | ||||
| -rw-r--r-- | include/configs/sbc8641d.h | 53 | ||||
| -rw-r--r-- | include/fdt_support.h | 3 |
19 files changed, 69 insertions, 127 deletions
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index 49a86fd..c133033 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -91,9 +91,6 @@ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ #define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index a014ad0..890a6c9 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -65,6 +65,7 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#define CONFIG_SYS_HAS_SERDES /* has SERDES */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ @@ -125,11 +126,6 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) - /* DDR Setup */ #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index faba353..96fd024 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -79,11 +79,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index fdd3597..23594a7 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -80,10 +80,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 0cc2d47..bc6c5c7 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -75,9 +75,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index bb7bb47..92c2b49 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -103,9 +103,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR3 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 57c2f2f..51e5d06 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -89,10 +89,6 @@ #endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 8382e3c..4d9606e 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -82,10 +82,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) - #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000) /* DDR Setup */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 94e4d24..0d1f779 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -1,5 +1,5 @@ /* - * Copyright 2006 Freescale Semiconductor. + * Copyright 2006, 2010 Freescale Semiconductor. * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -58,8 +58,8 @@ #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ -#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ -#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #endif @@ -122,9 +122,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW #endif -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) - /* * DDR Setup */ @@ -328,43 +325,43 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x0000000c00000000ULL #else -#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_VIRT +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT #endif -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \ +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_PCIE1_IO_VIRT \ | CONFIG_SYS_PHYS_ADDR_HIGH) -#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */ +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ #ifdef CONFIG_PHYS_64BIT /* - * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT. + * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. * This will increase the amount of PCI address space available for * for mapping RAM. */ -#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS #else -#define CONFIG_SYS_PCI2_MEM_BUS (CONFIG_SYS_PCI1_MEM_BUS \ - + CONFIG_SYS_PCI1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ + + CONFIG_SYS_PCIE1_MEM_SIZE) #endif -#define CONFIG_SYS_PCI2_MEM_VIRT (CONFIG_SYS_PCI1_MEM_VIRT \ - + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \ - + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \ - + CONFIG_SYS_PCI1_IO_SIZE) -#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \ - + CONFIG_SYS_PCI1_IO_SIZE) -#define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE +#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ + + CONFIG_SYS_PCIE1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ + + CONFIG_SYS_PCIE1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ + + CONFIG_SYS_PCIE1_IO_SIZE) +#define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ + + CONFIG_SYS_PCIE1_IO_SIZE) +#define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE #if defined(CONFIG_PCI) @@ -393,10 +390,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 /*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT /*PCI video card used*/ -/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ +/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ /* video */ #define CONFIG_VIDEO @@ -409,7 +406,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ATI_RADEON_FB #define CONFIG_VIDEO_LOGO /*#define CONFIG_CONSOLE_CURSOR*/ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -425,8 +422,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE #endif -#define CONFIG_MPC86XX_PCI2 - #endif /* CONFIG_PCI */ #if defined(CONFIG_TSEC_ENET) @@ -497,17 +492,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U /* if CONFIG_PCI: - * BAT2 PCI1 and PCI1 MEM + * BAT2 PCIE1 and PCIE1 MEM * if CONFIG_RIO * BAT2 Rapidio Memory */ #ifdef CONFIG_PCI -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ +#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \ +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ +#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #else /* CONFIG_RIO */ @@ -556,14 +551,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* - * BAT4 PCI1_IO and PCI2_IO + * BAT4 PCIE1_IO and PCIE2_IO */ -#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ +#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \ +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ +#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index b42b5d0..f9d12f5 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -30,6 +30,7 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +#define CONFIG_SYS_HAS_SERDES /* has SERDES */ #define CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS @@ -60,10 +61,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* pci0 */ -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) /* pci1 */ -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) /* pci2 */ - /* DDR Setup */ #define CONFIG_DDR_SPD #define CONFIG_VERY_BIG_RAM diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 3cebbab..fca3cdd 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -129,9 +129,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 569da4f..bf2acbf 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -90,10 +90,6 @@ #endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR3 1 diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 90abe14..d8f2602 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -137,10 +137,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) - /* * DDR Setup */ diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h index c63fd42..8770a8d 100644 --- a/include/configs/XPEDITE5170.h +++ b/include/configs/XPEDITE5170.h @@ -97,8 +97,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* * Diagnostics diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index df5ef78..83aeffd 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -81,7 +81,6 @@ #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) /* * Diagnostics diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 1d6091c..fc4a986 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -99,8 +99,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* * Diagnostics diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 3f4056e..c8b8d0d 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -109,10 +109,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 315eebe..618513a 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -56,8 +56,8 @@ #define CONFIG_SYS_SCRATCH_VA 0xe8000000 #define CONFIG_PCI 1 /* Enable PCIE */ -#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ @@ -108,9 +108,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) - /* * DDR Setup */ @@ -307,23 +304,23 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS -#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BUS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS -#define CONFIG_SYS_PCI1_IO_VIRT CONFIG_SYS_PCI1_IO_BUS -#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS -#define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BUS -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BUS 0xe3000000 -#define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BUS -#define CONFIG_SYS_PCI2_IO_VIRT CONFIG_SYS_PCI2_IO_BUS -#define CONFIG_SYS_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 +#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS +#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS +#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ + +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 +#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS +#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS +#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ #if defined(CONFIG_PCI) @@ -409,10 +406,10 @@ * 0xa000_0000 512M PCI-Express 2 Memory * Changed it for operating from 0xd0000000 */ -#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ +#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U /* @@ -452,10 +449,10 @@ * 0xe300_0000 16M PCI-Express 2 I/0 * Note that this is at 0xe0000000 */ -#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \ +#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U /* diff --git a/include/fdt_support.h b/include/fdt_support.h index fc16159..54af9fe 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -83,6 +83,9 @@ int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size); void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size); void fdt_del_node_and_alias(void *blob, const char *alias); +u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr); +int fdt_node_offset_by_compat_reg(void *blob, const char *compat, + phys_addr_t compat_off); #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ |