summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/asm-ppc/fsl_law.h5
-rw-r--r--include/asm-ppc/fsl_lbc.h301
-rw-r--r--include/asm-ppc/global_data.h3
-rw-r--r--include/asm-ppc/io.h36
-rw-r--r--include/asm-ppc/ppc4xx-sdram.h1156
-rw-r--r--include/asm-ppc/processor.h17
-rw-r--r--include/configs/CPCI4052.h38
-rw-r--r--include/configs/CPCI405AB.h22
-rw-r--r--include/configs/CPCI405DT.h33
-rw-r--r--include/configs/MPC8315ERDB.h2
-rw-r--r--include/configs/MPC8349EMDS.h2
-rw-r--r--include/configs/MPC8349ITX.h4
-rw-r--r--include/configs/MPC8360EMDS.h2
-rw-r--r--include/configs/MPC8360ERDK.h2
-rw-r--r--include/configs/MPC837XEMDS.h2
-rw-r--r--include/configs/MPC8540ADS.h3
-rw-r--r--include/configs/MPC8541CDS.h3
-rw-r--r--include/configs/MPC8544DS.h6
-rw-r--r--include/configs/MPC8548CDS.h3
-rw-r--r--include/configs/MPC8555CDS.h3
-rw-r--r--include/configs/MPC8560ADS.h4
-rw-r--r--include/configs/MPC8568MDS.h1
-rw-r--r--include/configs/MPC8610HPCD.h2
-rw-r--r--include/configs/MPC8641HPCN.h1
-rw-r--r--include/configs/MVBLM7.h479
-rw-r--r--include/configs/SBC8540.h1
-rw-r--r--include/configs/TQM834x.h2
-rw-r--r--include/configs/TQM85xx.h380
-rw-r--r--include/configs/acadia.h169
-rw-r--r--include/configs/alpr.h1
-rw-r--r--include/configs/amcc-common.h259
-rw-r--r--include/configs/bamboo.h169
-rw-r--r--include/configs/bubinga.h150
-rw-r--r--include/configs/canyonlands.h173
-rw-r--r--include/configs/ebony.h152
-rw-r--r--include/configs/katmai.h163
-rw-r--r--include/configs/kilauea.h276
-rw-r--r--include/configs/luan.h148
-rw-r--r--include/configs/makalu.h272
-rw-r--r--include/configs/ocotea.h152
-rw-r--r--include/configs/sbc8560.h1
-rw-r--r--include/configs/scb9328.h4
-rw-r--r--include/configs/sequoia.h173
-rw-r--r--include/configs/socrates.h29
-rw-r--r--include/configs/stxgp3.h1
-rw-r--r--include/configs/stxssa.h1
-rw-r--r--include/configs/taihu.h146
-rw-r--r--include/configs/taishan.h161
-rw-r--r--include/configs/trizepsiv.h4
-rw-r--r--include/configs/walnut.h155
-rw-r--r--include/configs/yosemite.h164
-rw-r--r--include/configs/yucca.h152
-rw-r--r--include/linux/mtd/fsl_upm.h1
-rw-r--r--include/linux/mtd/mtd-abi.h2
-rw-r--r--include/mpc83xx.h235
-rw-r--r--include/mpc85xx.h37
-rw-r--r--include/mpc86xx.h2
-rw-r--r--include/pci_ids.h3
-rw-r--r--include/ppc405.h527
-rw-r--r--include/ppc440.h896
-rw-r--r--include/ppc4xx.h40
61 files changed, 3224 insertions, 4107 deletions
diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h
index e955c75..227bf83 100644
--- a/include/asm-ppc/fsl_law.h
+++ b/include/asm-ppc/fsl_law.h
@@ -6,6 +6,9 @@
#define SET_LAW_ENTRY(idx, a, sz, trgt) \
{ .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
+#define SET_LAW(a, sz, trgt) \
+ { .index = -1, .addr = a, .size = sz, .trgt_id = trgt }
+
enum law_size {
LAW_SIZE_4K = 0xb,
LAW_SIZE_8K,
@@ -70,6 +73,8 @@ struct law_entry {
};
extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
+extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
+extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern void disable_law(u8 idx);
extern void init_laws(void);
extern void print_laws(void);
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
new file mode 100644
index 0000000..c4af797
--- /dev/null
+++ b/include/asm-ppc/fsl_lbc.h
@@ -0,0 +1,301 @@
+/*
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __ASM_PPC_FSL_LBC_H
+#define __ASM_PPC_FSL_LBC_H
+
+#include <config.h>
+
+/* BR - Base Registers
+ */
+#define BR0 0x5000 /* Register offset to immr */
+#define BR1 0x5008
+#define BR2 0x5010
+#define BR3 0x5018
+#define BR4 0x5020
+#define BR5 0x5028
+#define BR6 0x5030
+#define BR7 0x5038
+
+#define BR_BA 0xFFFF8000
+#define BR_BA_SHIFT 15
+#define BR_PS 0x00001800
+#define BR_PS_SHIFT 11
+#define BR_PS_8 0x00000800 /* Port Size 8 bit */
+#define BR_PS_16 0x00001000 /* Port Size 16 bit */
+#define BR_PS_32 0x00001800 /* Port Size 32 bit */
+#define BR_DECC 0x00000600
+#define BR_DECC_SHIFT 9
+#define BR_DECC_OFF 0x00000000
+#define BR_DECC_CHK 0x00000200
+#define BR_DECC_CHK_GEN 0x00000400
+#define BR_WP 0x00000100
+#define BR_WP_SHIFT 8
+#define BR_MSEL 0x000000E0
+#define BR_MSEL_SHIFT 5
+#define BR_MS_GPCM 0x00000000 /* GPCM */
+#define BR_MS_FCM 0x00000020 /* FCM */
+#ifdef CONFIG_MPC83xx
+#define BR_MS_SDRAM 0x00000060 /* SDRAM */
+#elif defined(CONFIG_MPC85xx)
+#define BR_MS_SDRAM 0x00000000 /* SDRAM */
+#endif
+#define BR_MS_UPMA 0x00000080 /* UPMA */
+#define BR_MS_UPMB 0x000000A0 /* UPMB */
+#define BR_MS_UPMC 0x000000C0 /* UPMC */
+#if !defined(CONFIG_MPC834X)
+#define BR_ATOM 0x0000000C
+#define BR_ATOM_SHIFT 2
+#endif
+#define BR_V 0x00000001
+#define BR_V_SHIFT 0
+
+#define UPMA 0
+#define UPMB 1
+#define UPMC 2
+
+#if defined(CONFIG_MPC834X)
+#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
+#else
+#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
+#endif
+
+/* OR - Option Registers
+ */
+#define OR0 0x5004 /* Register offset to immr */
+#define OR1 0x500C
+#define OR2 0x5014
+#define OR3 0x501C
+#define OR4 0x5024
+#define OR5 0x502C
+#define OR6 0x5034
+#define OR7 0x503C
+
+#define OR_GPCM_AM 0xFFFF8000
+#define OR_GPCM_AM_SHIFT 15
+#define OR_GPCM_BCTLD 0x00001000
+#define OR_GPCM_BCTLD_SHIFT 12
+#define OR_GPCM_CSNT 0x00000800
+#define OR_GPCM_CSNT_SHIFT 11
+#define OR_GPCM_ACS 0x00000600
+#define OR_GPCM_ACS_SHIFT 9
+#define OR_GPCM_ACS_DIV2 0x00000600
+#define OR_GPCM_ACS_DIV4 0x00000400
+#define OR_GPCM_XACS 0x00000100
+#define OR_GPCM_XACS_SHIFT 8
+#define OR_GPCM_SCY 0x000000F0
+#define OR_GPCM_SCY_SHIFT 4
+#define OR_GPCM_SCY_1 0x00000010
+#define OR_GPCM_SCY_2 0x00000020
+#define OR_GPCM_SCY_3 0x00000030
+#define OR_GPCM_SCY_4 0x00000040
+#define OR_GPCM_SCY_5 0x00000050
+#define OR_GPCM_SCY_6 0x00000060
+#define OR_GPCM_SCY_7 0x00000070
+#define OR_GPCM_SCY_8 0x00000080
+#define OR_GPCM_SCY_9 0x00000090
+#define OR_GPCM_SCY_10 0x000000a0
+#define OR_GPCM_SCY_11 0x000000b0
+#define OR_GPCM_SCY_12 0x000000c0
+#define OR_GPCM_SCY_13 0x000000d0
+#define OR_GPCM_SCY_14 0x000000e0
+#define OR_GPCM_SCY_15 0x000000f0
+#define OR_GPCM_SETA 0x00000008
+#define OR_GPCM_SETA_SHIFT 3
+#define OR_GPCM_TRLX 0x00000004
+#define OR_GPCM_TRLX_SHIFT 2
+#define OR_GPCM_EHTR 0x00000002
+#define OR_GPCM_EHTR_SHIFT 1
+#define OR_GPCM_EAD 0x00000001
+#define OR_GPCM_EAD_SHIFT 0
+
+/* helpers to convert values into an OR address mask (GPCM mode) */
+#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
+#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
+
+#define OR_FCM_AM 0xFFFF8000
+#define OR_FCM_AM_SHIFT 15
+#define OR_FCM_BCTLD 0x00001000
+#define OR_FCM_BCTLD_SHIFT 12
+#define OR_FCM_PGS 0x00000400
+#define OR_FCM_PGS_SHIFT 10
+#define OR_FCM_CSCT 0x00000200
+#define OR_FCM_CSCT_SHIFT 9
+#define OR_FCM_CST 0x00000100
+#define OR_FCM_CST_SHIFT 8
+#define OR_FCM_CHT 0x00000080
+#define OR_FCM_CHT_SHIFT 7
+#define OR_FCM_SCY 0x00000070
+#define OR_FCM_SCY_SHIFT 4
+#define OR_FCM_SCY_1 0x00000010
+#define OR_FCM_SCY_2 0x00000020
+#define OR_FCM_SCY_3 0x00000030
+#define OR_FCM_SCY_4 0x00000040
+#define OR_FCM_SCY_5 0x00000050
+#define OR_FCM_SCY_6 0x00000060
+#define OR_FCM_SCY_7 0x00000070
+#define OR_FCM_RST 0x00000008
+#define OR_FCM_RST_SHIFT 3
+#define OR_FCM_TRLX 0x00000004
+#define OR_FCM_TRLX_SHIFT 2
+#define OR_FCM_EHTR 0x00000002
+#define OR_FCM_EHTR_SHIFT 1
+
+#define OR_UPM_AM 0xFFFF8000
+#define OR_UPM_AM_SHIFT 15
+#define OR_UPM_XAM 0x00006000
+#define OR_UPM_XAM_SHIFT 13
+#define OR_UPM_BCTLD 0x00001000
+#define OR_UPM_BCTLD_SHIFT 12
+#define OR_UPM_BI 0x00000100
+#define OR_UPM_BI_SHIFT 8
+#define OR_UPM_TRLX 0x00000004
+#define OR_UPM_TRLX_SHIFT 2
+#define OR_UPM_EHTR 0x00000002
+#define OR_UPM_EHTR_SHIFT 1
+#define OR_UPM_EAD 0x00000001
+#define OR_UPM_EAD_SHIFT 0
+
+#define OR_SDRAM_AM 0xFFFF8000
+#define OR_SDRAM_AM_SHIFT 15
+#define OR_SDRAM_XAM 0x00006000
+#define OR_SDRAM_XAM_SHIFT 13
+#define OR_SDRAM_COLS 0x00001C00
+#define OR_SDRAM_COLS_SHIFT 10
+#define OR_SDRAM_ROWS 0x000001C0
+#define OR_SDRAM_ROWS_SHIFT 6
+#define OR_SDRAM_PMSEL 0x00000020
+#define OR_SDRAM_PMSEL_SHIFT 5
+#define OR_SDRAM_EAD 0x00000001
+#define OR_SDRAM_EAD_SHIFT 0
+
+#define OR_AM_32KB 0xFFFF8000
+#define OR_AM_64KB 0xFFFF0000
+#define OR_AM_128KB 0xFFFE0000
+#define OR_AM_256KB 0xFFFC0000
+#define OR_AM_512KB 0xFFF80000
+#define OR_AM_1MB 0xFFF00000
+#define OR_AM_2MB 0xFFE00000
+#define OR_AM_4MB 0xFFC00000
+#define OR_AM_8MB 0xFF800000
+#define OR_AM_16MB 0xFF000000
+#define OR_AM_32MB 0xFE000000
+#define OR_AM_64MB 0xFC000000
+#define OR_AM_128MB 0xF8000000
+#define OR_AM_256MB 0xF0000000
+#define OR_AM_512MB 0xE0000000
+#define OR_AM_1GB 0xC0000000
+#define OR_AM_2GB 0x80000000
+#define OR_AM_4GB 0x00000000
+
+/* MxMR - UPM Machine A/B/C Mode Registers
+ */
+#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */
+#define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */
+#define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */
+#define MxMR_WLFx_1X 0x00000400 /* executed 1 time */
+#define MxMR_WLFx_2X 0x00000800 /* executed 2 times */
+#define MxMR_WLFx_3X 0x00000c00 /* executed 3 times */
+#define MxMR_WLFx_4X 0x00001000 /* executed 4 times */
+#define MxMR_WLFx_5X 0x00001400 /* executed 5 times */
+#define MxMR_WLFx_6X 0x00001800 /* executed 6 times */
+#define MxMR_WLFx_7X 0x00001c00 /* executed 7 times */
+#define MxMR_WLFx_8X 0x00002000 /* executed 8 times */
+#define MxMR_WLFx_9X 0x00002400 /* executed 9 times */
+#define MxMR_WLFx_10X 0x00002800 /* executed 10 times */
+#define MxMR_WLFx_11X 0x00002c00 /* executed 11 times */
+#define MxMR_WLFx_12X 0x00003000 /* executed 12 times */
+#define MxMR_WLFx_13X 0x00003400 /* executed 13 times */
+#define MxMR_WLFx_14X 0x00003800 /* executed 14 times */
+#define MxMR_WLFx_15X 0x00003c00 /* executed 15 times */
+#define MxMR_WLFx_16X 0x00000000 /* executed 16 times */
+#define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */
+#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */
+#define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */
+#define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */
+#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
+#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */
+#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */
+#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */
+#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */
+#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
+#define MxMR_OP_WARR 0x10000000 /* Write to Array */
+#define MxMR_OP_RARR 0x20000000 /* Read from Array */
+#define MxMR_OP_RUNP 0x30000000 /* Run Pattern */
+#define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */
+#define MxMR_RFEN 0x40000000 /* Refresh Enable */
+#define MxMR_BSEL 0x80000000 /* Bus Select */
+
+#define LBLAWAR_EN 0x80000000
+#define LBLAWAR_4KB 0x0000000B
+#define LBLAWAR_8KB 0x0000000C
+#define LBLAWAR_16KB 0x0000000D
+#define LBLAWAR_32KB 0x0000000E
+#define LBLAWAR_64KB 0x0000000F
+#define LBLAWAR_128KB 0x00000010
+#define LBLAWAR_256KB 0x00000011
+#define LBLAWAR_512KB 0x00000012
+#define LBLAWAR_1MB 0x00000013
+#define LBLAWAR_2MB 0x00000014
+#define LBLAWAR_4MB 0x00000015
+#define LBLAWAR_8MB 0x00000016
+#define LBLAWAR_16MB 0x00000017
+#define LBLAWAR_32MB 0x00000018
+#define LBLAWAR_64MB 0x00000019
+#define LBLAWAR_128MB 0x0000001A
+#define LBLAWAR_256MB 0x0000001B
+#define LBLAWAR_512MB 0x0000001C
+#define LBLAWAR_1GB 0x0000001D
+#define LBLAWAR_2GB 0x0000001E
+
+/* LBCR - Local Bus Configuration Register
+ */
+#define LBCR_LDIS 0x80000000
+#define LBCR_LDIS_SHIFT 31
+#define LBCR_BCTLC 0x00C00000
+#define LBCR_BCTLC_SHIFT 22
+#define LBCR_LPBSE 0x00020000
+#define LBCR_LPBSE_SHIFT 17
+#define LBCR_EPAR 0x00010000
+#define LBCR_EPAR_SHIFT 16
+#define LBCR_BMT 0x0000FF00
+#define LBCR_BMT_SHIFT 8
+
+/* LCRR - Clock Ratio Register
+ */
+#define LCRR_DBYP 0x80000000
+#define LCRR_DBYP_SHIFT 31
+#define LCRR_BUFCMDC 0x30000000
+#define LCRR_BUFCMDC_SHIFT 28
+#define LCRR_BUFCMDC_1 0x10000000
+#define LCRR_BUFCMDC_2 0x20000000
+#define LCRR_BUFCMDC_3 0x30000000
+#define LCRR_BUFCMDC_4 0x00000000
+#define LCRR_ECL 0x03000000
+#define LCRR_ECL_SHIFT 24
+#define LCRR_ECL_4 0x00000000
+#define LCRR_ECL_5 0x01000000
+#define LCRR_ECL_6 0x02000000
+#define LCRR_ECL_7 0x03000000
+#define LCRR_EADC 0x00030000
+#define LCRR_EADC_SHIFT 16
+#define LCRR_EADC_1 0x00010000
+#define LCRR_EADC_2 0x00020000
+#define LCRR_EADC_3 0x00030000
+#define LCRR_EADC_4 0x00000000
+#define LCRR_CLKDIV 0x0000000F
+#define LCRR_CLKDIV_SHIFT 0
+#define LCRR_CLKDIV_2 0x00000002
+#define LCRR_CLKDIV_4 0x00000004
+#define LCRR_CLKDIV_8 0x00000008
+
+#endif /* __ASM_PPC_FSL_LBC_H */
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index ea70266..8cf7b6f 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -96,6 +96,9 @@ typedef struct global_data {
uint mp_alloc_base;
uint mp_alloc_top;
#endif /* CONFIG_QE */
+#if defined(CONFIG_FSL_LAW)
+ u32 used_laws;
+#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
unsigned long pci_clk;
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 7cc28bf..c349681 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -238,6 +238,42 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val)
__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}
+/* Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+ out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+ out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+ out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
new file mode 100644
index 0000000..83931f1
--- /dev/null
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -0,0 +1,1156 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC4xx_SDRAM_H_
+#define _PPC4xx_SDRAM_H_
+
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_SDRAM)
+
+/*
+ * SDRAM Controller
+ */
+/*
+ * XXX - ToDo: Revisit file to change all these lower case defines into
+ * upper case. Also needs to be done in the controller setup code too
+ * of course. sr, 2008-06-02
+ */
+#ifndef CONFIG_405EP
+#define mem_besra 0x00 /* bus error syndrome reg a */
+#define mem_besrsa 0x04 /* bus error syndrome reg set a */
+#define mem_besrb 0x08 /* bus error syndrome reg b */
+#define mem_besrsb 0x0c /* bus error syndrome reg set b */
+#define mem_bear 0x10 /* bus error address reg */
+#endif
+#define mem_mcopt1 0x20 /* memory controller options 1 */
+#define mem_status 0x24 /* memory status */
+#define mem_rtr 0x30 /* refresh timer reg */
+#define mem_pmit 0x34 /* power management idle timer */
+#define mem_mb0cf 0x40 /* memory bank 0 configuration */
+#define mem_mb1cf 0x44 /* memory bank 1 configuration */
+#ifndef CONFIG_405EP
+#define mem_mb2cf 0x48 /* memory bank 2 configuration */
+#define mem_mb3cf 0x4c /* memory bank 3 configuration */
+#endif
+#define mem_sdtr1 0x80 /* timing reg 1 */
+#ifndef CONFIG_405EP
+#define mem_ecccf 0x94 /* ECC configuration */
+#define mem_eccerr 0x98 /* ECC error status */
+#endif
+
+#endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */
+
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
+
+/*
+ * Memory controller registers
+ */
+#define SDRAM_CFG0 0x20 /* memory controller options 0 */
+#define SDRAM_CFG1 0x21 /* memory controller options 1 */
+
+/*
+ * XXX - ToDo: Revisit file to change all these lower case defines into
+ * upper case. Also needs to be done in the controller setup code too
+ * of course. sr, 2008-06-02
+ */
+#define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
+#define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
+#define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */
+#define mem_besr1_set 0x000c /* bus error status reg 1 (set) */
+#define mem_bear 0x0010 /* bus error address reg */
+#define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */
+#define mem_mirq_set 0x0012 /* bus master interrupt (set) */
+#define mem_slio 0x0018 /* ddr sdram slave interface options */
+#define mem_cfg0 0x0020 /* ddr sdram options 0 */
+#define mem_cfg1 0x0021 /* ddr sdram options 1 */
+#define mem_devopt 0x0022 /* ddr sdram device options */
+#define mem_mcsts 0x0024 /* memory controller status */
+#define mem_rtr 0x0030 /* refresh timer register */
+#define mem_pmit 0x0034 /* power management idle timer */
+#define mem_uabba 0x0038 /* plb UABus base address */
+#define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */
+#define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */
+#define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */
+#define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */
+#define mem_tr0 0x0080 /* sdram timing register 0 */
+#define mem_tr1 0x0081 /* sdram timing register 1 */
+#define mem_clktr 0x0082 /* ddr clock timing register */
+#define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */
+#define mem_dlycal 0x0084 /* delay line calibration register */
+#define mem_eccesr 0x0098 /* ECC error status */
+
+/*
+ * Memory Controller Options 0
+ */
+#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
+#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
+#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
+#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
+#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
+#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
+#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
+#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
+#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
+#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
+#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
+#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
+
+/*
+ * Memory Controller Options 1
+ */
+#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
+#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
+
+/*
+ * SDRAM DEVPOT Options
+ */
+#define SDRAM_DEVOPT_DLL 0x80000000
+#define SDRAM_DEVOPT_DS 0x40000000
+
+/*
+ * SDRAM MCSTS Options
+ */
+#define SDRAM_MCSTS_MRSC 0x80000000
+#define SDRAM_MCSTS_SRMS 0x40000000
+#define SDRAM_MCSTS_CIS 0x20000000
+
+/*
+ * SDRAM Refresh Timer Register
+ */
+#define SDRAM_RTR_RINT_MASK 0xFFFF0000
+#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
+
+/*
+ * SDRAM UABus Base Address Reg
+ */
+#define SDRAM_UABBA_UBBA_MASK 0x0000000F
+
+/*
+ * Memory Bank 0-7 configuration
+ */
+#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
+#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
+#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
+#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
+#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
+#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
+#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
+#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
+#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
+#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
+#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
+#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
+#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
+#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
+#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
+
+/*
+ * SDRAM TR0 Options
+ */
+#define SDRAM_TR0_SDWR_MASK 0x80000000
+#define SDRAM_TR0_SDWR_2_CLK 0x00000000
+#define SDRAM_TR0_SDWR_3_CLK 0x80000000
+#define SDRAM_TR0_SDWD_MASK 0x40000000
+#define SDRAM_TR0_SDWD_0_CLK 0x00000000
+#define SDRAM_TR0_SDWD_1_CLK 0x40000000
+#define SDRAM_TR0_SDCL_MASK 0x01800000
+#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
+#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
+#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
+#define SDRAM_TR0_SDPA_MASK 0x000C0000
+#define SDRAM_TR0_SDPA_2_CLK 0x00040000
+#define SDRAM_TR0_SDPA_3_CLK 0x00080000
+#define SDRAM_TR0_SDPA_4_CLK 0x000C0000
+#define SDRAM_TR0_SDCP_MASK 0x00030000
+#define SDRAM_TR0_SDCP_2_CLK 0x00000000
+#define SDRAM_TR0_SDCP_3_CLK 0x00010000
+#define SDRAM_TR0_SDCP_4_CLK 0x00020000
+#define SDRAM_TR0_SDCP_5_CLK 0x00030000
+#define SDRAM_TR0_SDLD_MASK 0x0000C000
+#define SDRAM_TR0_SDLD_1_CLK 0x00000000
+#define SDRAM_TR0_SDLD_2_CLK 0x00004000
+#define SDRAM_TR0_SDRA_MASK 0x0000001C
+#define SDRAM_TR0_SDRA_6_CLK 0x00000000
+#define SDRAM_TR0_SDRA_7_CLK 0x00000004
+#define SDRAM_TR0_SDRA_8_CLK 0x00000008
+#define SDRAM_TR0_SDRA_9_CLK 0x0000000C
+#define SDRAM_TR0_SDRA_10_CLK 0x00000010
+#define SDRAM_TR0_SDRA_11_CLK 0x00000014
+#define SDRAM_TR0_SDRA_12_CLK 0x00000018
+#define SDRAM_TR0_SDRA_13_CLK 0x0000001C
+#define SDRAM_TR0_SDRD_MASK 0x00000003
+#define SDRAM_TR0_SDRD_2_CLK 0x00000001
+#define SDRAM_TR0_SDRD_3_CLK 0x00000002
+#define SDRAM_TR0_SDRD_4_CLK 0x00000003
+
+/*
+ * SDRAM TR1 Options
+ */
+#define SDRAM_TR1_RDSS_MASK 0xC0000000
+#define SDRAM_TR1_RDSS_TR0 0x00000000
+#define SDRAM_TR1_RDSS_TR1 0x40000000
+#define SDRAM_TR1_RDSS_TR2 0x80000000
+#define SDRAM_TR1_RDSS_TR3 0xC0000000
+#define SDRAM_TR1_RDSL_MASK 0x00C00000
+#define SDRAM_TR1_RDSL_STAGE1 0x00000000
+#define SDRAM_TR1_RDSL_STAGE2 0x00400000
+#define SDRAM_TR1_RDSL_STAGE3 0x00800000
+#define SDRAM_TR1_RDCD_MASK 0x00000800
+#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
+#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
+#define SDRAM_TR1_RDCT_MASK 0x000001FF
+#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
+#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
+#define SDRAM_TR1_RDCT_MIN 0x00000000
+#define SDRAM_TR1_RDCT_MAX 0x000001FF
+
+/*
+ * SDRAM WDDCTR Options
+ */
+#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
+#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
+#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
+#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
+#define SDRAM_WDDCTR_DCD_MASK 0x000001FF
+
+/*
+ * SDRAM CLKTR Options
+ */
+#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
+#define SDRAM_CLKTR_CLKP_0DEG 0x00000000
+#define SDRAM_CLKTR_CLKP_90DEG 0x40000000
+#define SDRAM_CLKTR_CLKP_180DEG 0x80000000
+#define SDRAM_CLKTR_DCDT_MASK 0x000001FF
+
+/*
+ * SDRAM DLYCAL Options
+ */
+#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
+#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
+#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
+
+#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR */
+
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
+
+#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
+#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
+#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
+
+/*
+ * Memory queue defines
+ */
+#define SDRAMQ_DCR_BASE 0x040
+
+#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
+#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
+#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
+#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
+#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
+#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
+#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
+#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
+#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
+#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
+#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
+#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
+#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
+#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
+#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
+
+#if !defined(CONFIG_405EX)
+/*
+ * Memory Bank 0-7 configuration
+ */
+#if defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
+#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFFE00000)>>2)
+#define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFFE00000)<<2)
+#endif /* CONFIG_440SPE */
+#if defined(CONFIG_440SP)
+#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
+#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFF800000))
+#define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFF800000))
+#endif /* CONFIG_440SP */
+#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
+#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((u32)(n))&0x3FF)<<6)
+#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((u32)(n))>>6)&0x3FF)
+#define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */
+#define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */
+#define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */
+#define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */
+#define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */
+#define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */
+#define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */
+#define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */
+#define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */
+#define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */
+#define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */
+#else /* CONFIG_405EX */
+/*
+ * XXX - ToDo:
+ * Revisit this file to check if all these 405EX defines are correct and
+ * can be used in the common 44x_spd_ddr2 code as well. sr, 2008-06-02
+ */
+#define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF)
+#define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0)
+#define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1)
+#define SDRAM_RXBAS_SDSZ_16MB PPC_REG_VAL(19, 0x2)
+#define SDRAM_RXBAS_SDSZ_32MB PPC_REG_VAL(19, 0x3)
+#define SDRAM_RXBAS_SDSZ_64MB PPC_REG_VAL(19, 0x4)
+#define SDRAM_RXBAS_SDSZ_128MB PPC_REG_VAL(19, 0x5)
+#define SDRAM_RXBAS_SDSZ_256MB PPC_REG_VAL(19, 0x6)
+#define SDRAM_RXBAS_SDSZ_512MB PPC_REG_VAL(19, 0x7)
+#define SDRAM_RXBAS_SDSZ_1024MB PPC_REG_VAL(19, 0x8)
+#define SDRAM_RXBAS_SDSZ_2048MB PPC_REG_VAL(19, 0x9)
+#define SDRAM_RXBAS_SDSZ_4096MB PPC_REG_VAL(19, 0xA)
+#define SDRAM_RXBAS_SDSZ_8192MB PPC_REG_VAL(19, 0xB)
+#define SDRAM_RXBAS_SDSZ_8 SDRAM_RXBAS_SDSZ_8MB
+#define SDRAM_RXBAS_SDSZ_16 SDRAM_RXBAS_SDSZ_16MB
+#define SDRAM_RXBAS_SDSZ_32 SDRAM_RXBAS_SDSZ_32MB
+#define SDRAM_RXBAS_SDSZ_64 SDRAM_RXBAS_SDSZ_64MB
+#define SDRAM_RXBAS_SDSZ_128 SDRAM_RXBAS_SDSZ_128MB
+#define SDRAM_RXBAS_SDSZ_256 SDRAM_RXBAS_SDSZ_256MB
+#define SDRAM_RXBAS_SDSZ_512 SDRAM_RXBAS_SDSZ_512MB
+#define SDRAM_RXBAS_SDSZ_1024 SDRAM_RXBAS_SDSZ_1024MB
+#define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB
+#define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB
+#define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB
+#define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0)
+#define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1)
+#define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2)
+#define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3)
+#define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4)
+#define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5)
+#define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6)
+#define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7)
+#define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8)
+#define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9)
+#define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0)
+#define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1)
+#endif /* CONFIG_405EX */
+
+/*
+ * Memory controller registers
+ */
+#define SDRAM_MCSTAT 0x14 /* memory controller status */
+#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
+#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
+#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
+#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
+#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
+#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
+#define SDRAM_CODT 0x26 /* on die termination for controller */
+#define SDRAM_VVPR 0x27 /* variable VRef programmming */
+#define SDRAM_OPARS 0x28 /* on chip driver control setup */
+#define SDRAM_OPART 0x29 /* on chip driver control trigger */
+#define SDRAM_RTR 0x30 /* refresh timer */
+#define SDRAM_PMIT 0x34 /* power management idle timer */
+#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
+#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
+#define SDRAM_MB2CF 0x48
+#define SDRAM_MB3CF 0x4C
+#define SDRAM_INITPLR0 0x50 /* manual initialization control */
+#define SDRAM_INITPLR1 0x51 /* manual initialization control */
+#define SDRAM_INITPLR2 0x52 /* manual initialization control */
+#define SDRAM_INITPLR3 0x53 /* manual initialization control */
+#define SDRAM_INITPLR4 0x54 /* manual initialization control */
+#define SDRAM_INITPLR5 0x55 /* manual initialization control */
+#define SDRAM_INITPLR6 0x56 /* manual initialization control */
+#define SDRAM_INITPLR7 0x57 /* manual initialization control */
+#define SDRAM_INITPLR8 0x58 /* manual initialization control */
+#define SDRAM_INITPLR9 0x59 /* manual initialization control */
+#define SDRAM_INITPLR10 0x5a /* manual initialization control */
+#define SDRAM_INITPLR11 0x5b /* manual initialization control */
+#define SDRAM_INITPLR12 0x5c /* manual initialization control */
+#define SDRAM_INITPLR13 0x5d /* manual initialization control */
+#define SDRAM_INITPLR14 0x5e /* manual initialization control */
+#define SDRAM_INITPLR15 0x5f /* manual initialization control */
+#define SDRAM_RQDC 0x70 /* read DQS delay control */
+#define SDRAM_RFDC 0x74 /* read feedback delay control */
+#define SDRAM_RDCC 0x78 /* read data capture control */
+#define SDRAM_DLCR 0x7A /* delay line calibration */
+#define SDRAM_CLKTR 0x80 /* DDR clock timing */
+#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
+#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
+#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
+#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
+#define SDRAM_MMODE 0x88 /* memory mode */
+#define SDRAM_MEMODE 0x89 /* memory extended mode */
+#define SDRAM_ECCCR 0x98 /* ECC error status */
+#define SDRAM_CID 0xA4 /* core ID */
+#define SDRAM_RID 0xA8 /* revision ID */
+#define SDRAM_RTSR 0xB1 /* run time status tracking */
+
+/*
+ * Memory Controller Status
+ */
+#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
+#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
+#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
+#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */
+#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
+#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */
+#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */
+#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */
+#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */
+
+/*
+ * Memory Controller Options 1
+ */
+#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/
+#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
+#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
+#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
+#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
+#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((u32)(n))>>28)&0x3)
+#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
+#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
+#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
+#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
+#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
+#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
+#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
+#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
+#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
+#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
+#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
+#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
+#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
+#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
+#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
+#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
+#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
+#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
+#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
+#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
+#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
+#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
+#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
+#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
+#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
+#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
+#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
+#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
+#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
+
+/*
+ * Memory Controller Options 2
+ */
+#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
+#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
+#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
+#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
+#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
+#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
+#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
+#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
+#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
+#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
+#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
+#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
+#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
+#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
+#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
+#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
+#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
+#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
+
+/*
+ * SDRAM Refresh Timer Register
+ */
+#define SDRAM_RTR_RINT_MASK 0xFFF80000
+#define SDRAM_RTR_RINT_ENCODE(n) ((((u32)(n))&0xFFF8)<<16)
+#define SDRAM_RTR_RINT_DECODE(n) ((((u32)(n))>>16)&0xFFF8)
+
+/*
+ * SDRAM Read DQS Delay Control Register
+ */
+#define SDRAM_RQDC_RQDE_MASK 0x80000000
+#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
+#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
+#define SDRAM_RQDC_RQFD_MASK 0x000001FF
+#define SDRAM_RQDC_RQFD_ENCODE(n) ((((u32)(n))&0x1FF)<<0)
+
+#define SDRAM_RQDC_RQFD_MAX 0x1FF
+
+/*
+ * SDRAM Read Data Capture Control Register
+ */
+#define SDRAM_RDCC_RDSS_MASK 0xC0000000
+#define SDRAM_RDCC_RDSS_T1 0x00000000
+#define SDRAM_RDCC_RDSS_T2 0x40000000
+#define SDRAM_RDCC_RDSS_T3 0x80000000
+#define SDRAM_RDCC_RDSS_T4 0xC0000000
+#define SDRAM_RDCC_RSAE_MASK 0x00000001
+#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
+#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
+
+/*
+ * SDRAM Read Feedback Delay Control Register
+ */
+#define SDRAM_RFDC_ARSE_MASK 0x80000000
+#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
+#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
+#define SDRAM_RFDC_RFOS_MASK 0x007F0000
+#define SDRAM_RFDC_RFOS_ENCODE(n) ((((u32)(n))&0x7F)<<16)
+#define SDRAM_RFDC_RFFD_MASK 0x000007FF
+#define SDRAM_RFDC_RFFD_ENCODE(n) ((((u32)(n))&0x7FF)<<0)
+
+#define SDRAM_RFDC_RFFD_MAX 0x7FF
+
+/*
+ * SDRAM Delay Line Calibration Register
+ */
+#define SDRAM_DLCR_DCLM_MASK 0x80000000
+#define SDRAM_DLCR_DCLM_MANUEL 0x80000000
+#define SDRAM_DLCR_DCLM_AUTO 0x00000000
+#define SDRAM_DLCR_DLCR_MASK 0x08000000
+#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
+#define SDRAM_DLCR_DLCR_IDLE 0x00000000
+#define SDRAM_DLCR_DLCS_MASK 0x07000000
+#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
+#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
+#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
+#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
+#define SDRAM_DLCR_DLCS_ERROR 0x04000000
+#define SDRAM_DLCR_DLCV_MASK 0x000001FF
+#define SDRAM_DLCR_DLCV_ENCODE(n) ((((u32)(n))&0x1FF)<<0)
+#define SDRAM_DLCR_DLCV_DECODE(n) ((((u32)(n))>>0)&0x1FF)
+
+/*
+ * SDRAM Controller On Die Termination Register
+ */
+#define SDRAM_CODT_ODT_ON 0x80000000
+#define SDRAM_CODT_ODT_OFF 0x00000000
+#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
+#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
+#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
+#define SDRAM_CODT_DQS_MASK 0x00000010
+#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
+#define SDRAM_CODT_DQS_SINGLE_END 0x00000010
+#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
+#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
+#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
+#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
+#define SDRAM_CODT_IO_HIZ 0x00000000
+#define SDRAM_CODT_IO_NMODE 0x00000001
+
+/*
+ * SDRAM Mode Register
+ */
+#define SDRAM_MMODE_WR_MASK 0x00000E00
+#define SDRAM_MMODE_WR_DDR1 0x00000000
+#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
+#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
+#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
+#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
+#define SDRAM_MMODE_DCL_MASK 0x00000070
+#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
+#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
+#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
+#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
+#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
+#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
+#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
+#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
+#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
+
+/*
+ * SDRAM Extended Mode Register
+ */
+#define SDRAM_MEMODE_DIC_MASK 0x00000002
+#define SDRAM_MEMODE_DIC_NORMAL 0x00000000
+#define SDRAM_MEMODE_DIC_WEAK 0x00000002
+#define SDRAM_MEMODE_DLL_MASK 0x00000001
+#define SDRAM_MEMODE_DLL_DISABLE 0x00000001
+#define SDRAM_MEMODE_DLL_ENABLE 0x00000000
+#define SDRAM_MEMODE_RTT_MASK 0x00000044
+#define SDRAM_MEMODE_RTT_DISABLED 0x00000000
+#define SDRAM_MEMODE_RTT_75OHM 0x00000004
+#define SDRAM_MEMODE_RTT_150OHM 0x00000040
+#define SDRAM_MEMODE_DQS_MASK 0x00000400
+#define SDRAM_MEMODE_DQS_DISABLE 0x00000400
+#define SDRAM_MEMODE_DQS_ENABLE 0x00000000
+
+/*
+ * SDRAM Clock Timing Register
+ */
+#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
+#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
+#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
+#define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000
+#define SDRAM_CLKTR_CLKP_270_DEG_ADV 0xC0000000
+
+/*
+ * SDRAM Write Timing Register
+ */
+#define SDRAM_WRDTR_LLWP_MASK 0x10000000
+#define SDRAM_WRDTR_LLWP_DIS 0x10000000
+#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
+#define SDRAM_WRDTR_WTR_MASK 0x0E000000
+#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
+#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000
+#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
+#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
+
+/*
+ * SDRAM SDTR1 Options
+ */
+#define SDRAM_SDTR1_LDOF_MASK 0x80000000
+#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
+#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
+#define SDRAM_SDTR1_RTW_MASK 0x00F00000
+#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
+#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
+#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
+#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
+#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
+#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
+#define SDRAM_SDTR1_RTRO_1_CLK 0x00001000
+#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
+
+/*
+ * SDRAM SDTR2 Options
+ */
+#define SDRAM_SDTR2_RCD_MASK 0xF0000000
+#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
+#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
+#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
+#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
+#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
+#define SDRAM_SDTR2_WTR_MASK 0x0F000000
+#define SDRAM_SDTR2_WTR_1_CLK 0x01000000
+#define SDRAM_SDTR2_WTR_2_CLK 0x02000000
+#define SDRAM_SDTR2_WTR_3_CLK 0x03000000
+#define SDRAM_SDTR2_WTR_4_CLK 0x04000000
+#define SDRAM_SDTR3_WTR_ENCODE(n) ((((u32)(n))&0xF)<<24)
+#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
+#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
+#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
+#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
+#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
+#define SDRAM_SDTR2_WPC_MASK 0x0000F000
+#define SDRAM_SDTR2_WPC_2_CLK 0x00002000
+#define SDRAM_SDTR2_WPC_3_CLK 0x00003000
+#define SDRAM_SDTR2_WPC_4_CLK 0x00004000
+#define SDRAM_SDTR2_WPC_5_CLK 0x00005000
+#define SDRAM_SDTR2_WPC_6_CLK 0x00006000
+#define SDRAM_SDTR3_WPC_ENCODE(n) ((((u32)(n))&0xF)<<12)
+#define SDRAM_SDTR2_RPC_MASK 0x00000F00
+#define SDRAM_SDTR2_RPC_2_CLK 0x00000200
+#define SDRAM_SDTR2_RPC_3_CLK 0x00000300
+#define SDRAM_SDTR2_RPC_4_CLK 0x00000400
+#define SDRAM_SDTR2_RP_MASK 0x000000F0
+#define SDRAM_SDTR2_RP_3_CLK 0x00000030
+#define SDRAM_SDTR2_RP_4_CLK 0x00000040
+#define SDRAM_SDTR2_RP_5_CLK 0x00000050
+#define SDRAM_SDTR2_RP_6_CLK 0x00000060
+#define SDRAM_SDTR2_RP_7_CLK 0x00000070
+#define SDRAM_SDTR2_RRD_MASK 0x0000000F
+#define SDRAM_SDTR2_RRD_2_CLK 0x00000002
+#define SDRAM_SDTR2_RRD_3_CLK 0x00000003
+
+/*
+ * SDRAM SDTR3 Options
+ */
+#define SDRAM_SDTR3_RAS_MASK 0x1F000000
+#define SDRAM_SDTR3_RAS_ENCODE(n) ((((u32)(n))&0x1F)<<24)
+#define SDRAM_SDTR3_RC_MASK 0x001F0000
+#define SDRAM_SDTR3_RC_ENCODE(n) ((((u32)(n))&0x1F)<<16)
+#define SDRAM_SDTR3_XCS_MASK 0x00001F00
+#define SDRAM_SDTR3_XCS 0x00000D00
+#define SDRAM_SDTR3_RFC_MASK 0x0000003F
+#define SDRAM_SDTR3_RFC_ENCODE(n) ((((u32)(n))&0x3F)<<0)
+
+/*
+ * Memory Bank 0-1 configuration
+ */
+#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
+#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
+#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
+#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
+#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
+#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
+#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
+#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
+#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
+#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
+#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
+#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
+#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
+#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
+
+#define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/
+#define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */
+#define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */
+#define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */
+#define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */
+
+#define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */
+
+#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */
+
+#if defined(CONFIG_SDRAM_PPC4xx_DENALI_DDR2)
+/*
+ * SDRAM Controller
+ */
+#define DDR0_00 0x00
+#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
+#define DDR0_00_INT_ACK_ALL 0x7F000000
+#define DDR0_00_INT_ACK_ENCODE(n) ((((u32)(n))&0x7F)<<24)
+#define DDR0_00_INT_ACK_DECODE(n) ((((u32)(n))>>24)&0x7F)
+/* Status */
+#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
+/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
+#define DDR0_00_INT_STATUS_BIT0 0x00010000
+/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
+#define DDR0_00_INT_STATUS_BIT1 0x00020000
+/* Bit2. Single correctable ECC event detected */
+#define DDR0_00_INT_STATUS_BIT2 0x00040000
+/* Bit3. Multiple correctable ECC events detected. */
+#define DDR0_00_INT_STATUS_BIT3 0x00080000
+/* Bit4. Single uncorrectable ECC event detected. */
+#define DDR0_00_INT_STATUS_BIT4 0x00100000
+/* Bit5. Multiple uncorrectable ECC events detected. */
+#define DDR0_00_INT_STATUS_BIT5 0x00200000
+/* Bit6. DRAM initialization complete. */
+#define DDR0_00_INT_STATUS_BIT6 0x00400000
+/* Bit7. Logical OR of all lower bits. */
+#define DDR0_00_INT_STATUS_BIT7 0x00800000
+
+#define DDR0_00_INT_STATUS_ENCODE(n) ((((u32)(n))&0xFF)<<16)
+#define DDR0_00_INT_STATUS_DECODE(n) ((((u32)(n))>>16)&0xFF)
+#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
+#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((u32)(n))&0x7F)<<8)
+#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((u32)(n))>>8)&0x7F)
+#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
+#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
+#define DDR0_00_DLL_START_POINT_DECODE(n) ((((u32)(n))>>0)&0x7F)
+
+#define DDR0_01 0x01
+#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
+#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((u32)(n))&0x1F)<<24)
+#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((u32)(n))>>24)&0x1F)
+#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
+#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((u32)(n))&0x1F)<<16)
+#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((u32)(n))>>16)&0x1F)
+#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
+#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((u32)(n))&0x7)<<8)
+#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((u32)(n))>>8)&0x7)
+#define DDR0_01_INT_MASK_MASK 0x000000FF
+#define DDR0_01_INT_MASK_ENCODE(n) ((((u32)(n))&0xFF)<<0)
+#define DDR0_01_INT_MASK_DECODE(n) ((((u32)(n))>>0)&0xFF)
+#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
+#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
+
+#define DDR0_02 0x02
+#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
+#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((u32)(n))&0x2)<<24)
+#define DDR0_02_MAX_CS_REG_DECODE(n) ((((u32)(n))>>24)&0x2)
+#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
+#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((u32)(n))&0xF)<<16)
+#define DDR0_02_MAX_COL_REG_DECODE(n) ((((u32)(n))>>16)&0xF)
+#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
+#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((u32)(n))&0xF)<<8)
+#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((u32)(n))>>8)&0xF)
+#define DDR0_02_START_MASK 0x00000001
+#define DDR0_02_START_ENCODE(n) ((((u32)(n))&0x1)<<0)
+#define DDR0_02_START_DECODE(n) ((((u32)(n))>>0)&0x1)
+#define DDR0_02_START_OFF 0x00000000
+#define DDR0_02_START_ON 0x00000001
+
+#define DDR0_03 0x03
+#define DDR0_03_BSTLEN_MASK 0x07000000
+#define DDR0_03_BSTLEN_ENCODE(n) ((((u32)(n))&0x7)<<24)
+#define DDR0_03_BSTLEN_DECODE(n) ((((u32)(n))>>24)&0x7)
+#define DDR0_03_CASLAT_MASK 0x00070000
+#define DDR0_03_CASLAT_ENCODE(n) ((((u32)(n))&0x7)<<16)
+#define DDR0_03_CASLAT_DECODE(n) ((((u32)(n))>>16)&0x7)
+#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
+#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((u32)(n))&0xF)<<8)
+#define DDR0_03_CASLAT_LIN_DECODE(n) ((((u32)(n))>>8)&0xF)
+#define DDR0_03_INITAREF_MASK 0x0000000F
+#define DDR0_03_INITAREF_ENCODE(n) ((((u32)(n))&0xF)<<0)
+#define DDR0_03_INITAREF_DECODE(n) ((((u32)(n))>>0)&0xF)
+
+#define DDR0_04 0x04
+#define DDR0_04_TRC_MASK 0x1F000000
+#define DDR0_04_TRC_ENCODE(n) ((((u32)(n))&0x1F)<<24)
+#define DDR0_04_TRC_DECODE(n) ((((u32)(n))>>24)&0x1F)
+#define DDR0_04_TRRD_MASK 0x00070000
+#define DDR0_04_TRRD_ENCODE(n) ((((u32)(n))&0x7)<<16)
+#define DDR0_04_TRRD_DECODE(n) ((((u32)(n))>>16)&0x7)
+#define DDR0_04_TRTP_MASK 0x00000700
+#define DDR0_04_TRTP_ENCODE(n) ((((u32)(n))&0x7)<<8)
+#define DDR0_04_TRTP_DECODE(n) ((((u32)(n))>>8)&0x7)
+
+#define DDR0_05 0x05
+#define DDR0_05_TMRD_MASK 0x1F000000
+#define DDR0_05_TMRD_ENCODE(n) ((((u32)(n))&0x1F)<<24)
+#define DDR0_05_TMRD_DECODE(n) ((((u32)(n))>>24)&0x1F)
+#define DDR0_05_TEMRS_MASK 0x00070000
+#define DDR0_05_TEMRS_ENCODE(n) ((((u32)(n))&0x7)<<16)
+#define DDR0_05_TEMRS_DECODE(n) ((((u32)(n))>>16)&0x7)
+#define DDR0_05_TRP_MASK 0x00000F00
+#define DDR0_05_TRP_ENCODE(n) ((((u32)(n))&0xF)<<8)
+#define DDR0_05_TRP_DECODE(n) ((((u32)(n))>>8)&0xF)
+#define DDR0_05_TRAS_MIN_MASK 0x000000FF
+#define DDR0_05_TRAS_MIN_ENCODE(n) ((((u32)(n))&0xFF)<<0)
+#define DDR0_05_TRAS_MIN_DECODE(n) ((((u32)(n))>>0)&0xFF)
+
+#define DDR0_06 0x06
+#define DDR0_06_WRITEINTERP_MASK 0x01000000
+#define DDR0_06_WRITEINTERP_ENCODE(n) ((((u32)(n))&0x1)<<24)
+#define DDR0_06_WRITEINTERP_DECODE(n) ((((u32)(n))>>24)&0x1)
+#define DDR0_06_TWTR_MASK 0x00070000
+#define DDR0_06_TWTR_ENCODE(n) ((((u32)(n))&0x7)<<16)
+#define DDR0_06_TWTR_DECODE(n) ((((u32)(n))>>16)&0x7)
+#define DDR0_06_TDLL_MASK 0x0000FF00
+#define DDR0_06_TDLL_ENCODE(n) ((((u32)(n))&0xFF)<<8)
+#define DDR0_06_TDLL_DECODE(n) ((((u32)(n))>>8)&0xFF)
+#define DDR0_06_TRFC_MASK 0x0000007F
+#define DDR0_06_TRFC_ENCODE(n) ((((u32)(n))&0x7F)<<0)
+#define DDR0_06_TRFC_DECODE(n) ((((u32)(n))>>0)&0x7F)
+
+#define DDR0_07 0x07
+#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
+#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((u32)(n))&0x1)<<24)
+#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((u32)(n))>>24)&0x1)
+#define DDR0_07_TFAW_MASK 0x001F0000
+#define DDR0_07_TFAW_ENCODE(n) ((((u32)(n))&0x1F)<<16)
+#define DDR0_07_TFAW_DECODE(n) ((((u32)(n))>>16)&0x1F)
+#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
+#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((u32)(n))&0x1)<<8)
+#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((u32)(n))>>8)&0x1)
+#define DDR0_07_AREFRESH_MASK 0x00000001
+#define DDR0_07_AREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<0)
+#define DDR0_07_AREFRESH_DECODE(n) ((((u32)(n))>>0)&0x1)
+
+#define DDR0_08 0x08
+#define DDR0_08_WRLAT_MASK 0x07000000
+#define DDR0_08_WRLAT_ENCODE(n) ((((u32)(n))&0x7)<<24)
+#define DDR0_08_WRLAT_DECODE(n) ((((u32)(n))>>24)&0x7)
+#define DDR0_08_TCPD_MASK 0x00FF0000
+#define DDR0_08_TCPD_ENCODE(n) ((((u32)(n))&0xFF)<<16)
+#define DDR0_08_TCPD_DECODE(n) ((((u32)(n))>>16)&0xFF)
+#define DDR0_08_DQS_N_EN_MASK 0x00000100
+#define DDR0_08_DQS_N_EN_ENCODE(n) ((((u32)(n))&0x1)<<8)
+#define DDR0_08_DQS_N_EN_DECODE(n) ((((u32)(n))>>8)&0x1)
+#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
+#define DDR0_08_DDRII_ENCODE(n) ((((u32)(n))&0x1)<<0)
+#define DDR0_08_DDRII_DECODE(n) ((((u32)(n))>>0)&0x1)
+
+#define DDR0_09 0x09
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<24)
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((u32)(n))>>24)&0x1F)
+#define DDR0_09_RTT_0_MASK 0x00030000
+#define DDR0_09_RTT_0_ENCODE(n) ((((u32)(n))&0x3)<<16)
+#define DDR0_09_RTT_0_DECODE(n) ((((u32)(n))>>16)&0x3)
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<8)
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>8)&0x7F)
+#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
+#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
+#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((u32)(n))>>0)&0x7F)
+
+#define DDR0_10 0x0A
+#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
+#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((u32)(n))&0x1)<<16)
+#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((u32)(n))>>16)&0x1)
+#define DDR0_10_CS_MAP_MASK 0x00000300
+#define DDR0_10_CS_MAP_NO_MEM 0x00000000
+#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
+#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
+#define DDR0_10_CS_MAP_ENCODE(n) ((((u32)(n))&0x3)<<8)
+#define DDR0_10_CS_MAP_DECODE(n) ((((u32)(n))>>8)&0x3)
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<0)
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((u32)(n))>>0)&0x1F)
+
+#define DDR0_11 0x0B
+#define DDR0_11_SREFRESH_MASK 0x01000000
+#define DDR0_11_SREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<24)
+#define DDR0_11_SREFRESH_DECODE(n) ((((u32)(n))>>24)&0x1F)
+#define DDR0_11_TXSNR_MASK 0x00FF0000
+#define DDR0_11_TXSNR_ENCODE(n) ((((u32)(n))&0xFF)<<16)
+#define DDR0_11_TXSNR_DECODE(n) ((((u32)(n))>>16)&0xFF)
+#define DDR0_11_TXSR_MASK 0x0000FF00
+#define DDR0_11_TXSR_ENCODE(n) ((((u32)(n))&0xFF)<<8)
+#define DDR0_11_TXSR_DECODE(n) ((((u32)(n))>>8)&0xFF)
+
+#define DDR0_12 0x0C
+#define DDR0_12_TCKE_MASK 0x0000007
+#define DDR0_12_TCKE_ENCODE(n) ((((u32)(n))&0x7)<<0)
+#define DDR0_12_TCKE_DECODE(n) ((((u32)(n))>>0)&0x7)
+
+#define DDR0_14 0x0E
+#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
+#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((u32)(n))&0x1)<<24)
+#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((u32)(n))>>24)&0x1)
+#define DDR0_14_REDUC_MASK 0x00010000
+#define DDR0_14_REDUC_64BITS 0x00000000
+#define DDR0_14_REDUC_32BITS 0x00010000
+#define DDR0_14_REDUC_ENCODE(n) ((((u32)(n))&0x1)<<16)
+#define DDR0_14_REDUC_DECODE(n) ((((u32)(n))>>16)&0x1)
+#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
+#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((u32)(n))&0x1)<<8)
+#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((u32)(n))>>8)&0x1)
+
+#define DDR0_17 0x11
+#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
+#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((u32)(n))&0x7F)<<24)
+#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((u32)(n))>>24)&0x7F)
+#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
+#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
+#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
+#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((u32)(n))&0x1)<<16)
+#define DDR0_17_DLLLOCKREG_DECODE(n) ((((u32)(n))>>16)&0x1)
+#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
+#define DDR0_17_DLL_LOCK_ENCODE(n) ((((u32)(n))&0x7F)<<8)
+#define DDR0_17_DLL_LOCK_DECODE(n) ((((u32)(n))>>8)&0x7F)
+
+#define DDR0_18 0x12
+#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
+#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
+#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((u32)(n))&0x7F)<<24)
+#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((u32)(n))>>24)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
+#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((u32)(n))&0x7F)<<16)
+#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((u32)(n))>>16)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
+#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((u32)(n))&0x7F)<<8)
+#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((u32)(n))>>8)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
+#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((u32)(n))&0x7F)<<0)
+#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((u32)(n))>>0)&0x7F)
+
+#define DDR0_19 0x13
+#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
+#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
+#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((u32)(n))&0x7F)<<24)
+#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((u32)(n))>>24)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
+#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((u32)(n))&0x7F)<<16)
+#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((u32)(n))>>16)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
+#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((u32)(n))&0x7F)<<8)
+#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((u32)(n))>>8)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
+#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((u32)(n))&0x7F)<<0)
+#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((u32)(n))>>0)&0x7F)
+
+#define DDR0_20 0x14
+#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
+#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((u32)(n))&0x7F)<<24)
+#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((u32)(n))>>24)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
+#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((u32)(n))&0x7F)<<16)
+#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((u32)(n))>>16)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
+#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((u32)(n))&0x7F)<<8)
+#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((u32)(n))>>8)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
+#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((u32)(n))&0x7F)<<0)
+#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((u32)(n))>>0)&0x7F)
+
+#define DDR0_21 0x15
+#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
+#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((u32)(n))&0x7F)<<24)
+#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((u32)(n))>>24)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
+#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((u32)(n))&0x7F)<<16)
+#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((u32)(n))>>16)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
+#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((u32)(n))&0x7F)<<8)
+#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((u32)(n))>>8)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
+#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((u32)(n))&0x7F)<<0)
+#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((u32)(n))>>0)&0x7F)
+
+#define DDR0_22 0x16
+#define DDR0_22_CTRL_RAW_MASK 0x03000000
+#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000
+#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000
+#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000
+#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000
+#define DDR0_22_CTRL_RAW_ENCODE(n) ((((u32)(n))&0x3)<<24)
+#define DDR0_22_CTRL_RAW_DECODE(n) ((((u32)(n))>>24)&0x3)
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<16)
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>16)&0x7F)
+#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
+#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<8)
+#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((u32)(n))>>8)&0x7F)
+#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
+#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((u32)(n))&0x7F)<<0)
+#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((u32)(n))>>0)&0x7F)
+
+#define DDR0_23 0x17
+#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
+#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<24)
+#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((u32)(n))>>24)&0x3)
+#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
+#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<16)
+#define DDR0_23_ECC_C_SYND_DECODE(n) ((((u32)(n))>>16)&0xFF)
+#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
+#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<8)
+#define DDR0_23_ECC_U_SYND_DECODE(n) ((((u32)(n))>>8)&0xFF)
+#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
+#define DDR0_23_FWC_ENCODE(n) ((((u32)(n))&0x1)<<0)
+#define DDR0_23_FWC_DECODE(n) ((((u32)(n))>>0)&0x1)
+
+#define DDR0_24 0x18
+#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
+#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((u32)(n))&0x3)<<24)
+#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((u32)(n))>>24)&0x3)
+#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
+#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<16)
+#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((u32)(n))>>16)&0x3)
+#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
+#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<8)
+#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((u32)(n))>>8)&0x3)
+#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
+#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<0)
+#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((u32)(n))>>0)&0x3)
+
+#define DDR0_25 0x19
+#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
+#define DDR0_25_VERSION_ENCODE(n) ((((u32)(n))&0xFFFF)<<16)
+#define DDR0_25_VERSION_DECODE(n) ((((u32)(n))>>16)&0xFFFF)
+#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
+#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((u32)(n))&0x3FF)<<0)
+#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((u32)(n))>>0)&0x3FF)
+
+#define DDR0_26 0x1A
+#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
+#define DDR0_26_TRAS_MAX_ENCODE(n) ((((u32)(n))&0xFFFF)<<16)
+#define DDR0_26_TRAS_MAX_DECODE(n) ((((u32)(n))>>16)&0xFFFF)
+#define DDR0_26_TREF_MASK 0x00003FFF
+#define DDR0_26_TREF_ENCODE(n) ((((u32)(n))&0x3FFF)<<0)
+#define DDR0_26_TREF_DECODE(n) ((((u32)(n))>>0)&0x3FFF)
+
+#define DDR0_27 0x1B
+#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
+#define DDR0_27_EMRS_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16)
+#define DDR0_27_EMRS_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF)
+#define DDR0_27_TINIT_MASK 0x0000FFFF
+#define DDR0_27_TINIT_ENCODE(n) ((((u32)(n))&0xFFFF)<<0)
+#define DDR0_27_TINIT_DECODE(n) ((((u32)(n))>>0)&0xFFFF)
+
+#define DDR0_28 0x1C
+#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
+#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16)
+#define DDR0_28_EMRS3_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF)
+#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
+#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<0)
+#define DDR0_28_EMRS2_DATA_DECODE(n) ((((u32)(n))>>0)&0x3FFF)
+
+#define DDR0_31 0x1F
+#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
+#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((u32)(n))&0xFFFF)<<0)
+#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((u32)(n))>>0)&0xFFFF)
+
+#define DDR0_32 0x20
+#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
+#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_33 0x21
+#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
+#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
+#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
+
+#define DDR0_34 0x22
+#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
+#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_35 0x23
+#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
+#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
+#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
+
+#define DDR0_36 0x24
+#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
+#define DDR0_36_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_37 0x25
+#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
+#define DDR0_37_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_38 0x26
+#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
+#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_39 0x27
+#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
+#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
+#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
+
+#define DDR0_40 0x28
+#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
+#define DDR0_40_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_41 0x29
+#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
+#define DDR0_41_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_42 0x2A
+#define DDR0_42_ADDR_PINS_MASK 0x07000000
+#define DDR0_42_ADDR_PINS_ENCODE(n) ((((u32)(n))&0x7)<<24)
+#define DDR0_42_ADDR_PINS_DECODE(n) ((((u32)(n))>>24)&0x7)
+#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
+#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((u32)(n))&0xF)<<0)
+#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((u32)(n))>>0)&0xF)
+
+#define DDR0_43 0x2B
+#define DDR0_43_TWR_MASK 0x07000000
+#define DDR0_43_TWR_ENCODE(n) ((((u32)(n))&0x7)<<24)
+#define DDR0_43_TWR_DECODE(n) ((((u32)(n))>>24)&0x7)
+#define DDR0_43_APREBIT_MASK 0x000F0000
+#define DDR0_43_APREBIT_ENCODE(n) ((((u32)(n))&0xF)<<16)
+#define DDR0_43_APREBIT_DECODE(n) ((((u32)(n))>>16)&0xF)
+#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
+#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((u32)(n))&0x7)<<8)
+#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((u32)(n))>>8)&0x7)
+#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
+#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
+#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
+#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((u32)(n))&0x1)<<0)
+#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((u32)(n))>>0)&0x1)
+
+#define DDR0_44 0x2C
+#define DDR0_44_TRCD_MASK 0x000000FF
+#define DDR0_44_TRCD_ENCODE(n) ((((u32)(n))&0xFF)<<0)
+#define DDR0_44_TRCD_DECODE(n) ((((u32)(n))>>0)&0xFF)
+
+#endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
+
+#endif /* _PPC4xx_SDRAM_H_ */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 8bdfb9d..139e686 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -460,17 +460,19 @@
#define SPRN_PID2 0x27a /* Process ID Register 2 */
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
#define SPRN_MCAR 0x23d /* Machine Check Address register */
-#ifdef CONFIG_440
#define MCSR_MCS 0x80000000 /* Machine Check Summary */
#define MCSR_IB 0x40000000 /* Instruction PLB Error */
+#if defined(CONFIG_440)
#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
+#else
+#define MCSR_DB 0x20000000 /* Data PLB Error */
+#endif /* defined(CONFIG_440) */
#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
-#endif
#define ESR_ST 0x00800000 /* Store Operation */
#if defined(CONFIG_MPC86xx)
@@ -960,6 +962,17 @@ n:
#define SR15 15
#ifndef __ASSEMBLY__
+
+struct cpu_type {
+ char name[15];
+ u32 soc_ver;
+};
+
+struct cpu_type *identify_cpu(uint ver);
+
+#define CPU_TYPE_ENTRY(n, v) \
+ { .name = #n, .soc_ver = SVR_##v, }
+
#ifndef CONFIG_MACH_SPECIFIC
extern int _machine;
extern int have_of;
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index b248639..fd49f56 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -88,32 +88,17 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
-
-#if 0 /* test-only */
-#define CONFIG_NETCONSOLE
-#define CONFIG_NET_MULTI
-
-#ifdef CONFIG_NET_MULTI
-#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */
-#endif
-#endif
-
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
-#if 0 /* test-only */
-#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
-#endif
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -256,29 +241,6 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*
- * JFFS2 partitions
- */
-
-/* No command line, one static partition, use whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT "nor0=cpci4052-0"
-#define MTDPARTS_DEFAULT "mtdparts=cpci4052-0:-(jffs2)"
-*/
-
#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
* NVRAM organization
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 1e9597d..55dd629 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -88,7 +88,6 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
@@ -238,27 +237,6 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT "nor0=cpci405ab-0"
-#define MTDPARTS_DEFAULT "mtdparts=cpci405ab-0:-(jffs2)"
-*/
-
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC32) for environment
*/
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index a8029ea..6b585be 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -87,23 +87,12 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
-
-#if 0 /* test-only */
-#define CONFIG_NETCONSOLE
-#define CONFIG_NET_MULTI
-
-#ifdef CONFIG_NET_MULTI
-#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */
-#endif
-#endif
-
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -260,27 +249,6 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT "nor0=cpci405dt-0"
-#define MTDPARTS_DEFAULT "mtdparts=cpci405dt-0:-(jffs2)"
-*/
-
#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
* NVRAM organization
@@ -416,7 +384,6 @@
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
/*
* Internal Definitions
*
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 7a5d0aa..095f665 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -203,7 +203,7 @@
#define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
- | OR_GPCM_ACS_0b11 \
+ | OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX \
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index bd77540..37e3ca4 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -157,7 +157,7 @@
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V) /* valid */
#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
- OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 38410a1..82d0686 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -211,7 +211,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V)
#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
- OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE
#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
@@ -236,7 +236,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_LED_BASE 0xF9000000
#define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V)
-#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
+#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
OR_GPCM_EHTR | OR_GPCM_EAD)
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index fcfbe6f..b4bff9a 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -203,7 +203,7 @@
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V) /* valid */
#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
- OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index adedcb9..ca8d53c 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -195,7 +195,7 @@
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V) /* valid */
#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
- OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
+ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_XACS | OR_GPCM_SCY_15 | \
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 4e159a0..0dd0279 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -239,7 +239,7 @@
#define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
- | OR_GPCM_ACS_0b11 \
+ | OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX \
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 5719759..d1d3cc3 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -87,9 +87,6 @@
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-
-#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 5b3ea05..a64565d 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -73,9 +73,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-
-#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index ffe9e00..669f4d7c 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -77,19 +77,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-
-#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000
-#define CFG_ALT_MEMTEST
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
@@ -171,6 +166,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index fc8ad88..acf6f0d 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -87,9 +87,6 @@ extern unsigned long get_clock_freq(void);
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-
-#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index e838345..1948c0d 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -73,9 +73,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-
-#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 9c95cc6..edf8525 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -40,6 +40,7 @@
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
+#define CONFIG_MPC8560 1
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
@@ -80,11 +81,8 @@
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-
#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
-#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index a7c69d2..9e6bb44 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -80,7 +80,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index a051b6d..fc16890 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -72,10 +72,8 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_R 1
-#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
-#define CFG_ALT_MEMTEST
/*
* Base addresses -- Note these are effective addresses where the
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 49ee7ff..455e154 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -87,7 +87,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
new file mode 100644
index 0000000..349ca14
--- /dev/null
+++ b/include/configs/MVBLM7.h
@@ -0,0 +1,479 @@
+/*
+ * Copyright (C) Matrix Vision GmbH 2008
+ *
+ * Matrix Vision mvBlueLYNX-M7 configuration file
+ * based on Freescale's MPC8349ITX.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define MV_VERSION "v1.0.1"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1
+#define CONFIG_MPC83XX 1
+#define CONFIG_MPC834X 1
+#define CONFIG_MPC8343 1
+
+#define CFG_IMMR 0xE0000000
+
+#define CONFIG_PCI
+#define CONFIG_83XX_GENERIC_PCI
+#define CONFIG_PCI_SKIP_HOST_BRIDGE
+#define CONFIG_HARD_I2C
+#define CONFIG_TSEC_ENET
+#define CONFIG_MPC8XXX_SPI
+#define CONFIG_HARD_SPI
+#define MVBLM7_MMC_CS 0x04000000
+
+/* I2C */
+#undef CONFIG_SOFT_I2C
+
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_OFFSET 0x3000
+#define CFG_I2C2_OFFSET 0x3100
+
+#define CFG_I2C_SPEED 100000
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE 0x00000000
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+#define CFG_83XX_DDR_USES_CS0 1
+#define CFG_MEMTEST_START (60<<20)
+#define CFG_MEMTEST_END (70<<20)
+
+#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+
+#define CFG_DDR_SIZE 256
+
+/* HC, 75Ohm, DDR-II, DRQ */
+#define CFG_DDRCDR 0x80000001
+/* EN, ODT_WR, 3BA, 14row, 10col */
+#define CFG_DDR_CS0_CONFIG 0x80014102
+#define CFG_DDR_CS1_CONFIG 0x0
+#define CFG_DDR_CS2_CONFIG 0x0
+#define CFG_DDR_CS3_CONFIG 0x0
+
+#define CFG_DDR_CS0_BNDS 0x0000000f
+#define CFG_DDR_CS1_BNDS 0x0
+#define CFG_DDR_CS2_BNDS 0x0
+#define CFG_DDR_CS3_BNDS 0x0
+
+#define CFG_DDR_CLK_CNTL 0x02000000
+
+#define CFG_DDR_TIMING_0 0x00260802
+#define CFG_DDR_TIMING_1 0x2625b221
+#define CFG_DDR_TIMING_2 0x1f9820c7
+#define CFG_DDR_TIMING_3 0x00000000
+
+/* ~MEM_EN, SREN, DDR-II, 32_BE */
+#define CFG_DDR_SDRAM_CFG 0x43080000
+#define CFG_DDR_SDRAM_CFG2 0x00401000
+#define CFG_DDR_INTERVAL 0x04060100
+
+#define CFG_DDR_MODE 0x078e0232
+
+/* Flash */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+#define CFG_FLASH_BASE 0xFF800000
+#define CFG_FLASH_SIZE 8
+#define CFG_FLASH_SIZE_SHIFT 3
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_ERASE_TOUT 60000
+#define CFG_FLASH_WRITE_TOUT 500
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 256
+
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V)
+#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
+ OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
+ OR_GPCM_EAD)
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE
+#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
+
+/*
+ * U-Boot memory configuration
+ */
+#define CFG_MONITOR_BASE TEXT_BASE
+#undef CFG_RAMBOOT
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
+#define CFG_MONITOR_LEN (512 * 1024)
+#define CFG_MALLOC_LEN (512 * 1024)
+
+/*
+ * Local Bus LCRR and LBCR regs
+ * LCRR: DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CFG_LBC_LBCR 0x00000000
+
+/* LB sdram refresh timer, about 6us */
+#define CFG_LBC_LSRT 0x32000000
+/* LB refresh timer prescal, 266MHz/32*/
+#define CFG_LBC_MRTPR 0x20000000
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_CONSOLE ttyS0
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500)
+#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+#define MV_DTB_NAME "mvblm7.dtb"
+
+/*
+ * PCI
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x10000000
+#define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE)
+#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE 0x10000000
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xE2000000
+#define CFG_PCI1_IO_SIZE 0x01000000
+
+#define _IO_BASE 0x00000000
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 3
+
+#define PCI_66M
+#define CONFIG_83XX_CLKIN 66666667
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+
+/* TSEC */
+#define CONFIG_GMII
+#define CFG_VSC8601_SKEWFIX
+#define CFG_VSC8601_SKEW_TX 3
+#define CFG_VSC8601_SKEW_RX 3
+
+#define CONFIG_TSEC1
+#define CONFIG_TSEC2
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_FEC1_PHY_NORXERR
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
+#define TSEC1_PHY_ADDR 0x10
+#define TSEC1_PHYIDX 0
+#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
+
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define CONFIG_FEC2_PHY_NORXERR
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
+#define TSEC2_PHY_ADDR 0x11
+#define TSEC2_PHYIDX 0
+#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
+
+#define CONFIG_ETHPRIME "TSEC0"
+
+#define CONFIG_BOOTP_VENDOREX
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_RANDOM_DELAY
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+/* USB */
+#define CONFIG_HAS_FSL_DR_USB
+
+/*
+ * Environment
+ */
+#undef CFG_FLASH_PROTECTION
+#define CONFIG_ENV_OVERWRITE
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0xFF800000
+#define CFG_ENV_SIZE 0x2000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO
+#define CFG_LOADS_BAUD_CHANGE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_FPGA
+
+#undef CONFIG_WATCHDOG
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+/* default load address */
+#define CFG_LOAD_ADDR 0x2000000
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 0x200000
+
+#define CFG_PROMPT "mvBL-M7> "
+#define CFG_CBSIZE 256
+
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE CFG_CBSIZE
+#define CFG_HZ 1000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+#define CFG_HRCW_LOW 0x0
+#define CFG_HRCW_HIGH 0x0
+
+/*
+ * System performance
+ */
+#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
+#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
+#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
+#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
+
+/* clocking */
+#define CFG_SCCR_ENCCM 0
+#define CFG_SCCR_USBMPHCM 0
+#define CFG_SCCR_USBDRCM 2
+#define CFG_SCCR_TSEC1CM 1
+#define CFG_SCCR_TSEC2CM 1
+
+#define CFG_SICRH 0x1fff8003
+#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
+
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL CFG_HID0_INIT
+
+#define CFG_HID2 HID2_HBE
+
+/* DDR */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI */
+#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
+ BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* no PCI2 */
+#define CFG_IBAT3L 0
+#define CFG_IBAT3U 0
+#define CFG_IBAT4L 0
+#define CFG_IBAT4U 0
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
+#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT7L 0
+#define CFG_IBAT7U 0
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+#define CFG_DBAT4L CFG_IBAT4L
+#define CFG_DBAT4U CFG_IBAT4U
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV eth0
+
+/* Default path and filenames */
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR "s"
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_RESET_TO_RETRY 1000
+
+#define MV_CI "mvBL-M7"
+#define MV_VCI "mvBL-M7"
+#define MV_FPGA_DATA "0xfff80000"
+#define MV_FPGA_SIZE "0x76ca2"
+#define MV_KERNEL_ADDR "0xff810000"
+#define MV_INITRD_ADDR "0xffc00000"
+#define MV_AUTOSCR_ADDR "0xff804000"
+#define MV_AUTOSCR_ADDR2 "0xff806000"
+#define MV_DTB_ADDR "0xff808000"
+#define MV_INITRD_LENGTH "0x00300000"
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define MV_KERNEL_ADDR_RAM "0x00100000"
+#define MV_DTB_ADDR_RAM "0x00600000"
+#define MV_INITRD_ADDR_RAM "0x01000000"
+
+#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \
+ then autoscr ${autoscr_addr}; \
+ else autoscr ${autoscr_addr2}; \
+ fi;"
+#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console_nr=0\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0" \
+ "fpga=0\0" \
+ "fpgadata=" MV_FPGA_DATA "\0" \
+ "fpgadatasize=" MV_FPGA_SIZE "\0" \
+ "autoscr_addr=" MV_AUTOSCR_ADDR "\0" \
+ "autoscr_addr2=" MV_AUTOSCR_ADDR2 "\0" \
+ "mv_kernel_addr=" MV_KERNEL_ADDR "\0" \
+ "mv_kernel_addr_ram=" MV_KERNEL_ADDR_RAM "\0" \
+ "mv_initrd_addr=" MV_INITRD_ADDR "\0" \
+ "mv_initrd_addr_ram=" MV_INITRD_ADDR_RAM "\0" \
+ "mv_initrd_length=" MV_INITRD_LENGTH "\0" \
+ "mv_dtb_addr=" MV_DTB_ADDR "\0" \
+ "mv_dtb_addr_ram=" MV_DTB_ADDR_RAM "\0" \
+ "dtb_name=" MV_DTB_NAME "\0" \
+ "mv_version=" MV_VERSION "\0" \
+ "dhcp_client_id=" MV_CI "\0" \
+ "dhcp_vendor-class-identifier=" MV_VCI "\0" \
+ "netretry=no\0" \
+ "use_static_ipaddr=no\0" \
+ "static_ipaddr=192.168.90.10\0" \
+ "static_netmask=255.255.255.0\0" \
+ "static_gateway=0.0.0.0\0" \
+ "initrd_name=uInitrd.mvblm7-xenorfs\0" \
+ "zcip=no\0" \
+ "netboot=yes\0" \
+ "mvtest=Ff\0" \
+ "tried_bootfromflash=no\0" \
+ "tried_bootfromnet=no\0" \
+ "bootfile=mvblm72625.boot\0" \
+ "use_dhcp=yes\0" \
+ "gev_start=yes\0" \
+ "mvbcdma_debug=0\0" \
+ "mvbcia_debug=0\0" \
+ "propdev_debug=0\0" \
+ "gevss_debug=0\0" \
+ "watchdog=0\0" \
+ "usb_dr_mode=host\0" \
+ ""
+
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA CFG_ALTERA_CYCLON2
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+
+#endif
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index ff64378..8a53fdd 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -49,6 +49,7 @@
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
+#define CONFIG_MPC8540 1
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 89fc465..0d2ca72 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -113,7 +113,7 @@ extern int tqm834x_num_flash_banks;
BR_MS_GPCM | BR_PS_32 | BR_V)
/* FLASH timing (0x0000_0c54) */
-#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \
+#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_5 | OR_GPCM_TRLX)
#define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index fca5f74..d18f234 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -1,4 +1,7 @@
/*
+ * (C) Copyright 2007
+ * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
+ *
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
@@ -27,7 +30,7 @@
*/
/*
- * TQM85xx (8560/40/55/41) board configuration file
+ * TQM85xx (8560/40/55/41/48) board configuration file
*/
#ifndef __CONFIG_H
@@ -39,25 +42,53 @@
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
#define CONFIG_PCI
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */
+#ifdef CONFIG_TQM8548
+#define CONFIG_PCI1
+#define CONFIG_PCIE1
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#endif
+
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+ /*
+ * Configuration for big NOR Flashes
+ *
+ * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
+ * Please be aware, that this changes the whole memory map (new CCSRBAR
+ * address, etc). You have to use an adapted Linux kernel or FDT blob
+ * if this option is set.
+ */
+#undef CONFIG_TQM_BIGFLASH
+
+/*
+ * NAND flash support (disabled by default)
+ *
+ * Warning: NAND support will likely increase the U-Boot image size
+ * to more than 256 KB. Please adjust TEXT_BASE if necessary.
+ */
+#undef CONFIG_NAND
+
/*
- * Only MPC8540 doesn't have CPM module
+ * MPC8540 and MPC8548 don't have CPM module
*/
-#ifndef CONFIG_MPC8540
+#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
#define CONFIG_CPM2 1 /* has CPM2 */
#endif
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+
+#undef CONFIG_CAN_DRIVER /* CAN Driver support */
/*
* sysclk for MPC85xx
*
* Two valid values are:
- * 33000000
- * 66000000
+ * 33333333
+ * 66666666
*
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
* is likely the desired value here, so that is now the default.
@@ -88,10 +119,18 @@
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_CCSRBAR 0xA0000000 /* relocated CCSRBAR */
+#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
+#endif /* CONFIG_TQM_BIGFLASH */
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+#define CFG_PCI1_ADDR (CFG_CCSRBAR + 0x8000)
+#define CFG_PCI2_ADDR (CFG_CCSRBAR + 0x9000)
+#define CFG_PCIE1_ADDR (CFG_CCSRBAR + 0xa000)
+
/*
* DDR Setup
*/
@@ -102,65 +141,116 @@
/* TQM8540 & 8560 need DLL-override */
#define CONFIG_DDR_DLL /* DLL fix needed */
#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
-#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */
+#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
-#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
+#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
+ defined(CONFIG_TQM8548)
#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
-#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */
+#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
+
+/*
+ * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM
+ * series while new boards have 'N' type Flashes from the S29GLxxxN
+ * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB.
+ */
+#ifdef CONFIG_TQM8548
+#define CONFIG_TQM_FLASH_N_TYPE
+#endif /* CONFIG_TQM8548 */
/*
* Flash on the Local Bus
*/
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_FLASH0 0xE0000000
+#define CFG_FLASH1 0xC0000000
+#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_FLASH0 0xFC000000
#define CFG_FLASH1 0xF8000000
+#endif /* CONFIG_TQM_BIGFLASH */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
-#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
+#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
+/* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
+ *
+ * Note: According to timing specifications external addr latch delay
+ * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
+ *
+ * For other Local Bus Clocks see following table:
+ *
+ * Clock/MHz CFG_ORx_PRELIM
+ * 166 0x.....CA5
+ * 133 0x.....C85
+ * 100 0x.....C65
+ * 83 0x.....FA2
+ * 66 0x.....C82
+ * 50 0x.....C60
+ * 42 0x.....040
+ * 33 0x.....030
+ * 25 0x.....020
+ *
+ */
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_BR0_PRELIM 0xE0001801 /* port size 32bit */
+#define CFG_OR0_PRELIM 0xE0000040 /* 512MB Flash */
+#define CFG_BR1_PRELIM 0xC0001801 /* port size 32bit */
+#define CFG_OR1_PRELIM 0xE0000040 /* 512MB Flash */
+#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */
#define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */
#define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */
#define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */
+#endif /* CONFIG_TQM_BIGFLASH */
-#define CFG_FLASH_CFI /* flash is CFI compat. */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
+#define CFG_FLASH_CFI /* flash is CFI compat. */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */
-#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
-#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
+#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
+#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
-#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
-#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
+/*
+ * Note: when changing the Local Bus clock divider you have to
+ * change the timing values in CFG_ORx_PRELIM.
+ *
+ * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
+ * LCRR[16:17] EADC : External address delay cycles. It should be set to 2
+ * for Local Bus Clock > 83.3 MHz.
+ */
+#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
+#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
-#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_INIT_RAM_ADDR (CFG_CCSRBAR \
+ + 0x04010000) /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (~TEXT_BASE + 1)/* Reserved for Monitor */
+#define CFG_MALLOC_LEN (384 * 1024) /* Reserved for malloc */
/* Serial Port */
#if defined(CONFIG_TQM8560)
-#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
+#define CONFIG_CONS_ON_SCC /* define if console on SCC */
+#undef CONFIG_CONS_NONE /* define if console on something else */
+#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-#else /* ! TQM8560 */
+#else /* !CONFIG_TQM8560 */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
@@ -173,20 +263,18 @@
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* PS/2 Keyboard */
-#if !defined(CONFIG_TQM8560)
#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
#define CONFIG_BOARD_EARLY_INIT_R 1
-#endif /* !CONFIG_TQM8560 */
#endif /* CONFIG_TQM8560 */
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 115200
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
@@ -194,11 +282,25 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/* CAN */
+#define CFG_CAN_BASE (CFG_CCSRBAR \
+ + 0x03000000) /* CAN base address */
+#ifdef CONFIG_CAN_DRIVER
+#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */
+#define CFG_OR2_CAN (CFG_CAN_OR_AM | OR_UPM_BI)
+#define CFG_BR2_CAN ((CFG_CAN_BASE & BR_BA) | \
+ BR_PS_8 | BR_MS_UPMC | BR_V)
+#endif /* CONFIG_CAN_DRIVER */
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
@@ -219,7 +321,7 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
+#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
@@ -228,10 +330,64 @@
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
+#ifndef CONFIG_PCIE1
/* RapidIO MMU */
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_RIO_MEM_BASE 0xb0000000 /* base address */
+#define CFG_RIO_MEM_SIZE 0x10000000 /* 256M */
+#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
+#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
+#endif /* CONFIG_TQM_BIGFLASH */
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
-#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
+#endif /* CONFIG_PCIE1 */
+
+/* NAND FLASH */
+#ifdef CONFIG_NAND
+
+#undef CFG_NAND_LEGACY
+
+#define CONFIG_NAND_FSL_UPM 1
+
+#define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */
+
+/* address distance between chip selects */
+#define CFG_NAND_SELECT_DEVICE 1
+#define CFG_NAND_CS_DIST 0x200
+
+#define CFG_NAND_SIZE 0x8000
+#define CFG_NAND0_BASE (CFG_CCSRBAR + 0x03010000)
+#define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST)
+#define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST)
+#define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST)
+
+#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+
+#if (CFG_MAX_NAND_DEVICE == 1)
+#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
+#elif (CFG_MAX_NAND_DEVICE == 2)
+#define CFG_NAND_QUIET_TEST 1
+#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
+ CFG_NAND1_BASE, \
+}
+#elif (CFG_MAX_NAND_DEVICE == 4)
+#define CFG_NAND_QUIET_TEST 1
+#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
+ CFG_NAND1_BASE, \
+ CFG_NAND2_BASE, \
+ CFG_NAND3_BASE, \
+}
+#endif
+
+/* CS3 for NAND Flash */
+#define CFG_BR3_PRELIM ((CFG_NAND0_BASE & BR_BA) | BR_PS_8 | \
+ BR_MS_UPMB | BR_V)
+#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_NAND_SIZE) | OR_UPM_BI)
+
+#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
+
+#endif /* CONFIG_NAND */
/*
* General PCI
@@ -240,9 +396,33 @@
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
+#define CFG_PCI1_IO_BASE (CFG_CCSRBAR + 0x02000000)
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
+#ifdef CONFIG_PCIE1
+/*
+ * General PCI express
+ * Addresses are mapped 1-1.
+ */
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_PCIE1_MEM_BASE 0xb0000000
+#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 512M */
+#define CFG_PCIE1_IO_BASE 0xaf000000
+#else /* !CONFIG_TQM_BIGFLASH */
+#define CFG_PCIE1_MEM_BASE 0xc0000000
+#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCIE1_IO_BASE 0xef000000
+#endif /* CONFIG_TQM_BIGFLASH */
+#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_IO_PHYS CFG_PCIE1_IO_BASE
+#define CFG_PCIE1_IO_SIZE 0x1000000 /* 16M */
+#endif /* CONFIG_PCIE1 */
#if defined(CONFIG_PCI)
@@ -254,8 +434,7 @@
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-#endif /* CONFIG_PCI */
-
+#endif /* CONFIG_PCI */
#define CONFIG_NET_MULTI 1
@@ -277,6 +456,27 @@
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
+#ifdef CONFIG_TQM8548
+/*
+ * TQM8548 has 4 ethernet ports. 4 ETSEC's.
+ *
+ * On the STK85xx Starterkit the ETSEC3/4 ports are on an
+ * additional adapter (AIO) between module and Starterkit.
+ */
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "TSEC2"
+#define CONFIG_TSEC4 1
+#define CONFIG_TSEC4_NAME "TSEC3"
+#define TSEC3_PHY_ADDR 4
+#define TSEC4_PHY_ADDR 5
+#define TSEC3_PHYIDX 0
+#define TSEC4_PHYIDX 0
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define CONFIG_HAS_ETH3
+#define CONFIG_HAS_ETH4
+#endif /* CONFIG_TQM8548 */
+
/* Options are TSEC[0-1], FEC */
#define CONFIG_ETHPRIME "TSEC0"
@@ -305,7 +505,7 @@
* FCC2: a - c (X50.2 - 1)
*/
#define CONFIG_ETHER_ON_FCC
-#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
+#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
#endif
#if defined(CONFIG_TQM8560)
@@ -321,12 +521,13 @@
* FCC3: a - d (X50.2 - 3)
*/
#define CONFIG_ETHER_ON_FCC
-#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
+#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
#endif
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
#define CONFIG_ETHER_ON_FCC1
-#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
+ CMXFCR_TF1CS_MSK)
#define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
@@ -334,7 +535,8 @@
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
#define CONFIG_ETHER_ON_FCC2
-#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
+ CMXFCR_TF2CS_MSK)
#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
@@ -342,7 +544,8 @@
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
#define CONFIG_ETHER_ON_FCC3
-#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
+ CMXFCR_TF3CS_MSK)
#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
@@ -352,17 +555,21 @@
* Environment
*/
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
-#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+
+#ifdef CONFIG_TQM_FLASH_N_TYPE
+#define CFG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */
+#else /* !CONFIG_TQM_FLASH_N_TYPE */
+#define CFG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
+#endif /* CONFIG_TQM_FLASH_N_TYPE */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000
-#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_TIMESTAMP /* Print image info with ts */
-
+#define CONFIG_TIMESTAMP /* Print image info with ts */
/*
* BOOTP options
@@ -372,6 +579,25 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
+#ifdef CONFIG_NAND
+/*
+ * Use NAND-FLash as JFFS2 device
+ */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_JFFS2
+
+#define CONFIG_JFFS2_NAND 1
+
+#ifdef CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nand0=TQM85xx-nand"
+#define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-"
+#else
+#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
+#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_SIZE 0x200000 /* size of jffs2 partition */
+#endif /* CONFIG_JFFS2_CMDLINE */
+
+#endif /* CONFIG_NAND */
/*
* Command line configuration.
@@ -389,10 +615,9 @@
#define CONFIG_CMD_MII
#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI
#endif
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
@@ -403,12 +628,13 @@
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
- #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
- #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
+#define CFG_PBSIZE (CFG_CBSIZE + \
+ sizeof(CFG_PROMPT) + 16) /* Print Buf Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
@@ -433,7 +659,6 @@
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
-
#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
@@ -444,10 +669,26 @@
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+/*
+ * Setup some board specific values for the default environment variables
+ */
+#ifdef CONFIG_CPM2
+#define CFG_ENV_CONSDEV "consdev=ttyCPM0\0"
+#else
+#define CFG_ENV_CONSDEV "consdev=ttyS0\0"
+#endif
+#define CFG_ENV_FDT_FILE "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
+ MK_STR(CONFIG_HOSTNAME)".dtb\0"
+#define CFG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
+#define CFG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
+ "uboot_addr="MK_STR(TEXT_BASE)"\0"
+
#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootfile="CFG_BOOTFILE_PATH"\0" \
+ CFG_ENV_BOOTFILE \
+ CFG_ENV_FDT_FILE \
+ CFG_ENV_CONSDEV \
"netdev=eth0\0" \
- "consdev=ttyS0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -457,20 +698,27 @@
"addcons=setenv bootargs $bootargs " \
"console=$consdev,$baudrate\0" \
"flash_nfs=run nfsargs addip addcons;" \
- "bootm $kernel_addr\0" \
+ "bootm $kernel_addr - $fdt_addr\0" \
"flash_self=run ramargs addip addcons;" \
- "bootm $kernel_addr $ramdisk_addr\0" \
- "net_nfs=tftp $loadaddr $bootfile;" \
- "run nfsargs addip addcons;bootm\0" \
+ "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
+ "net_nfs=tftp $kernel_addr_r $bootfile;" \
+ "tftp $fdt_addr_r $fdt_file;" \
+ "run nfsargs addip addcons;" \
+ "bootm $kernel_addr_r - $fdt_addr_r\0" \
"rootpath=/opt/eldk/ppc_85xx\0" \
- "kernel_addr=FE000000\0" \
- "ramdisk_addr=FE180000\0" \
- "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \
- "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
- "cp.b 100000 fffc0000 40000;" \
+ "fdt_addr_r=900000\0" \
+ "kernel_addr_r=1000000\0" \
+ "fdt_addr=ffec0000\0" \
+ "kernel_addr=ffd00000\0" \
+ "ramdisk_addr=ff800000\0" \
+ CFG_ENV_UBOOT \
+ "load=tftp 100000 $uboot\0" \
+ "update=protect off $uboot_addr +$filesize;" \
+ "erase $uboot_addr +$filesize;" \
+ "cp.b 100000 $uboot_addr $filesize;" \
"setenv filesize;saveenv\0" \
"upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_H */
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index bbf726d..9092a7c 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -34,6 +34,13 @@
#define CONFIG_ACADIA 1 /* Board is Acadia */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME acadia
+#include "amcc-common.h"
+
/* Detect Acadia PLL input clock automatically via CPLD bit */
#define CONFIG_SYS_CLK_FREQ ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \
66666666 : 33333000)
@@ -59,16 +66,11 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xfe000000
#define CFG_CPLD_BASE 0x80000000
#define CFG_NAND_ADDR 0xd0000000
#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1)
-#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */
-
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer
*----------------------------------------------------------------------*/
@@ -89,12 +91,6 @@
*----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#define CFG_BASE_BAUD 691200
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/*-----------------------------------------------------------------------
* Environment
@@ -202,10 +198,7 @@
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
@@ -222,77 +215,24 @@
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
-#if 0 /* test-only... */
-/*-----------------------------------------------------------------------
- * SPI stuff - Define to include SPI control
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SPI
-#endif
-
/*-----------------------------------------------------------------------
* Ethernet
*----------------------------------------------------------------------*/
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_NET_MULTI 1
-#define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/
#define CONFIG_HAS_ETH0 1
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define xstr(s) str(s)
-#define str(s) #s
-
+/*
+ * Default environment variables
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=acadia\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=acadia/uImage\0" \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_PPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fff10000\0" \
"ramdisk_addr=fff20000\0" \
- "initrd_high=30000000\0" \
- "load=tftp 200000 acadia/u-boot.bin\0" \
- "update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \
- "era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \
- "cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
- "nload=tftp 200000 acadia/u-boot-nand.bin\0" \
- "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
- "setenv filesize;saveenv\0" \
- "nupd=run nload nupdate\0" \
"kozio=bootm ffc60000\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
@@ -305,35 +245,10 @@
#define CONFIG_SUPPORT_VFAT
/*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_USB
/*
@@ -344,43 +259,6 @@
#undef CONFIG_CMD_IMLS
#endif
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
@@ -493,21 +371,4 @@
#define CFG_GPIO1_TSRL 0x00000000
#define CFG_GPIO1_TSRH 0x00000000
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
- #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#endif /* __CONFIG_H */
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 3e906c4..fb6feb5 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -33,7 +33,6 @@
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
-#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_4xx_DCACHE /* Enable i- and d-cache */
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
new file mode 100644
index 0000000..1f27d78
--- /dev/null
+++ b/include/configs/amcc-common.h
@@ -0,0 +1,259 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Common configuration options for all AMCC boards
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __AMCC_COMMON_H
+#define __AMCC_COMMON_H
+
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_MONITOR_BASE TEXT_BASE /* Start of U-Boot */
+#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1)
+#define CFG_MALLOC_LEN (1 << 20) /* Reserved for malloc */
+
+/*
+ * UART
+ */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * Ethernet/EMAC/PHY
+ */
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_NET_MULTI
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#if defined(CONFIG_440)
+#define CFG_RX_ETH_BUFFER 32 /* number of eth rx buffers */
+#else
+#define CFG_RX_ETH_BUFFER 16 /* number of eth rx buffers */
+#endif
+
+/*
+ * Commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#if defined(CONFIG_440)
+#define CONFIG_CMD_CACHE
+#endif
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_LOOPW /* enable loopw command */
+#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE /* include version env variable */
+#define CFG_CONSOLE_INFO_QUIET /* don't print console @ startup*/
+
+#define CFG_HUSH_PARSER /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Internal Definitions
+ */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+/*
+ * Booting and default environment
+ */
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+/*
+ * Only very few boards have default console not on ttyS0 (like Taishan)
+ */
+#if !defined(CONFIG_USE_TTY)
+#define CONFIG_USE_TTY ttyS0
+#endif
+
+/*
+ * Only some 4xx PPC's are equipped with an FPU
+ */
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define CONFIG_AMCC_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
+#else
+#define CONFIG_AMCC_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
+#endif
+
+/*
+ * Only some boards need to extend the bootargs by some additional
+ * parameters (like Makalu)
+ */
+#if !defined(CONFIG_ADDMISC)
+#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs}\0"
+#endif
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+/*
+ * General common environment variables shared on all AMCC eval boards
+ */
+#define CONFIG_AMCC_DEF_ENV \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0" \
+ CONFIG_ADDMISC \
+ "initrd_high=30000000\0" \
+ "kernel_addr_r=400000\0" \
+ "fdt_addr_r=800000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ CONFIG_AMCC_DEF_ENV_ROOTPATH
+
+/*
+ * Default environment for arch/powerpc booting
+ * for boards that are ported to arch/powerpc
+ */
+#define CONFIG_AMCC_DEF_ENV_POWERPC \
+ "flash_self=run ramargs addip addtty addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmisc;" \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "tftp ${fdt_addr_r} ${fdt_file}; " \
+ "run nfsargs addip addtty addmisc;" \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"
+
+/*
+ * Default environment for arch/ppc booting,
+ * for boards that are not ported to arch/powerpc yet
+ */
+#define CONFIG_AMCC_DEF_ENV_PPC \
+ "flash_self=run ramargs addip addtty addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
+ "run nfsargs addip addtty addmisc;" \
+ "bootm ${kernel_addr_r}\0"
+
+/*
+ * Default environment for arch/ppc booting (old version),
+ * for boards that are ported to arch/ppc and arch/powerpc
+ */
+#define CONFIG_AMCC_DEF_ENV_PPC_OLD \
+ "flash_self_old=run ramargs addip addtty addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs_old=run nfsargs addip addtty addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
+ "run nfsargs addip addtty addmisc;" \
+ "bootm ${kernel_addr_r}\0"
+
+#define CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ "load=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \
+ "era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \
+ "cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load update\0" \
+
+#define CONFIG_AMCC_DEF_ENV_NAND_UPD \
+ "nload=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot-nand.bin\0" \
+ "nupdate=nand erase 0 100000;nand write 200000 0 100000;" \
+ "setenv filesize;saveenv\0" \
+ "nupd=run nload nupdate\0"
+
+#endif /* __AMCC_COMMON_H */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 2f0df8a..41058f8 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -36,6 +36,12 @@
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME bamboo
+#include "amcc-common.h"
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/*
@@ -49,10 +55,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
@@ -84,14 +86,9 @@
* Serial Port
*----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
/*-----------------------------------------------------------------------
* NVRAM/RTC
*
@@ -223,15 +220,11 @@
#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
#define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
#define CONFIG_PROG_SDRAM_TLB
-#undef CFG_DRAM_TEST
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
@@ -245,54 +238,20 @@
#define CFG_ENV_OFFSET 0x0
#endif /* CFG_ENV_IS_IN_EEPROM */
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=bamboo\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=/tftpboot/bamboo/uImage\0" \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_PPC_OLD \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fff00000\0" \
"ramdisk_addr=fff10000\0" \
- "initrd_high=30000000\0" \
- "load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \
- "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
- "cp.b 100000 fffa0000 60000;" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_HAS_ETH0
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
#define CONFIG_PHY1_ADDR 1
@@ -300,16 +259,6 @@
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#endif /* CONFIG_BAMBOO_NAND */
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_NET_MULTI 1 /* required for netconsole */
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI
@@ -319,77 +268,27 @@
#define USB_2_0_DEVICE
#endif /*CONFIG_440EP*/
-
/*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
#ifdef CONFIG_BAMBOO_NAND
#define CONFIG_CMD_NAND
#endif
-
#define CONFIG_SUPPORT_VFAT
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CONFIG_LYNXKDI 1 /* support kdi files */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
/*-----------------------------------------------------------------------
* PCI stuff
@@ -408,28 +307,4 @@
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#endif /* __CONFIG_H */
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index 75dd4e7..acce82f 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -37,6 +37,12 @@
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME bubinga
+#include "amcc-common.h"
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
@@ -80,118 +86,35 @@
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
#endif
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=bubinga\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=/tftpboot/bubinga/uImage\0" \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_PPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=fff80000\0" \
"ramdisk_addr=fff90000\0" \
- "initrd_high=30000000\0" \
- "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \
- "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
- "cp.b 100000 fffc0000 40000;" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
""
-#define CONFIG_BOOTCOMMAND "run net_nfs"
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
-#define CONFIG_NET_MULTI 1
-#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
/*
- * Command line configuration.
+ * Commands additional to the ones defined in amcc-common.h
*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/*
* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
@@ -205,29 +128,11 @@
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD 691200
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
/*-----------------------------------------------------------------------
* I2C stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
@@ -272,21 +177,9 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
#define CFG_SRAM_BASE 0xFFF00000
#define CFG_FLASH_BASE 0xFFF80000
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
@@ -423,21 +316,4 @@
#define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
#define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#endif /* __CONFIG_H */
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index 3dd577a..ac2e5d9 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -30,12 +30,19 @@
/* This config file is used for Canyonlands (460EX) and Glacier (460GT) */
#ifndef CONFIG_CANYONLANDS
#define CONFIG_460GT 1 /* Specific PPC460GT */
+#define CONFIG_HOSTNAME glacier
#else
#define CONFIG_460EX 1 /* Specific PPC460EX */
+#define CONFIG_HOSTNAME canyonlands
#endif
#define CONFIG_440 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+
#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
@@ -47,8 +54,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-
#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
@@ -86,10 +91,6 @@
#define CFG_AHB_BASE 0xE2000000 /* internal AHB peripherals */
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc()*/
-
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in OCM)
*----------------------------------------------------------------------*/
@@ -102,13 +103,8 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
@@ -242,10 +238,7 @@
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_SPEED 400000 /* I2C speed */
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
@@ -270,7 +263,6 @@
* Ethernet
*----------------------------------------------------------------------*/
#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
#define CONFIG_PHY1_ADDR 1
#define CONFIG_HAS_ETH0
@@ -282,14 +274,11 @@
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#endif
-#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_PHY_DYNAMIC_ANEG 1
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
/*-----------------------------------------------------------------------
* USB-OHCI
*----------------------------------------------------------------------*/
@@ -305,104 +294,30 @@
#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
#endif
-/*-----------------------------------------------------------------------
- * Default environment
- *----------------------------------------------------------------------*/
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-/* Setup some board specific values for the default environment variables */
-#ifdef CONFIG_CANYONLANDS
-#define CONFIG_HOSTNAME canyonlands
-#define CFG_BOOTFILE "bootfile=canyonlands/uImage\0"
-#define CFG_DTBFILE "fdt_file=canyonlands/canyonlands.dtb\0"
-#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
-#else
-#define CONFIG_HOSTNAME glacier
-#define CFG_BOOTFILE "bootfile=glacier/uImage\0"
-#define CFG_DTBFILE "fdt_file=glacier/glacier.dtb\0"
-#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
-#endif
-
+/*
+ * Default environment variables
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
- CFG_BOOTFILE \
- CFG_DTBFILE \
- CFG_ROOTPATH \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr} - ${fdt_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "tftp ${fdt_addr_r} ${fdt_file}; " \
- "run nfsargs addip addtty;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "kernel_addr_r=400000\0" \
- "fdt_addr_r=800000\0" \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
"ramdisk_addr=fc200000\0" \
- "initrd_high=30000000\0" \
- "load=tftp 200000 ${hostname}/u-boot.bin\0" \
- "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
- "cp.b ${fileaddr} fffa0000 ${filesize};" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
- "nload=tftp 200000 ${hostname}/u-boot-nand.bin\0" \
- "nupdate=nand erase 0 100000;nand write 200000 0 100000;" \
- "setenv filesize;saveenv\0" \
- "nupd=run nload nupdate\0" \
"pciconfighost=1\0" \
"pcie_mode=RP:RP\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
/*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
#ifdef CONFIG_460EX
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
@@ -415,41 +330,6 @@
#define CONFIG_ISO_PARTITION
/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#endif
-
-/*-----------------------------------------------------------------------
* PCI stuff
*----------------------------------------------------------------------*/
/* General PCI */
@@ -465,21 +345,6 @@
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
@@ -671,8 +536,4 @@
}
#endif
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#endif /* __CONFIG_H */
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
index ba68fd4..df444d8 100644
--- a/include/configs/ebony.h
+++ b/include/configs/ebony.h
@@ -35,10 +35,15 @@
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME ebony
+#include "amcc-common.h"
+
+/*
* Define here the location of the environment variables (FLASH or NVRAM).
* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
* supported for backward compatibility.
@@ -55,7 +60,6 @@
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
-#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
@@ -74,18 +78,11 @@
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
-
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
-#define CONFIG_BAUDRATE 115200
-
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
/*-----------------------------------------------------------------------
* NVRAM/RTC
@@ -141,10 +138,7 @@
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
@@ -153,125 +147,31 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=ebony\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=/tftpboot/ebony/uImage\0" \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_PPC_OLD \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=ff800000\0" \
"ramdisk_addr=ff810000\0" \
- "initrd_high=30000000\0" \
- "load=tftp 100000 /tftpboot/ebony/u-boot.bin\0" \
- "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
- "cp.b 100000 fffc0000 40000;" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 8 /* PHY address */
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */
-#define CONFIG_NET_MULTI 1
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-
/*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
@@ -288,28 +188,4 @@
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#endif /* __CONFIG_H */
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index cce883f..d3789bd 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -37,8 +37,14 @@
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_440SPE 1 /* Specifc SPe support */
-#undef CFG_DRAM_TEST /* Disable-takes long time */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME katmai
+#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
@@ -48,7 +54,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xff000000 /* start of FLASH */
#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
@@ -78,10 +83,6 @@
#define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1)
-#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
-
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in internal SRAM)
*----------------------------------------------------------------------*/
@@ -98,12 +99,8 @@
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
-#define CONFIG_SERIAL_MULTI 1
#undef CONFIG_UART1_CONSOLE
#undef CFG_EXT_SERIAL_CLOCK
-#define CONFIG_BAUDRATE 115200
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* DDR SDRAM
@@ -117,10 +114,7 @@
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
@@ -172,139 +166,36 @@
*----------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define xstr(s) str(s)
-#define str(s) #s
-
+/*
+ * Default environment variables
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=katmai\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "net_nfs_fdt=tftp 200000 ${bootfile};" \
- "tftp ${fdt_addr} ${fdt_file};" \
- "run nfsargs addip addtty;" \
- "bootm 200000 - ${fdt_addr}\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=katmai/uImage\0" \
- "fdt_file=katmai/katmai.dtb\0" \
- "fdt_addr=400000\0" \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_PPC_OLD \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=fff10000\0" \
"ramdisk_addr=fff20000\0" \
- "initrd_high=30000000\0" \
- "load=tftp 200000 katmai/u-boot.bin\0" \
- "update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \
- "era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \
- "cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
"kozio=bootm ffc60000\0" \
"pciconfighost=1\0" \
"pcie_mode=RP:RP:RP\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
/*
- * Command line configuration.
+ * Commands additional to the ones defined in amcc-common.h
*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_HAS_ETH0
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_RESET_DELAY 1000
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_NET_MULTI /* needed for NetConsole */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
/*-----------------------------------------------------------------------
* FLASH related
@@ -436,28 +327,4 @@
#define CFG_GPIO_TCR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)
#define CFG_GPIO_ODR 0
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#endif /* __CONFIG_H */
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index a596768..9c1a3a4 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -1,4 +1,7 @@
/*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ * Grant Erickson <gerickson@nuovations.com>
+ *
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
@@ -36,6 +39,12 @@
#define CONFIG_405EX 1 /* Specifc 405EX support*/
#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME kilauea
+#include "amcc-common.h"
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_BOARD_EMAC_COUNT
@@ -44,43 +53,70 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFC000000
#define CFG_NAND_ADDR 0xF8000000
#define CFG_FPGA_BASE 0xF0000000
#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
-#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
-#define CFG_MONITOR_BASE (TEXT_BASE)
/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */
-#define CFG_INIT_RAM_END (4 << 10)
+ * Initial RAM & Stack Pointer Configuration Options
+ *
+ * There are traditionally three options for the primordial
+ * (i.e. initial) stack usage on the 405-series:
+ *
+ * 1) On-chip Memory (OCM) (i.e. SRAM)
+ * 2) Data cache
+ * 3) SDRAM
+ *
+ * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
+ * the latter of which is less than desireable since it requires
+ * setting up the SDRAM and ECC in assembly code.
+ *
+ * To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip
+ * select on the External Bus Controller (EBC) and then select a
+ * value for 'CFG_INIT_RAM_ADDR' outside of the range of valid,
+ * physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and
+ * select a value for 'CFG_INIT_RAM_ADDR' within the range of valid,
+ * physical SDRAM to use (3).
+ *-----------------------------------------------------------------------*/
+
+#define CFG_INIT_DCACHE_CS 4
+
+#if defined(CFG_INIT_DCACHE_CS)
+#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
+#else
+#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + (32 << 20)) /* 32 MiB */
+#endif /* defined(CFG_INIT_DCACHE_CS) */
+
+#define CFG_INIT_RAM_END (4 << 10) /* 4 KiB */
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-/* reserve some memory for POST and BOOT limit info */
-#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
-/* extra data in init-ram */
-#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
-#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8)
-#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12)
-#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */
+/*
+ * If the data cache is being used for the primordial stack and global
+ * data area, the POST word must be placed somewhere else. The General
+ * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
+ * its compare and mask register contents across reset, so it is used
+ * for the POST word.
+ */
+
+#if defined(CFG_INIT_DCACHE_CS)
+# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+# define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
+#else
+# define CFG_INIT_EXTRA_SIZE 16
+# define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE)
+# define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
+# define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR
+#endif /* defined(CFG_INIT_DCACHE_CS) */
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
@@ -131,9 +167,9 @@
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
*
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller. sr - 2006-08-25
+ * On 405EX the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from location 0xfffff000...0xffffffff the
+ * NAND controller cannot be accessed since it is attached to CS0 too.
*/
#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
@@ -187,12 +223,54 @@
*----------------------------------------------------------------------*/
#define CFG_MBYTES_SDRAM (256) /* 256MB */
+#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE)
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+#define CFG_SDRAM0_MB0CF ((CFG_SDRAM0_MB0CF_BASE >> 3) | \
+ SDRAM_RXBAS_SDSZ_256MB | \
+ SDRAM_RXBAS_SDAM_MODE7 | \
+ SDRAM_RXBAS_SDBE_ENABLE)
+#define CFG_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MCOPT1 0x04322000
+#define CFG_SDRAM0_MCOPT2 0x00000000
+#define CFG_SDRAM0_MODT0 0x01800000
+#define CFG_SDRAM0_MODT1 0x00000000
+#define CFG_SDRAM0_CODT 0x0080f837
+#define CFG_SDRAM0_RTR 0x06180000
+#define CFG_SDRAM0_INITPLR0 0xa8380000
+#define CFG_SDRAM0_INITPLR1 0x81900400
+#define CFG_SDRAM0_INITPLR2 0x81020000
+#define CFG_SDRAM0_INITPLR3 0x81030000
+#define CFG_SDRAM0_INITPLR4 0x81010404
+#define CFG_SDRAM0_INITPLR5 0x81000542
+#define CFG_SDRAM0_INITPLR6 0x81900400
+#define CFG_SDRAM0_INITPLR7 0x8D080000
+#define CFG_SDRAM0_INITPLR8 0x8D080000
+#define CFG_SDRAM0_INITPLR9 0x8D080000
+#define CFG_SDRAM0_INITPLR10 0x8D080000
+#define CFG_SDRAM0_INITPLR11 0x81000442
+#define CFG_SDRAM0_INITPLR12 0x81010780
+#define CFG_SDRAM0_INITPLR13 0x81010400
+#define CFG_SDRAM0_INITPLR14 0x00000000
+#define CFG_SDRAM0_INITPLR15 0x00000000
+#define CFG_SDRAM0_RQDC 0x80000038
+#define CFG_SDRAM0_RFDC 0x00000209
+#define CFG_SDRAM0_RDCC 0x40000000
+#define CFG_SDRAM0_DLCR 0x030000a5
+#define CFG_SDRAM0_CLKTR 0x80000000
+#define CFG_SDRAM0_WRDTR 0x00000000
+#define CFG_SDRAM0_SDTR1 0x80201000
+#define CFG_SDRAM0_SDTR2 0x32204232
+#define CFG_SDRAM0_SDTR3 0x080b0d1a
+#define CFG_SDRAM0_MMODE 0x00000442
+#define CFG_SDRAM0_MEMODE 0x00000404
+
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
@@ -212,7 +290,6 @@
*----------------------------------------------------------------------*/
#define CONFIG_M88E1111_PHY 1
#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
@@ -220,107 +297,37 @@
#define CONFIG_HAS_ETH0 1
-#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY1_ADDR 2
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_PPC_OLD \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ CONFIG_AMCC_DEF_ENV_NAND_UPD \
"logversion=2\0" \
- "netdev=eth0\0" \
- "hostname=kilauea\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_self_old=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
- "flash_nfs_old=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr} - ${fdt_addr}\0" \
- "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
- "run nfsargs addip addtty;bootm ${kernel_addr_r}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "tftp ${fdt_addr_r} ${fdt_file}; " \
- "run nfsargs addip addtty;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=kilauea/uImage\0" \
- "fdt_file=kilauea/kilauea.dtb\0" \
- "kernel_addr_r=400000\0" \
- "fdt_addr_r=800000\0" \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
"ramdisk_addr=fc200000\0" \
- "initrd_high=30000000\0" \
- "load=tftp 200000 kilauea/u-boot.bin\0" \
- "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
- "cp.b ${fileaddr} fffa0000 ${filesize};" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
- "nload=tftp 200000 kilauea/u-boot-nand.bin\0" \
- "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
- "setenv filesize;saveenv\0" \
- "nupd=run nload nupdate\0" \
"pciconfighost=1\0" \
"pcie_mode=RP:RP\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
/*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_LOG
-#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
/* POST support */
-#define CONFIG_POST (CFG_POST_MEMORY | \
- CFG_POST_CACHE | \
+#define CONFIG_POST (CFG_POST_CACHE | \
CFG_POST_CPU | \
CFG_POST_ETHER | \
CFG_POST_I2C | \
@@ -335,37 +342,6 @@
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
/*-----------------------------------------------------------------------
* PCI stuff
*----------------------------------------------------------------------*/
@@ -394,13 +370,6 @@
/* base address of inbound PCIe window */
#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
@@ -429,7 +398,7 @@
/* Memory Bank 2 (FPGA) initialization */
#define CFG_EBC_PB2AP 0x9400C800
-#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */
+#define CFG_EBC_PB2CR (CFG_FPGA_BASE | 0x18000)
#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */
@@ -474,19 +443,6 @@
} \
}
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
/*-----------------------------------------------------------------------
* Some Kilauea stuff..., mainly fpga registers
*/
@@ -522,8 +478,4 @@
#define CFG_FPGA_USER_LED0 0x00000200
#define CFG_FPGA_USER_LED1 0x00000100
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#endif /* __CONFIG_H */
diff --git a/include/configs/luan.h b/include/configs/luan.h
index 37151d3..805cc59 100644
--- a/include/configs/luan.h
+++ b/include/configs/luan.h
@@ -37,6 +37,12 @@
#define CONFIG_440 1
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME luan
+#include "amcc-common.h"
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
@@ -44,11 +50,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */
-#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
-#define CFG_SDRAM_BASE 0x00000000 /* MUST be zero */
-
#define CFG_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */
#define CFG_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */
#define CFG_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */
@@ -68,7 +69,6 @@
#define CFG_FLASH_BASE CFG_SMALL_FLASH
#endif
-#undef CFG_DRAM_TEST
#if CFG_SRAM_BASE
#define CFG_KBYTES_SDRAM 1024*2
#else
@@ -88,13 +88,8 @@
* Serial Port
*----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */
-#define CONFIG_BAUDRATE 115200
-#undef CONFIG_SERIAL_MULTI
#undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
@@ -139,10 +134,7 @@
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
@@ -151,61 +143,22 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=luan\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):$(netdev):off panic=1\0" \
- "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm $(kernel_addr)\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=/tftpboot/luan/uImage\0" \
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_PPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=fc000000\0" \
"ramdisk_addr=fc100000\0" \
- "initrd_high=30000000\0" \
- "load=tftp 100000 /tftpboot/luan/u-boot.bin\0" \
- "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
- "cp.b 100000 fffc0000 40000;" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_HAS_ETH0
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_NET_MULTI /* needed for NetConsole */
-
#ifdef DEBUG
#define CONFIG_PANIC_HANG
#else
@@ -213,60 +166,11 @@
#endif
/*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#undef CONFIG_LYNXKDI /* support kdi files */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
@@ -287,28 +191,4 @@
#endif
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#endif /* __CONFIG_H */
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index af066f3..65b240e 100644
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -1,4 +1,7 @@
/*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ * Grant Erickson <gerickson@nuovations.com>
+ *
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
@@ -36,6 +39,13 @@
#define CONFIG_405EX 1 /* Specifc 405EX support*/
#define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME makalu
+#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"
+#include "amcc-common.h"
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
@@ -43,42 +53,69 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFC000000
#define CFG_FPGA_BASE 0xF0000000
#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
-#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
-#define CFG_MONITOR_BASE (TEXT_BASE)
/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */
-#define CFG_INIT_RAM_END (4 << 10)
+ * Initial RAM & Stack Pointer Configuration Options
+ *
+ * There are traditionally three options for the primordial
+ * (i.e. initial) stack usage on the 405-series:
+ *
+ * 1) On-chip Memory (OCM) (i.e. SRAM)
+ * 2) Data cache
+ * 3) SDRAM
+ *
+ * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
+ * the latter of which is less than desireable since it requires
+ * setting up the SDRAM and ECC in assembly code.
+ *
+ * To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip
+ * select on the External Bus Controller (EBC) and then select a
+ * value for 'CFG_INIT_RAM_ADDR' outside of the range of valid,
+ * physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and
+ * select a value for 'CFG_INIT_RAM_ADDR' within the range of valid,
+ * physical SDRAM to use (3).
+ *-----------------------------------------------------------------------*/
+
+#define CFG_INIT_DCACHE_CS 4
+
+#if defined(CFG_INIT_DCACHE_CS)
+#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
+#else
+#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + (32 << 20)) /* 32 MiB */
+#endif /* defined(CFG_INIT_DCACHE_CS) */
+
+#define CFG_INIT_RAM_END (4 << 10) /* 4 KiB */
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-/* reserve some memory for POST and BOOT limit info */
-#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
-/* extra data in init-ram */
-#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
-#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8)
-#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12)
-#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */
+/*
+ * If the data cache is being used for the primordial stack and global
+ * data area, the POST word must be placed somewhere else. The General
+ * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
+ * its compare and mask register contents across reset, so it is used
+ * for the POST word.
+ */
+
+#if defined(CFG_INIT_DCACHE_CS)
+# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+# define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
+#else
+# define CFG_INIT_EXTRA_SIZE 16
+# define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE)
+# define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
+# define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR
+#endif /* defined(CFG_INIT_DCACHE_CS) */
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK /* no ext. clk */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
@@ -113,14 +150,60 @@
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM 256
+#define CFG_MBYTES_SDRAM (256) /* 256MB */
+
+#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE)
+#define CFG_SDRAM0_MB1CF_BASE ((128 << 20) + CFG_SDRAM_BASE)
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+#define CFG_SDRAM0_MB0CF ((CFG_SDRAM0_MB0CF_BASE >> 3) | \
+ SDRAM_RXBAS_SDSZ_128MB | \
+ SDRAM_RXBAS_SDAM_MODE2 | \
+ SDRAM_RXBAS_SDBE_ENABLE)
+#define CFG_SDRAM0_MB1CF ((CFG_SDRAM0_MB1CF_BASE >> 3) | \
+ SDRAM_RXBAS_SDSZ_128MB | \
+ SDRAM_RXBAS_SDAM_MODE2 | \
+ SDRAM_RXBAS_SDBE_ENABLE)
+#define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MCOPT1 0x04322000
+#define CFG_SDRAM0_MCOPT2 0x00000000
+#define CFG_SDRAM0_MODT0 0x01800000
+#define CFG_SDRAM0_MODT1 0x00000000
+#define CFG_SDRAM0_CODT 0x0080f837
+#define CFG_SDRAM0_RTR 0x06180000
+#define CFG_SDRAM0_INITPLR0 0xa8380000
+#define CFG_SDRAM0_INITPLR1 0x81900400
+#define CFG_SDRAM0_INITPLR2 0x81020000
+#define CFG_SDRAM0_INITPLR3 0x81030000
+#define CFG_SDRAM0_INITPLR4 0x81010404
+#define CFG_SDRAM0_INITPLR5 0x81000542
+#define CFG_SDRAM0_INITPLR6 0x81900400
+#define CFG_SDRAM0_INITPLR7 0x8D080000
+#define CFG_SDRAM0_INITPLR8 0x8D080000
+#define CFG_SDRAM0_INITPLR9 0x8D080000
+#define CFG_SDRAM0_INITPLR10 0x8D080000
+#define CFG_SDRAM0_INITPLR11 0x81000442
+#define CFG_SDRAM0_INITPLR12 0x81010780
+#define CFG_SDRAM0_INITPLR13 0x81010400
+#define CFG_SDRAM0_INITPLR14 0x00000000
+#define CFG_SDRAM0_INITPLR15 0x00000000
+#define CFG_SDRAM0_RQDC 0x80000038
+#define CFG_SDRAM0_RFDC 0x00000209
+#define CFG_SDRAM0_RDCC 0x40000000
+#define CFG_SDRAM0_DLCR 0x030000a5
+#define CFG_SDRAM0_CLKTR 0x80000000
+#define CFG_SDRAM0_WRDTR 0x00000000
+#define CFG_SDRAM0_SDTR1 0x80201000
+#define CFG_SDRAM0_SDTR2 0x32204232
+#define CFG_SDRAM0_SDTR3 0x080b0d1a
+#define CFG_SDRAM0_MMODE 0x00000442
+#define CFG_SDRAM0_MEMODE 0x00000404
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
@@ -140,7 +223,6 @@
*----------------------------------------------------------------------*/
#define CONFIG_M88E1111_PHY 1
#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
@@ -148,104 +230,35 @@
#define CONFIG_HAS_ETH0 1
-#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY1_ADDR 0
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "logversion=2\0" \
- "netdev=eth0\0" \
- "hostname=makalu\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0" \
- "flash_self_old=run ramargs addip addtty addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_self=run ramargs addip addtty addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
- "flash_nfs_old=run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr} - ${fdt_addr}\0" \
- "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
- "run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr_r}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "tftp ${fdt_addr_r} ${fdt_file}; " \
- "run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=makalu/uImage\0" \
- "fdt_file=makalu/makalu.dtb\0" \
- "kernel_addr_r=400000\0" \
- "fdt_addr_r=800000\0" \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_PPC_OLD \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
"ramdisk_addr=fc200000\0" \
- "initrd_high=30000000\0" \
- "load=tftp 200000 makalu/u-boot.bin\0" \
- "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
- "cp.b ${fileaddr} fffa0000 ${filesize};" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
"pciconfighost=1\0" \
"pcie_mode=RP:RP\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
/*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
#define CONFIG_CMD_DTT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_LOG
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
/* POST support */
-#define CONFIG_POST (CFG_POST_MEMORY | \
- CFG_POST_CACHE | \
+#define CONFIG_POST (CFG_POST_CACHE | \
CFG_POST_CPU | \
CFG_POST_ETHER | \
CFG_POST_I2C | \
@@ -260,37 +273,6 @@
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
/*-----------------------------------------------------------------------
* PCI stuff
*----------------------------------------------------------------------*/
@@ -319,13 +301,6 @@
/* base address of inbound PCIe window */
#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
@@ -384,21 +359,4 @@
#define CFG_GPIO_PCIE_CLKREQ 27
#define CFG_GPIO_PCIE_WAKE 28
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#endif /* __CONFIG_H */
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
index be2b3ec..407aae7 100644
--- a/include/configs/ocotea.h
+++ b/include/configs/ocotea.h
@@ -44,16 +44,19 @@
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME ocotea
+#include "amcc-common.h"
+
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
-#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
@@ -75,18 +78,11 @@
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
-
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
-#define CONFIG_BAUDRATE 115200
-
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Environment
@@ -156,10 +152,7 @@
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
@@ -168,54 +161,17 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=ocotea\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=/tftpboot/ocotea/uImage\0" \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_PPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=fff00000\0" \
"ramdisk_addr=fff10000\0" \
- "initrd_high=30000000\0" \
- "load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \
- "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
- "cp.b 100000 fffc0000 40000;" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_PHY1_ADDR 2
#define CONFIG_PHY2_ADDR 0x10
@@ -228,73 +184,15 @@
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_RESET_DELAY 1000
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-
/*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
@@ -311,28 +209,4 @@
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#endif /* __CONFIG_H */
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index 81a1e07..146eafe 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -42,6 +42,7 @@
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
+#define CONFIG_MPC8560 1
/* XXX flagging this as something I might want to delete */
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
index d140241..4ae25ad 100644
--- a/include/configs/scb9328.h
+++ b/include/configs/scb9328.h
@@ -257,13 +257,9 @@
#define CFG_CS5L_VAL 0x00000D03
#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0x16000000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE+4)
-/* #define CONFIG_DM9000_USE_8BIT */
-#define CONFIG_DM9000_USE_16BIT
-/* #define CONFIG_DM9000_USE_32BIT */
/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
f_ref=16,777MHz
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 48251f3..f4eefae 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -34,11 +34,19 @@
/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
#ifndef CONFIG_RAINIER
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_HOSTNAME sequoia
#else
#define CONFIG_440GRX 1 /* Specific PPC440GRx */
+#define CONFIG_HOSTNAME rainier
#endif
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+
/* Detect Sequoia PLL input clock automatically via CPLD bit */
#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
33333333 : 33000000)
@@ -64,19 +72,9 @@
* Base addresses -- Note these are effective addresses where the actual
* resources get mapped (not physical addresses).
*/
-#ifndef CONFIG_VIDEO
-#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
-#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
-#else
-#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
-#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
-#endif
-
#define CFG_TLB_FOR_BOOT_FLASH 0x0003
#define CFG_BOOT_BASE_ADDR 0xf0000000
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
-#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
#define CFG_OCM_BASE 0xe0010000 /* ocm */
#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
@@ -108,14 +106,9 @@
* Serial Port
*/
#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
/*
* Environment
*/
@@ -227,10 +220,7 @@
/*
* I2C
*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
@@ -247,80 +237,27 @@
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-/* Setup some board specific values for the default environment variables */
-#ifndef CONFIG_RAINIER
-#define CONFIG_HOSTNAME sequoia
-#define CFG_BOOTFILE "bootfile=sequoia/uImage\0"
-#define CFG_DTBFILE "fdt_file=sequoia/sequoia.dtb\0"
-#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
-#else
-#define CONFIG_HOSTNAME rainier
-#define CFG_BOOTFILE "bootfile=rainier/uImage\0"
-#define CFG_DTBFILE "fdt_file=rainier/rainier.dtb\0"
-#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
-#endif
-
+/*
+ * Default environment variables
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
- CFG_BOOTFILE \
- CFG_ROOTPATH \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "addmisc=setenv bootargs ${bootargs}\0" \
- "flash_nfs=run nfsargs addip addtty addmisc;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};" \
- "run nfsargs addip addtty addmisc;" \
- "bootm\0" \
- "fdt_file=sequoia/sequoia.dtb\0" \
- "fdt_addr=400000\0" \
- "net_nfs_fdt=tftp 200000 ${bootfile};" \
- "tftp ${fdt_addr} ${fdt_file};" \
- "run nfsargs addip addtty addmisc;" \
- "bootm 200000 - ${fdt_addr}\0" \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_PPC_OLD \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=FC000000\0" \
"ramdisk_addr=FC180000\0" \
- "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
- "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
- "cp.b 200000 FFFA0000 60000\0" \
- "upd=run load update\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_M88E1111_PHY 1
#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */
- /* buffers & descriptors */
-#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY1_ADDR 1
@@ -347,35 +284,12 @@
#define CONFIG_ISO_PARTITION
/*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#ifdef CONFIG_440EPX
@@ -407,35 +321,6 @@
#define CONFIG_SUPPORT_VFAT
/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
- /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-/*
* PCI stuff
*/
/* General PCI */
@@ -453,13 +338,6 @@
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
- * For booting Linux, the board info and command line data have to be in the
- * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
- * during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
* External Bus Controller (EBC) Setup
*/
@@ -577,23 +455,6 @@
} \
}
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#ifdef CONFIG_VIDEO
#define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */
#define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 6dc9eff..1627413 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -165,7 +165,7 @@
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
/* Serial Port */
@@ -216,11 +216,6 @@
#define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */
#define CFG_EEPROM_PAGE_WRITE_BITS 4
-/* RapidIO MMU */
-#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
-#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
-#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
-
/*
* General PCI
* Memory space is mapped 1-1.
@@ -238,13 +233,7 @@
#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#define CONFIG_EEPRO100
-#undef CONFIG_TULIP
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
@@ -390,10 +379,10 @@
"tftp ${fdt_addr_r} ${fdt_file}; " \
"run nfsargs addip addcons;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "fdt_file=$hostname/socrates.dtb\0" \
+ "fdt_file=$hostname/socrates.dtb\0" \
"fdt_addr_r=B00000\0" \
"fdt_addr=FC1E0000\0" \
- "rootpath=/opt/eldk/ppc_85xx\0" \
+ "rootpath=/opt/eldk/ppc_85xxDP\0" \
"kernel_addr=FC000000\0" \
"kernel_addr_r=200000\0" \
"ramdisk_addr=FC200000\0" \
@@ -420,4 +409,14 @@
#define CONFIG_DOS_PARTITION 1
#define CONFIG_USB_STORAGE 1
+/* FPGA and NAND */
+#define CFG_FPGA_BASE 0xc0000000
+#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
+#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */
+
+#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70)
+#define CFG_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_CMD_NAND
+
#endif /* __CONFIG_H */
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index ec04a30..6e8213d 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -41,6 +41,7 @@
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
+#define CONFIG_MPC8560 1
#undef CONFIG_PCI /* pci ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index d033c86..a1e9789 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -41,6 +41,7 @@
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
+#define CONFIG_MPC8560 1
#define CONFIG_PCI /* PCI ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
diff --git a/include/configs/taihu.h b/include/configs/taihu.h
index c060b1e..86f776d 100644
--- a/include/configs/taihu.h
+++ b/include/configs/taihu.h
@@ -32,6 +32,12 @@
#define CONFIG_4xx 1 /* member of PPC4xx family */
#define CONFIG_TAIHU 1 /* on a taihu board */
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME taihu
+#include "amcc-common.h"
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
@@ -70,87 +76,31 @@
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootfile=/tftpboot/taihu/uImage\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "netdev=eth0\0" \
- "hostname=taihu\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_PPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=FC000000\0" \
"ramdisk_addr=FC180000\0" \
- "load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \
- "update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \
- "cp.b 200000 FFFC0000 40000\0" \
- "upd=run load update\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0x14 /* PHY address */
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
-#define CONFIG_NET_MULTI 1
-#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_PHY_RESET 1
/*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SPI
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
#define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
#define CFG_SDRAM_BANKS 2
@@ -169,23 +119,6 @@
#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/*
* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
@@ -198,35 +131,13 @@
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD 691200
-
-#define CONFIG_BAUDRATE 115200
-
#define CONFIG_UART1_CONSOLE 1
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
/*-----------------------------------------------------------------------
* I2C stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
@@ -278,25 +189,12 @@ unsigned char spi_read(void);
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFFE00000
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
@@ -421,21 +319,5 @@ unsigned char spi_read(void);
#define CPLD_REG0_ADDR 0x50100000
#define CPLD_REG1_ADDR 0x50100001
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
#endif /* __CONFIG_H */
diff --git a/include/configs/taishan.h b/include/configs/taishan.h
index 1879d38..ba42192 100644
--- a/include/configs/taishan.h
+++ b/include/configs/taishan.h
@@ -32,9 +32,15 @@
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
-#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME taishan
+#define CONFIG_USE_TTY ttyS1
+#include "amcc-common.h"
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
@@ -42,9 +48,7 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
-#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
@@ -70,19 +74,11 @@
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
-#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc*/
-
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_UART1_CONSOLE 1 /* use of UART1 as console */
-#define CONFIG_SERIAL_MULTI 1 /* enable serial multi support */
#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
-#define CONFIG_BAUDRATE 115200
-
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Environment
@@ -138,10 +134,7 @@
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#undef CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR 0x50
@@ -159,65 +152,23 @@
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=taishan\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=/tftpboot/taishan/uImage\0" \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_PPC_OLD \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=fc000000\0" \
"ramdisk_addr=fc180000\0" \
- "initrd_high=30000000\0" \
- "load=tftp 100000 /tftpboot/taishan/u-boot.bin\0" \
- "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
- "cp.b 100000 fffc0000 40000;" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
- "fixedip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
- "$(gatewayip):$(netmask):$(hostname):$(netdev):off panic=1\0" \
- "dhcp=setenv bootargs $(bootargs) ip=dhcp\0" \
"kozio=bootm 0xffe00000\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*-----------------------------------------------------------------------
* Networking
*----------------------------------------------------------------------*/
#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY2_ADDR 0x1
@@ -230,70 +181,12 @@
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_RESET_DELAY 1000
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
/*
- * Command line configuration.
+ * Commands additional to the ones defined in amcc-common.h
*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
#define CONFIG_CMD_DTT
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* PCI stuff
@@ -312,28 +205,4 @@
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#endif /* __CONFIG_H */
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index 25155ad..f77dd14 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -276,13 +276,9 @@
#define CFG_MCIO1_VAL 0x0000c108
#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0x08000000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
-/* #define CONFIG_DM9000_USE_8BIT */
-/* #define CONFIG_DM9000_USE_16BIT */
-#define CONFIG_DM9000_USE_32BIT
#define CONFIG_USB_OHCI_NEW 1
#define CFG_USB_OHCI_BOARD_INIT 1
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
index adc420b..e19c5f3 100644
--- a/include/configs/walnut.h
+++ b/include/configs/walnut.h
@@ -38,122 +38,44 @@
#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
/* ...and on a SYCAMORE board */
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME walnut
+#include "amcc-common.h"
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=walnut\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=/tftpboot/walnut/uImage\0" \
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_PPC_OLD \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=fff80000\0" \
"ramdisk_addr=fff80000\0" \
- "initrd_high=30000000\0" \
- "load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \
- "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
- "cp.b 100000 fffc0000 40000;" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
""
-#define CONFIG_BOOTCOMMAND "run net_nfs"
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
-
-#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
#define CONFIG_HAS_ETH0 1
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_NET_MULTI /* needed for NetConsole */
-
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
/*
- * Command line configuration.
+ * Commands additional to the ones defined in amcc-common.h
*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/*
* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
@@ -167,29 +89,11 @@
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD 691200
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
/*-----------------------------------------------------------------------
* I2C stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
@@ -224,13 +128,8 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFFF80000
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
/*
* Define here the location of the environment variables (FLASH or NVRAM).
@@ -243,13 +142,6 @@
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
#endif
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
/*-----------------------------------------------------------------------
* FLASH organization
*/
@@ -335,21 +227,4 @@
*/
#define SPD_EEPROM_ADDRESS 0x50
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#endif /* __CONFIG_H */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index f22e798..891b515 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -42,6 +42,11 @@
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_BOARD_RESET 1 /* call board_reset() */
@@ -50,10 +55,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
-#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
@@ -84,14 +85,9 @@
* Serial Port
*----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
/*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
@@ -142,10 +138,7 @@
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
@@ -167,72 +160,22 @@
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-/* Setup some board specific values for the default environment variables */
-#ifndef CONFIG_YELLOWSTONE
-#define CONFIG_HOSTNAME yosemite
-#define CFG_BOOTFILE "bootfile=/tftpboot/yosemite/uImage\0"
-#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
-#else
-#define CONFIG_HOSTNAME yellowstone
-#define CFG_BOOTFILE "bootfile=/tftpboot/yellowstone/uImage\0"
-#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
-#endif
-
+/*
+ * Default environment variables
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
- CFG_BOOTFILE \
- CFG_ROOTPATH \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "bootfile=/tftpboot/${hostname}/uImage\0" \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_PPC_OLD \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=fc000000\0" \
"ramdisk_addr=fc180000\0" \
- "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
- "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
- "cp.b 200000 fff80000 80000;" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_NET_MULTI 1 /* required for netconsole */
-#define CONFIG_PHY1_ADDR 3
#define CONFIG_HAS_ETH0 1 /* add support for "ethaddr" */
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
-
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_PHY1_ADDR 3
/* Partitions */
#define CONFIG_MAC_PARTITION
@@ -263,36 +206,11 @@
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
-
/*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
#define CONFIG_CMD_DTT
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
#ifdef CONFIG_440EP
#define CONFIG_CMD_USB
@@ -300,36 +218,6 @@
#define CONFIG_CMD_EXT2
#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CONFIG_LYNXKDI 1 /* support kdi files */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
@@ -347,13 +235,6 @@
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
@@ -370,21 +251,4 @@
#define CFG_BCSR5_PCI66EN 0x80
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#endif /* __CONFIG_H */
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 6f9d3e3..026fef6 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -38,13 +38,18 @@
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_440SPE 1 /* Specifc SPe support */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#undef CFG_DRAM_TEST /* Disable-takes long time */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define EXTCLK_33_33 33333333
#define EXTCLK_66_66 66666666
#define EXTCLK_50 50000000
#define EXTCLK_83 83333333
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME yucca
+#include "amcc-common.h"
+
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#undef CONFIG_SHOW_BOOT_PROGRESS
#undef CONFIG_STRESS
@@ -53,9 +58,7 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
-#define CFG_MONITOR_BASE 0xfffb0000 /* start of monitor */
#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
@@ -99,24 +102,15 @@
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
-#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */
-#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
-
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
-#define CONFIG_SERIAL_MULTI 1
#undef CONFIG_UART1_CONSOLE
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CFG_EXT_SERIAL_CLOCK
/* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
-#define CONFIG_BAUDRATE 115200
-
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
@@ -127,10 +121,7 @@
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
#define IIC0_BOOTPROM_ADDR 0x50
#define IIC0_ALT_BOOTPROM_ADDR 0x54
@@ -153,123 +144,32 @@
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=yucca\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=yucca/uImage\0" \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_PPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=E7F10000\0" \
"ramdisk_addr=E7F20000\0" \
- "initrd_high=30000000\0" \
- "load=tftp 100000 yuca/u-boot.bin\0" \
- "update=protect off 2:4-7;era 2:4-7;" \
- "cp.b ${fileaddr} FFFB0000 ${filesize};" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
"pciconfighost=1\0" \
"pcie_mode=RP:EP:EP\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
/*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
-
#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_MII 1 /* MII PHY management */
-#undef CONFIG_NET_MULTI
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_HAS_ETH0
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_RESET_DELAY 1000
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_NET_MULTI /* needed for NetConsole */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* FLASH related
@@ -318,26 +218,6 @@
/* Support for Intel 82557/82559/82559ER chips. */
#define CONFIG_EEPRO100
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
/* FB Divisor selection */
#define FPGA_FB_DIV_6 6
#define FPGA_FB_DIV_10 10
@@ -539,10 +419,4 @@
#define PERIOD_33_33MHZ 30000 /* 30ns */
#define PERIOD_25_00MHZ 40000 /* 40ns */
-/*---------------------------------------------------------------------------*/
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#endif /* __CONFIG_H */
diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h
index 634ff02..49fd8a6 100644
--- a/include/linux/mtd/fsl_upm.h
+++ b/include/linux/mtd/fsl_upm.h
@@ -16,7 +16,6 @@
#include <linux/mtd/nand.h>
struct fsl_upm {
- const u32 *array;
void __iomem *mdr;
void __iomem *mxmr;
void __iomem *mar;
diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h
index 72d7341..4cebea9 100644
--- a/include/linux/mtd/mtd-abi.h
+++ b/include/linux/mtd/mtd-abi.h
@@ -93,7 +93,7 @@ struct nand_oobinfo {
uint32_t useecc;
uint32_t eccbytes;
uint32_t oobfree[8][2];
- uint32_t eccpos[32];
+ uint32_t eccpos[48];
};
#endif /* __MTD_ABI_H__ */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index d2e1e2b..939b825 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -14,6 +14,7 @@
#define __MPC83XX_H__
#include <config.h>
+#include <asm/fsl_lbc.h>
#if defined(CONFIG_E300)
#include <asm/e300.h>
#endif
@@ -820,6 +821,7 @@
#define CSCONFIG_EN 0x80000000
#define CSCONFIG_AP 0x00800000
#define CSCONFIG_ODT_WR_ACS 0x00010000
+#define CSCONFIG_BANK_BIT_3 0x00004000
#define CSCONFIG_ROW_BIT 0x00000700
#define CSCONFIG_ROW_BIT_12 0x00000000
#define CSCONFIG_ROW_BIT_13 0x00000100
@@ -1019,239 +1021,6 @@
#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */
#define ECC_ERROR_MAN_SBEC_SHIFT 0
-/* BR - Base Registers
- */
-#define BR0 0x5000 /* Register offset to immr */
-#define BR1 0x5008
-#define BR2 0x5010
-#define BR3 0x5018
-#define BR4 0x5020
-#define BR5 0x5028
-#define BR6 0x5030
-#define BR7 0x5038
-
-#define BR_BA 0xFFFF8000
-#define BR_BA_SHIFT 15
-#define BR_PS 0x00001800
-#define BR_PS_SHIFT 11
-#define BR_PS_8 0x00000800 /* Port Size 8 bit */
-#define BR_PS_16 0x00001000 /* Port Size 16 bit */
-#define BR_PS_32 0x00001800 /* Port Size 32 bit */
-#define BR_DECC 0x00000600
-#define BR_DECC_SHIFT 9
-#define BR_DECC_OFF 0x00000000
-#define BR_DECC_CHK 0x00000200
-#define BR_DECC_CHK_GEN 0x00000400
-#define BR_WP 0x00000100
-#define BR_WP_SHIFT 8
-#define BR_MSEL 0x000000E0
-#define BR_MSEL_SHIFT 5
-#define BR_MS_GPCM 0x00000000 /* GPCM */
-#define BR_MS_FCM 0x00000020 /* FCM */
-#define BR_MS_SDRAM 0x00000060 /* SDRAM */
-#define BR_MS_UPMA 0x00000080 /* UPMA */
-#define BR_MS_UPMB 0x000000A0 /* UPMB */
-#define BR_MS_UPMC 0x000000C0 /* UPMC */
-#if !defined(CONFIG_MPC834X)
-#define BR_ATOM 0x0000000C
-#define BR_ATOM_SHIFT 2
-#endif
-#define BR_V 0x00000001
-#define BR_V_SHIFT 0
-
-#if defined(CONFIG_MPC834X)
-#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
-#else
-#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
-#endif
-
-/* OR - Option Registers
- */
-#define OR0 0x5004 /* Register offset to immr */
-#define OR1 0x500C
-#define OR2 0x5014
-#define OR3 0x501C
-#define OR4 0x5024
-#define OR5 0x502C
-#define OR6 0x5034
-#define OR7 0x503C
-
-#define OR_GPCM_AM 0xFFFF8000
-#define OR_GPCM_AM_SHIFT 15
-#define OR_GPCM_BCTLD 0x00001000
-#define OR_GPCM_BCTLD_SHIFT 12
-#define OR_GPCM_CSNT 0x00000800
-#define OR_GPCM_CSNT_SHIFT 11
-#define OR_GPCM_ACS 0x00000600
-#define OR_GPCM_ACS_SHIFT 9
-#define OR_GPCM_ACS_0b10 0x00000400
-#define OR_GPCM_ACS_0b11 0x00000600
-#define OR_GPCM_XACS 0x00000100
-#define OR_GPCM_XACS_SHIFT 8
-#define OR_GPCM_SCY 0x000000F0
-#define OR_GPCM_SCY_SHIFT 4
-#define OR_GPCM_SCY_1 0x00000010
-#define OR_GPCM_SCY_2 0x00000020
-#define OR_GPCM_SCY_3 0x00000030
-#define OR_GPCM_SCY_4 0x00000040
-#define OR_GPCM_SCY_5 0x00000050
-#define OR_GPCM_SCY_6 0x00000060
-#define OR_GPCM_SCY_7 0x00000070
-#define OR_GPCM_SCY_8 0x00000080
-#define OR_GPCM_SCY_9 0x00000090
-#define OR_GPCM_SCY_10 0x000000a0
-#define OR_GPCM_SCY_11 0x000000b0
-#define OR_GPCM_SCY_12 0x000000c0
-#define OR_GPCM_SCY_13 0x000000d0
-#define OR_GPCM_SCY_14 0x000000e0
-#define OR_GPCM_SCY_15 0x000000f0
-#define OR_GPCM_SETA 0x00000008
-#define OR_GPCM_SETA_SHIFT 3
-#define OR_GPCM_TRLX 0x00000004
-#define OR_GPCM_TRLX_SHIFT 2
-#define OR_GPCM_EHTR 0x00000002
-#define OR_GPCM_EHTR_SHIFT 1
-#define OR_GPCM_EAD 0x00000001
-#define OR_GPCM_EAD_SHIFT 0
-
-#define OR_FCM_AM 0xFFFF8000
-#define OR_FCM_AM_SHIFT 15
-#define OR_FCM_BCTLD 0x00001000
-#define OR_FCM_BCTLD_SHIFT 12
-#define OR_FCM_PGS 0x00000400
-#define OR_FCM_PGS_SHIFT 10
-#define OR_FCM_CSCT 0x00000200
-#define OR_FCM_CSCT_SHIFT 9
-#define OR_FCM_CST 0x00000100
-#define OR_FCM_CST_SHIFT 8
-#define OR_FCM_CHT 0x00000080
-#define OR_FCM_CHT_SHIFT 7
-#define OR_FCM_SCY 0x00000070
-#define OR_FCM_SCY_SHIFT 4
-#define OR_FCM_SCY_1 0x00000010
-#define OR_FCM_SCY_2 0x00000020
-#define OR_FCM_SCY_3 0x00000030
-#define OR_FCM_SCY_4 0x00000040
-#define OR_FCM_SCY_5 0x00000050
-#define OR_FCM_SCY_6 0x00000060
-#define OR_FCM_SCY_7 0x00000070
-#define OR_FCM_RST 0x00000008
-#define OR_FCM_RST_SHIFT 3
-#define OR_FCM_TRLX 0x00000004
-#define OR_FCM_TRLX_SHIFT 2
-#define OR_FCM_EHTR 0x00000002
-#define OR_FCM_EHTR_SHIFT 1
-
-#define OR_UPM_AM 0xFFFF8000
-#define OR_UPM_AM_SHIFT 15
-#define OR_UPM_XAM 0x00006000
-#define OR_UPM_XAM_SHIFT 13
-#define OR_UPM_BCTLD 0x00001000
-#define OR_UPM_BCTLD_SHIFT 12
-#define OR_UPM_BI 0x00000100
-#define OR_UPM_BI_SHIFT 8
-#define OR_UPM_TRLX 0x00000004
-#define OR_UPM_TRLX_SHIFT 2
-#define OR_UPM_EHTR 0x00000002
-#define OR_UPM_EHTR_SHIFT 1
-#define OR_UPM_EAD 0x00000001
-#define OR_UPM_EAD_SHIFT 0
-
-#define OR_SDRAM_AM 0xFFFF8000
-#define OR_SDRAM_AM_SHIFT 15
-#define OR_SDRAM_XAM 0x00006000
-#define OR_SDRAM_XAM_SHIFT 13
-#define OR_SDRAM_COLS 0x00001C00
-#define OR_SDRAM_COLS_SHIFT 10
-#define OR_SDRAM_ROWS 0x000001C0
-#define OR_SDRAM_ROWS_SHIFT 6
-#define OR_SDRAM_PMSEL 0x00000020
-#define OR_SDRAM_PMSEL_SHIFT 5
-#define OR_SDRAM_EAD 0x00000001
-#define OR_SDRAM_EAD_SHIFT 0
-
-#define OR_AM_32KB 0xFFFF8000
-#define OR_AM_64KB 0xFFFF0000
-#define OR_AM_128KB 0xFFFE0000
-#define OR_AM_256KB 0xFFFC0000
-#define OR_AM_512KB 0xFFF80000
-#define OR_AM_1MB 0xFFF00000
-#define OR_AM_2MB 0xFFE00000
-#define OR_AM_4MB 0xFFC00000
-#define OR_AM_8MB 0xFF800000
-#define OR_AM_16MB 0xFF000000
-#define OR_AM_32MB 0xFE000000
-#define OR_AM_64MB 0xFC000000
-#define OR_AM_128MB 0xF8000000
-#define OR_AM_256MB 0xF0000000
-#define OR_AM_512MB 0xE0000000
-#define OR_AM_1GB 0xC0000000
-#define OR_AM_2GB 0x80000000
-#define OR_AM_4GB 0x00000000
-
-#define LBLAWAR_EN 0x80000000
-#define LBLAWAR_4KB 0x0000000B
-#define LBLAWAR_8KB 0x0000000C
-#define LBLAWAR_16KB 0x0000000D
-#define LBLAWAR_32KB 0x0000000E
-#define LBLAWAR_64KB 0x0000000F
-#define LBLAWAR_128KB 0x00000010
-#define LBLAWAR_256KB 0x00000011
-#define LBLAWAR_512KB 0x00000012
-#define LBLAWAR_1MB 0x00000013
-#define LBLAWAR_2MB 0x00000014
-#define LBLAWAR_4MB 0x00000015
-#define LBLAWAR_8MB 0x00000016
-#define LBLAWAR_16MB 0x00000017
-#define LBLAWAR_32MB 0x00000018
-#define LBLAWAR_64MB 0x00000019
-#define LBLAWAR_128MB 0x0000001A
-#define LBLAWAR_256MB 0x0000001B
-#define LBLAWAR_512MB 0x0000001C
-#define LBLAWAR_1GB 0x0000001D
-#define LBLAWAR_2GB 0x0000001E
-
-/* LBCR - Local Bus Configuration Register
- */
-#define LBCR_LDIS 0x80000000
-#define LBCR_LDIS_SHIFT 31
-#define LBCR_BCTLC 0x00C00000
-#define LBCR_BCTLC_SHIFT 22
-#define LBCR_LPBSE 0x00020000
-#define LBCR_LPBSE_SHIFT 17
-#define LBCR_EPAR 0x00010000
-#define LBCR_EPAR_SHIFT 16
-#define LBCR_BMT 0x0000FF00
-#define LBCR_BMT_SHIFT 8
-
-/* LCRR - Clock Ratio Register
- */
-#define LCRR_DBYP 0x80000000
-#define LCRR_DBYP_SHIFT 31
-#define LCRR_BUFCMDC 0x30000000
-#define LCRR_BUFCMDC_SHIFT 28
-#define LCRR_BUFCMDC_1 0x10000000
-#define LCRR_BUFCMDC_2 0x20000000
-#define LCRR_BUFCMDC_3 0x30000000
-#define LCRR_BUFCMDC_4 0x00000000
-#define LCRR_ECL 0x03000000
-#define LCRR_ECL_SHIFT 24
-#define LCRR_ECL_4 0x00000000
-#define LCRR_ECL_5 0x01000000
-#define LCRR_ECL_6 0x02000000
-#define LCRR_ECL_7 0x03000000
-#define LCRR_EADC 0x00030000
-#define LCRR_EADC_SHIFT 16
-#define LCRR_EADC_1 0x00010000
-#define LCRR_EADC_2 0x00020000
-#define LCRR_EADC_3 0x00030000
-#define LCRR_EADC_4 0x00000000
-#define LCRR_CLKDIV 0x0000000F
-#define LCRR_CLKDIV_SHIFT 0
-#define LCRR_CLKDIV_2 0x00000002
-#define LCRR_CLKDIV_4 0x00000004
-#define LCRR_CLKDIV_8 0x00000008
-
/* DMAMR - DMA Mode Register
*/
#define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */
diff --git a/include/mpc85xx.h b/include/mpc85xx.h
index 321b24f..a4d4d65 100644
--- a/include/mpc85xx.h
+++ b/include/mpc85xx.h
@@ -6,6 +6,8 @@
#ifndef __MPC85xx_H__
#define __MPC85xx_H__
+#include <asm/fsl_lbc.h>
+
/* define for common ppc_asm.tmpl */
#define EXC_OFF_SYS_RESET 0x100 /* System reset */
#define _START_OFFSET 0
@@ -26,39 +28,4 @@
#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
-/*
- * Local Bus Controller - memory controller registers
- */
-#define BRx_V 0x00000001 /* Bank Valid */
-#define BRx_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
-#define BRx_MS_SDRAM 0x00000000 /* SDRAM Machine Select */
-#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
-#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */
-#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */
-#define BRx_PS_8 0x00000800 /* 8 bit port size */
-#define BRx_PS_32 0x00001800 /* 32 bit port size */
-#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */
-
-#define ORxG_EAD 0x00000001 /* External addr latch delay */
-#define ORxG_EHTR 0x00000002 /* Extended hold time on read */
-#define ORxG_TRLX 0x00000004 /* Timing relaxed */
-#define ORxG_SETA 0x00000008 /* External address termination */
-#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
-#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
-#define ORxG_XACS 0x00000100 /* Extra addr to CS setup */
-#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/
-#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */
-
-#define ORxU_BI 0x00000100 /* Burst Inhibit */
-#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */
-
-#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
-#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
-#define MxMR_OP_WARR 0x10000000 /* Write to Array */
-#define MxMR_BSEL 0x80000000 /* Bus Select */
-
-/* helpers to convert values into an OR address mask (GPCM mode) */
-#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
-#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
-
#endif /* __MPC85xx_H__ */
diff --git a/include/mpc86xx.h b/include/mpc86xx.h
index 9fd349a..ce3d784 100644
--- a/include/mpc86xx.h
+++ b/include/mpc86xx.h
@@ -7,6 +7,8 @@
#ifndef __MPC86xx_H__
#define __MPC86xx_H__
+#include <asm/fsl_lbc.h>
+
#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
#define _START_OFFSET EXC_OFF_SYS_RESET
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 61c2203..d061017 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -1812,7 +1812,8 @@
#define PCI_DEVICE_ID_INTEL_82434 0x04a3
#define PCI_DEVICE_ID_INTEL_I960 0x0960
#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
-#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
+#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
+#define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c
#define PCI_DEVICE_ID_INTEL_82542 0x1000
#define PCI_DEVICE_ID_INTEL_82543GC_FIBER 0x1001
#define PCI_DEVICE_ID_INTEL_82543GC_COPPER 0x1004
diff --git a/include/ppc405.h b/include/ppc405.h
index d953378..2231a5f 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -22,6 +22,10 @@
#ifndef __PPC405_H__
#define __PPC405_H__
+/* Define bits and masks for real-mode storage attribute control registers */
+#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
+#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
+
#ifndef CONFIG_IOP480
#define CFG_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
#else
@@ -363,31 +367,118 @@
#endif /* defined(CONFIG_405EZ) */
/******************************************************************************
- * SDRAM Controller
- ******************************************************************************/
- /* values for memcfga register - indirect addressing of these regs */
-#ifndef CONFIG_405EP
- #define mem_besra 0x00 /* bus error syndrome reg a */
- #define mem_besrsa 0x04 /* bus error syndrome reg set a */
- #define mem_besrb 0x08 /* bus error syndrome reg b */
- #define mem_besrsb 0x0c /* bus error syndrome reg set b */
- #define mem_bear 0x10 /* bus error address reg */
-#endif
- #define mem_mcopt1 0x20 /* memory controller options 1 */
- #define mem_status 0x24 /* memory status */
- #define mem_rtr 0x30 /* refresh timer reg */
- #define mem_pmit 0x34 /* power management idle timer */
- #define mem_mb0cf 0x40 /* memory bank 0 configuration */
- #define mem_mb1cf 0x44 /* memory bank 1 configuration */
-#ifndef CONFIG_405EP
- #define mem_mb2cf 0x48 /* memory bank 2 configuration */
- #define mem_mb3cf 0x4c /* memory bank 3 configuration */
-#endif
- #define mem_sdtr1 0x80 /* timing reg 1 */
-#ifndef CONFIG_405EP
- #define mem_ecccf 0x94 /* ECC configuration */
- #define mem_eccerr 0x98 /* ECC error status */
-#endif
+ * External Bus Controller (EBC)
+ *****************************************************************************/
+
+/* Bank Configuration Register */
+#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF)
+#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(unsigned long, n)) & \
+ EBC_BXCR_BAS_MASK) << 0)
+#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7)
+#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0)
+#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1)
+#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2)
+#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3)
+#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4)
+#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5)
+#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6)
+#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7)
+#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3)
+#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0)
+#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1)
+#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2)
+#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3)
+#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3)
+#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0)
+#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1)
+#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3)
+
+/* Bank Access Parameter Register */
+#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1)
+#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0)
+#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, \
+ (static_cast(unsigned long, n)) \
+ & 0xFF)
+#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, \
+ (static_cast(unsigned long, n)) \
+ & 0x1F)
+#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, \
+ (static_cast(unsigned long, n)) \
+ & 0x7)
+#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0)
+#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1)
+#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3)
+#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0)
+#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1)
+#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2)
+#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3)
+#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, \
+ (static_cast(unsigned long, n)) \
+ & 0x3)
+#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, \
+ (static_cast(unsigned long, n)) \
+ & 0x3)
+#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, \
+ (static_cast(unsigned long, n)) \
+ & 0x3)
+#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, \
+ (static_cast(unsigned long, n)) \
+ & 0x3)
+#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, \
+ (static_cast(unsigned long, n)) \
+ & 0x7)
+#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1)
+#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0)
+#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0)
+#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1)
+#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0)
+#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1)
+#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0)
+#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1)
+
+/* Configuration Register */
+#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1)
+#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0)
+#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1)
+#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1)
+#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0)
+#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1)
+#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7)
+#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0)
+#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1)
+#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2)
+#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3)
+#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4)
+#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5)
+#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6)
+#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7)
+#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1)
+#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0)
+#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1)
+#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1)
+#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0)
+#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1)
+#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1)
+#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0)
+#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1)
+#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1)
+#define EBC_CFG_OEO_DISABLE PPC_REG_VAL(8, 0x0)
+#define EBC_CFG_OEO_ENABLE PPC_REG_VAL(8, 0x1)
+#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1)
+#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0)
+#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1)
+#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1)
+#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0)
+#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1)
+#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F)
+#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, \
+ (static_cast(unsigned long, n)) \
+ & 0x1F)
+#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3)
+#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0)
+#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1)
+#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2)
+#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3)
#ifndef CONFIG_405EP
/******************************************************************************
@@ -1163,369 +1254,6 @@
#if defined(CONFIG_405EX)
#define SDR0_SRST 0x0200
-#define SDRAM_BESR0 0x00
-#define SDRAM_BEARL 0x02
-#define SDRAM_BEARU 0x03
-#define SDRAM_WMIRQ 0x06 /**/
-#define SDRAM_PLBOPT 0x08 /**/
-#define SDRAM_PUABA 0x09 /**/
-#define SDRAM_MCSTAT 0x1F /* memory controller status */
-#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
-#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
-#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
-#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
-#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
-#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
-#define SDRAM_CODT 0x26 /* on die termination for controller */
-#define SDRAM_VVPR 0x27 /* variable VRef programmming */
-#define SDRAM_OPARS 0x28 /* on chip driver control setup */
-#define SDRAM_OPART 0x29 /* on chip driver control trigger */
-#define SDRAM_RTR 0x30 /* refresh timer */
-#define SDRAM_PMIT 0x34 /* power management idle timer */
-#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
-#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
-#define SDRAM_MB2CF 0x48 /* memory bank 2 configuration */
-#define SDRAM_MB3CF 0x4C /* memory bank 3 configuration */
-#define SDRAM_INITPLR0 0x50 /* manual initialization control */
-#define SDRAM_INITPLR1 0x51 /* manual initialization control */
-#define SDRAM_INITPLR2 0x52 /* manual initialization control */
-#define SDRAM_INITPLR3 0x53 /* manual initialization control */
-#define SDRAM_INITPLR4 0x54 /* manual initialization control */
-#define SDRAM_INITPLR5 0x55 /* manual initialization control */
-#define SDRAM_INITPLR6 0x56 /* manual initialization control */
-#define SDRAM_INITPLR7 0x57 /* manual initialization control */
-#define SDRAM_INITPLR8 0x58 /* manual initialization control */
-#define SDRAM_INITPLR9 0x59 /* manual initialization control */
-#define SDRAM_INITPLR10 0x5a /* manual initialization control */
-#define SDRAM_INITPLR11 0x5b /* manual initialization control */
-#define SDRAM_INITPLR12 0x5c /* manual initialization control */
-#define SDRAM_INITPLR13 0x5d /* manual initialization control */
-#define SDRAM_INITPLR14 0x5e /* manual initialization control */
-#define SDRAM_INITPLR15 0x5f /* manual initialization control */
-#define SDRAM_RQDC 0x70 /* read DQS delay control */
-#define SDRAM_RFDC 0x74 /* read feedback delay control */
-#define SDRAM_RDCC 0x78 /* read data capture control */
-#define SDRAM_DLCR 0x7A /* delay line calibration */
-#define SDRAM_CLKTR 0x80 /* DDR clock timing */
-#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
-#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
-#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
-#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
-#define SDRAM_MMODE 0x88 /* memory mode */
-#define SDRAM_MEMODE 0x89 /* memory extended mode */
-#define SDRAM_ECCCR 0x98 /* ECC error status */
-#define SDRAM_RID 0xF8 /* revision ID */
-
-/*-----------------------------------------------------------------------------+
-| Memory Bank 0-7 configuration
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RXBAS_SDSZ_4 0x00000000 /* 4M */
-#define SDRAM_RXBAS_SDSZ_8 0x00001000 /* 8M */
-#define SDRAM_RXBAS_SDSZ_16 0x00002000 /* 16M */
-#define SDRAM_RXBAS_SDSZ_32 0x00003000 /* 32M */
-#define SDRAM_RXBAS_SDSZ_64 0x00004000 /* 64M */
-#define SDRAM_RXBAS_SDSZ_128 0x00005000 /* 128M */
-#define SDRAM_RXBAS_SDSZ_256 0x00006000 /* 256M */
-#define SDRAM_RXBAS_SDSZ_512 0x00007000 /* 512M */
-#define SDRAM_RXBAS_SDSZ_1024 0x00008000 /* 1024M */
-#define SDRAM_RXBAS_SDSZ_2048 0x00009000 /* 2048M */
-#define SDRAM_RXBAS_SDSZ_4096 0x0000a000 /* 4096M */
-#define SDRAM_RXBAS_SDSZ_8192 0x0000b000 /* 8192M */
-
-/*-----------------------------------------------------------------------------+
-| Memory Controller Status
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
-#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
-#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
-#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */
-#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
-#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */
-
-/*-----------------------------------------------------------------------------+
-| Memory Controller Options 1
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask */
-#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
-#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
-#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
-#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
-#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3)
-#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
-#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
-#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
-#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
-#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
-#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
-#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
-#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
-#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
-#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
-#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
-#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
-#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
-#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
-#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
-#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
-#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
-#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
-#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
-#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
-#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
-#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
-#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
-#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
-#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
-#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
-#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
-#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
-#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
-
-/*-----------------------------------------------------------------------------+
-| Memory Controller Options 2
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
-#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
-#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
-#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
-#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
-#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
-#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
-#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
-#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
-#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
-#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
-#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
-#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
-#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
-#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
-#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
-#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
-#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Refresh Timer Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RTR_RINT_MASK 0xFFF80000
-#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16)
-#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8)
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Read DQS Delay Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RQDC_RQDE_MASK 0x80000000
-#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
-#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
-#define SDRAM_RQDC_RQFD_MASK 0x000001FF
-#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
-
-#define SDRAM_RQDC_RQFD_MAX 0xFF
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Read Data Capture Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RDCC_RDSS_MASK 0xC0000000
-#define SDRAM_RDCC_RDSS_T1 0x00000000
-#define SDRAM_RDCC_RDSS_T2 0x40000000
-#define SDRAM_RDCC_RDSS_T3 0x80000000
-#define SDRAM_RDCC_RDSS_T4 0xC0000000
-#define SDRAM_RDCC_RSAE_MASK 0x00000001
-#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
-#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Read Feedback Delay Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RFDC_ARSE_MASK 0x80000000
-#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
-#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
-#define SDRAM_RFDC_RFOS_MASK 0x007F0000
-#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
-#define SDRAM_RFDC_RFFD_MASK 0x000003FF
-#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
-
-#define SDRAM_RFDC_RFFD_MAX 0x4FF
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Delay Line Calibration Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_DLCR_DCLM_MASK 0x80000000
-#define SDRAM_DLCR_DCLM_MANUEL 0x80000000
-#define SDRAM_DLCR_DCLM_AUTO 0x00000000
-#define SDRAM_DLCR_DLCR_MASK 0x08000000
-#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
-#define SDRAM_DLCR_DLCR_IDLE 0x00000000
-#define SDRAM_DLCR_DLCS_MASK 0x07000000
-#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
-#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
-#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
-#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
-#define SDRAM_DLCR_DLCS_ERROR 0x04000000
-#define SDRAM_DLCR_DLCV_MASK 0x000001FF
-#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
-#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Controller On Die Termination Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_CODT_ODT_ON 0x80000000
-#define SDRAM_CODT_ODT_OFF 0x00000000
-#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
-#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
-#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
-#define SDRAM_CODT_DQS_MASK 0x00000010
-#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
-#define SDRAM_CODT_DQS_SINGLE_END 0x00000010
-#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
-#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
-#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
-#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
-#define SDRAM_CODT_IO_HIZ 0x00000000
-#define SDRAM_CODT_IO_NMODE 0x00000001
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Mode Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MMODE_WR_MASK 0x00000E00
-#define SDRAM_MMODE_WR_DDR1 0x00000000
-#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
-#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
-#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
-#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
-#define SDRAM_MMODE_DCL_MASK 0x00000070
-#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
-#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
-#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
-#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
-#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
-#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
-#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
-#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
-#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Extended Mode Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MEMODE_DIC_MASK 0x00000002
-#define SDRAM_MEMODE_DIC_NORMAL 0x00000000
-#define SDRAM_MEMODE_DIC_WEAK 0x00000002
-#define SDRAM_MEMODE_DLL_MASK 0x00000001
-#define SDRAM_MEMODE_DLL_DISABLE 0x00000001
-#define SDRAM_MEMODE_DLL_ENABLE 0x00000000
-#define SDRAM_MEMODE_RTT_MASK 0x00000044
-#define SDRAM_MEMODE_RTT_DISABLED 0x00000000
-#define SDRAM_MEMODE_RTT_75OHM 0x00000004
-#define SDRAM_MEMODE_RTT_150OHM 0x00000040
-#define SDRAM_MEMODE_DQS_MASK 0x00000400
-#define SDRAM_MEMODE_DQS_DISABLE 0x00000400
-#define SDRAM_MEMODE_DQS_ENABLE 0x00000000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Clock Timing Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
-#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
-#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Write Timing Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_WRDTR_WDTP_1_CYC 0x80000000
-#define SDRAM_WRDTR_LLWP_MASK 0x10000000
-#define SDRAM_WRDTR_LLWP_DIS 0x10000000
-#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
-#define SDRAM_WRDTR_WTR_MASK 0x0E000000
-#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
-#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
-#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM SDTR1 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR1_LDOF_MASK 0x80000000
-#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
-#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
-#define SDRAM_SDTR1_RTW_MASK 0x00F00000
-#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
-#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
-#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
-#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
-#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
-#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
-#define SDRAM_SDTR1_RTRO_1_CLK 0x00000000
-#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM SDTR2 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR2_RCD_MASK 0xF0000000
-#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
-#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
-#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
-#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
-#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
-#define SDRAM_SDTR2_WTR_MASK 0x0F000000
-#define SDRAM_SDTR2_WTR_1_CLK 0x01000000
-#define SDRAM_SDTR2_WTR_2_CLK 0x02000000
-#define SDRAM_SDTR2_WTR_3_CLK 0x03000000
-#define SDRAM_SDTR2_WTR_4_CLK 0x04000000
-#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
-#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
-#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
-#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
-#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
-#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
-#define SDRAM_SDTR2_WPC_MASK 0x0000F000
-#define SDRAM_SDTR2_WPC_2_CLK 0x00002000
-#define SDRAM_SDTR2_WPC_3_CLK 0x00003000
-#define SDRAM_SDTR2_WPC_4_CLK 0x00004000
-#define SDRAM_SDTR2_WPC_5_CLK 0x00005000
-#define SDRAM_SDTR2_WPC_6_CLK 0x00006000
-#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12)
-#define SDRAM_SDTR2_RPC_MASK 0x00000F00
-#define SDRAM_SDTR2_RPC_2_CLK 0x00000200
-#define SDRAM_SDTR2_RPC_3_CLK 0x00000300
-#define SDRAM_SDTR2_RPC_4_CLK 0x00000400
-#define SDRAM_SDTR2_RP_MASK 0x000000F0
-#define SDRAM_SDTR2_RP_3_CLK 0x00000030
-#define SDRAM_SDTR2_RP_4_CLK 0x00000040
-#define SDRAM_SDTR2_RP_5_CLK 0x00000050
-#define SDRAM_SDTR2_RP_6_CLK 0x00000060
-#define SDRAM_SDTR2_RP_7_CLK 0x00000070
-#define SDRAM_SDTR2_RRD_MASK 0x0000000F
-#define SDRAM_SDTR2_RRD_2_CLK 0x00000002
-#define SDRAM_SDTR2_RRD_3_CLK 0x00000003
-
-/*-----------------------------------------------------------------------------+
-| SDRAM SDTR3 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR3_RAS_MASK 0x1F000000
-#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
-#define SDRAM_SDTR3_RC_MASK 0x001F0000
-#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
-#define SDRAM_SDTR3_XCS_MASK 0x00001F00
-#define SDRAM_SDTR3_XCS 0x00000D00
-#define SDRAM_SDTR3_RFC_MASK 0x0000003F
-#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
-
-/*-----------------------------------------------------------------------------+
-| Memory Bank 0-1 configuration
-+-----------------------------------------------------------------------------*/
-#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
-#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
-#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
-#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
-#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
-#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
-#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
-#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
-#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
-#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
-#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
-#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
-#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
-#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
-
#define sdr_uart0 0x0120 /* UART0 Config */
#define sdr_uart1 0x0121 /* UART1 Config */
#define sdr_mfr 0x4300 /* SDR0_MFR reg */
@@ -1612,4 +1340,27 @@
#define SDR0_PFC1_GPT_FREQ 0x0000000f
#endif
+/* General Purpose Timer (GPT) Register Offsets */
+#define GPT0_TBC 0x00000000
+#define GPT0_IM 0x00000018
+#define GPT0_ISS 0x0000001C
+#define GPT0_ISC 0x00000020
+#define GPT0_IE 0x00000024
+#define GPT0_COMP0 0x00000080
+#define GPT0_COMP1 0x00000084
+#define GPT0_COMP2 0x00000088
+#define GPT0_COMP3 0x0000008C
+#define GPT0_COMP4 0x00000090
+#define GPT0_COMP5 0x00000094
+#define GPT0_COMP6 0x00000098
+#define GPT0_MASK0 0x000000C0
+#define GPT0_MASK1 0x000000C4
+#define GPT0_MASK2 0x000000C8
+#define GPT0_MASK3 0x000000CC
+#define GPT0_MASK4 0x000000D0
+#define GPT0_MASK5 0x000000D4
+#define GPT0_MASK6 0x000000D8
+#define GPT0_DCT0 0x00000110
+#define GPT0_DCIS 0x0000011C
+
#endif /* __PPC405_H__ */
diff --git a/include/ppc440.h b/include/ppc440.h
index 54b4553..62f1680 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -210,36 +210,6 @@
#define sdr_plbtr 0x4200
#define sdr_mfr 0x4300 /* SDR0_MFR reg */
-/*-----------------------------------------------------------------------------
- | SDRAM Controller
- +----------------------------------------------------------------------------*/
-/* values for memcfga register - indirect addressing of these regs */
-#define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
-#define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
-#define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */
-#define mem_besr1_set 0x000c /* bus error status reg 1 (set) */
-#define mem_bear 0x0010 /* bus error address reg */
-#define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */
-#define mem_mirq_set 0x0012 /* bus master interrupt (set) */
-#define mem_slio 0x0018 /* ddr sdram slave interface options */
-#define mem_cfg0 0x0020 /* ddr sdram options 0 */
-#define mem_cfg1 0x0021 /* ddr sdram options 1 */
-#define mem_devopt 0x0022 /* ddr sdram device options */
-#define mem_mcsts 0x0024 /* memory controller status */
-#define mem_rtr 0x0030 /* refresh timer register */
-#define mem_pmit 0x0034 /* power management idle timer */
-#define mem_uabba 0x0038 /* plb UABus base address */
-#define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */
-#define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */
-#define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */
-#define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */
-#define mem_tr0 0x0080 /* sdram timing register 0 */
-#define mem_tr1 0x0081 /* sdram timing register 1 */
-#define mem_clktr 0x0082 /* ddr clock timing register */
-#define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */
-#define mem_dlycal 0x0084 /* delay line calibration register */
-#define mem_eccesr 0x0098 /* ECC error status */
-
#ifdef CONFIG_440GX
#define sdr_amp 0x0240
#define sdr_xpllc 0x01c1
@@ -380,872 +350,6 @@
#define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
#endif /* CONFIG_440SPE */
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-/*----------------------------------------------------------------------------+
-| SDRAM Controller
-+----------------------------------------------------------------------------*/
-/*-----------------------------------------------------------------------------+
-| SDRAM DLYCAL Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
-#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
-#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
-
-/*----------------------------------------------------------------------------+
-| Memory queue defines
-+----------------------------------------------------------------------------*/
-/* A REVOIR versus RWC - SG*/
-#define SDRAMQ_DCR_BASE 0x040
-
-#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
-#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
-#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
-#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
-#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
-#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
-#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
-#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
-#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
-#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
-#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
-#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
-#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
-#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
-#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
-
-/*-----------------------------------------------------------------------------+
-| Memory Bank 0-7 configuration
-+-----------------------------------------------------------------------------*/
-#if defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
-#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2)
-#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2)
-#endif /* CONFIG_440SPE */
-#if defined(CONFIG_440SP)
-#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
-#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFF800000))
-#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFF800000))
-#endif /* CONFIG_440SP */
-#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
-#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6)
-#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF)
-#define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */
-#define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */
-#define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */
-#define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */
-#define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */
-#define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */
-#define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */
-#define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */
-#define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */
-#define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */
-#define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */
-
-/*----------------------------------------------------------------------------+
-| Memory controller defines
-+----------------------------------------------------------------------------*/
-/* A REVOIR versus specs 4 bank - SG*/
-#define SDRAM_MCSTAT 0x14 /* memory controller status */
-#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
-#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
-#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
-#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
-#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
-#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
-#define SDRAM_CODT 0x26 /* on die termination for controller */
-#define SDRAM_VVPR 0x27 /* variable VRef programmming */
-#define SDRAM_OPARS 0x28 /* on chip driver control setup */
-#define SDRAM_OPART 0x29 /* on chip driver control trigger */
-#define SDRAM_RTR 0x30 /* refresh timer */
-#define SDRAM_PMIT 0x34 /* power management idle timer */
-#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
-#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
-#define SDRAM_MB2CF 0x48
-#define SDRAM_MB3CF 0x4C
-#define SDRAM_INITPLR0 0x50 /* manual initialization control */
-#define SDRAM_INITPLR1 0x51 /* manual initialization control */
-#define SDRAM_INITPLR2 0x52 /* manual initialization control */
-#define SDRAM_INITPLR3 0x53 /* manual initialization control */
-#define SDRAM_INITPLR4 0x54 /* manual initialization control */
-#define SDRAM_INITPLR5 0x55 /* manual initialization control */
-#define SDRAM_INITPLR6 0x56 /* manual initialization control */
-#define SDRAM_INITPLR7 0x57 /* manual initialization control */
-#define SDRAM_INITPLR8 0x58 /* manual initialization control */
-#define SDRAM_INITPLR9 0x59 /* manual initialization control */
-#define SDRAM_INITPLR10 0x5a /* manual initialization control */
-#define SDRAM_INITPLR11 0x5b /* manual initialization control */
-#define SDRAM_INITPLR12 0x5c /* manual initialization control */
-#define SDRAM_INITPLR13 0x5d /* manual initialization control */
-#define SDRAM_INITPLR14 0x5e /* manual initialization control */
-#define SDRAM_INITPLR15 0x5f /* manual initialization control */
-#define SDRAM_RQDC 0x70 /* read DQS delay control */
-#define SDRAM_RFDC 0x74 /* read feedback delay control */
-#define SDRAM_RDCC 0x78 /* read data capture control */
-#define SDRAM_DLCR 0x7A /* delay line calibration */
-#define SDRAM_CLKTR 0x80 /* DDR clock timing */
-#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
-#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
-#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
-#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
-#define SDRAM_MMODE 0x88 /* memory mode */
-#define SDRAM_MEMODE 0x89 /* memory extended mode */
-#define SDRAM_ECCCR 0x98 /* ECC error status */
-#define SDRAM_CID 0xA4 /* core ID */
-#define SDRAM_RID 0xA8 /* revision ID */
-#define SDRAM_RTSR 0xB1 /* run time status tracking */
-
-/*-----------------------------------------------------------------------------+
-| Memory Controller Status
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
-#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
-#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
-#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */
-#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
-#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */
-#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */
-#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */
-#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */
-
-/*-----------------------------------------------------------------------------+
-| Memory Controller Options 1
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/
-#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
-#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
-#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
-#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
-#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3)
-#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
-#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
-#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
-#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
-#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
-#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
-#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
-#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
-#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
-#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
-#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
-#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
-#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
-#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
-#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
-#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
-#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
-#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
-#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
-#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
-#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
-#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
-#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
-#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
-#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
-#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
-#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
-#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
-#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
-
-/*-----------------------------------------------------------------------------+
-| Memory Controller Options 2
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
-#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
-#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
-#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
-#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
-#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
-#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
-#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
-#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
-#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
-#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
-#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
-#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
-#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
-#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
-#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
-#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
-#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Refresh Timer Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RTR_RINT_MASK 0xFFF80000
-#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16)
-#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8)
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Read DQS Delay Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RQDC_RQDE_MASK 0x80000000
-#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
-#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
-#define SDRAM_RQDC_RQFD_MASK 0x000001FF
-#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
-
-#define SDRAM_RQDC_RQFD_MAX 0x1FF
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Read Data Capture Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RDCC_RDSS_MASK 0xC0000000
-#define SDRAM_RDCC_RDSS_T1 0x00000000
-#define SDRAM_RDCC_RDSS_T2 0x40000000
-#define SDRAM_RDCC_RDSS_T3 0x80000000
-#define SDRAM_RDCC_RDSS_T4 0xC0000000
-#define SDRAM_RDCC_RSAE_MASK 0x00000001
-#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
-#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Read Feedback Delay Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RFDC_ARSE_MASK 0x80000000
-#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
-#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
-#define SDRAM_RFDC_RFOS_MASK 0x007F0000
-#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
-#define SDRAM_RFDC_RFFD_MASK 0x000007FF
-#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x7FF)<<0)
-
-#define SDRAM_RFDC_RFFD_MAX 0x7FF
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Delay Line Calibration Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_DLCR_DCLM_MASK 0x80000000
-#define SDRAM_DLCR_DCLM_MANUEL 0x80000000
-#define SDRAM_DLCR_DCLM_AUTO 0x00000000
-#define SDRAM_DLCR_DLCR_MASK 0x08000000
-#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
-#define SDRAM_DLCR_DLCR_IDLE 0x00000000
-#define SDRAM_DLCR_DLCS_MASK 0x07000000
-#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
-#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
-#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
-#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
-#define SDRAM_DLCR_DLCS_ERROR 0x04000000
-#define SDRAM_DLCR_DLCV_MASK 0x000001FF
-#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
-#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Controller On Die Termination Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_CODT_ODT_ON 0x80000000
-#define SDRAM_CODT_ODT_OFF 0x00000000
-#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
-#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
-#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
-#define SDRAM_CODT_DQS_MASK 0x00000010
-#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
-#define SDRAM_CODT_DQS_SINGLE_END 0x00000010
-#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
-#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
-#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
-#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
-#define SDRAM_CODT_IO_HIZ 0x00000000
-#define SDRAM_CODT_IO_NMODE 0x00000001
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Mode Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MMODE_WR_MASK 0x00000E00
-#define SDRAM_MMODE_WR_DDR1 0x00000000
-#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
-#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
-#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
-#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
-#define SDRAM_MMODE_DCL_MASK 0x00000070
-#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
-#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
-#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
-#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
-#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
-#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
-#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
-#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
-#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Extended Mode Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MEMODE_DIC_MASK 0x00000002
-#define SDRAM_MEMODE_DIC_NORMAL 0x00000000
-#define SDRAM_MEMODE_DIC_WEAK 0x00000002
-#define SDRAM_MEMODE_DLL_MASK 0x00000001
-#define SDRAM_MEMODE_DLL_DISABLE 0x00000001
-#define SDRAM_MEMODE_DLL_ENABLE 0x00000000
-#define SDRAM_MEMODE_RTT_MASK 0x00000044
-#define SDRAM_MEMODE_RTT_DISABLED 0x00000000
-#define SDRAM_MEMODE_RTT_75OHM 0x00000004
-#define SDRAM_MEMODE_RTT_150OHM 0x00000040
-#define SDRAM_MEMODE_DQS_MASK 0x00000400
-#define SDRAM_MEMODE_DQS_DISABLE 0x00000400
-#define SDRAM_MEMODE_DQS_ENABLE 0x00000000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Clock Timing Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
-#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
-#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
-#define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000
-#define SDRAM_CLKTR_CLKP_270_DEG_ADV 0xC0000000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM Write Timing Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_WRDTR_LLWP_MASK 0x10000000
-#define SDRAM_WRDTR_LLWP_DIS 0x10000000
-#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
-#define SDRAM_WRDTR_WTR_MASK 0x0E000000
-#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
-#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000
-#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
-#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM SDTR1 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR1_LDOF_MASK 0x80000000
-#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
-#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
-#define SDRAM_SDTR1_RTW_MASK 0x00F00000
-#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
-#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
-#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
-#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
-#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
-#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
-#define SDRAM_SDTR1_RTRO_1_CLK 0x00001000
-#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
-
-/*-----------------------------------------------------------------------------+
-| SDRAM SDTR2 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR2_RCD_MASK 0xF0000000
-#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
-#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
-#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
-#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
-#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
-#define SDRAM_SDTR2_WTR_MASK 0x0F000000
-#define SDRAM_SDTR2_WTR_1_CLK 0x01000000
-#define SDRAM_SDTR2_WTR_2_CLK 0x02000000
-#define SDRAM_SDTR2_WTR_3_CLK 0x03000000
-#define SDRAM_SDTR2_WTR_4_CLK 0x04000000
-#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
-#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
-#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
-#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
-#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
-#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
-#define SDRAM_SDTR2_WPC_MASK 0x0000F000
-#define SDRAM_SDTR2_WPC_2_CLK 0x00002000
-#define SDRAM_SDTR2_WPC_3_CLK 0x00003000
-#define SDRAM_SDTR2_WPC_4_CLK 0x00004000
-#define SDRAM_SDTR2_WPC_5_CLK 0x00005000
-#define SDRAM_SDTR2_WPC_6_CLK 0x00006000
-#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12)
-#define SDRAM_SDTR2_RPC_MASK 0x00000F00
-#define SDRAM_SDTR2_RPC_2_CLK 0x00000200
-#define SDRAM_SDTR2_RPC_3_CLK 0x00000300
-#define SDRAM_SDTR2_RPC_4_CLK 0x00000400
-#define SDRAM_SDTR2_RP_MASK 0x000000F0
-#define SDRAM_SDTR2_RP_3_CLK 0x00000030
-#define SDRAM_SDTR2_RP_4_CLK 0x00000040
-#define SDRAM_SDTR2_RP_5_CLK 0x00000050
-#define SDRAM_SDTR2_RP_6_CLK 0x00000060
-#define SDRAM_SDTR2_RP_7_CLK 0x00000070
-#define SDRAM_SDTR2_RRD_MASK 0x0000000F
-#define SDRAM_SDTR2_RRD_2_CLK 0x00000002
-#define SDRAM_SDTR2_RRD_3_CLK 0x00000003
-
-/*-----------------------------------------------------------------------------+
-| SDRAM SDTR3 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR3_RAS_MASK 0x1F000000
-#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
-#define SDRAM_SDTR3_RC_MASK 0x001F0000
-#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
-#define SDRAM_SDTR3_XCS_MASK 0x00001F00
-#define SDRAM_SDTR3_XCS 0x00000D00
-#define SDRAM_SDTR3_RFC_MASK 0x0000003F
-#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
-
-/*-----------------------------------------------------------------------------+
-| Memory Bank 0-1 configuration
-+-----------------------------------------------------------------------------*/
-#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
-#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
-#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
-#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
-#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
-#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
-#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
-#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
-#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
-#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
-#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
-#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
-#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
-#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
-
-#define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/
-#define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */
-#define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */
-#define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */
-#define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */
-
-#define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */
-#endif /* CONFIG_440SPE */
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-/*-----------------------------------------------------------------------------
- | SDRAM Controller
- +----------------------------------------------------------------------------*/
-#define DDR0_00 0x00
-#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
-#define DDR0_00_INT_ACK_ALL 0x7F000000
-#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
-/* Status */
-#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
-/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
-#define DDR0_00_INT_STATUS_BIT0 0x00010000
-/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
-#define DDR0_00_INT_STATUS_BIT1 0x00020000
-/* Bit2. Single correctable ECC event detected */
-#define DDR0_00_INT_STATUS_BIT2 0x00040000
-/* Bit3. Multiple correctable ECC events detected. */
-#define DDR0_00_INT_STATUS_BIT3 0x00080000
-/* Bit4. Single uncorrectable ECC event detected. */
-#define DDR0_00_INT_STATUS_BIT4 0x00100000
-/* Bit5. Multiple uncorrectable ECC events detected. */
-#define DDR0_00_INT_STATUS_BIT5 0x00200000
-/* Bit6. DRAM initialization complete. */
-#define DDR0_00_INT_STATUS_BIT6 0x00400000
-/* Bit7. Logical OR of all lower bits. */
-#define DDR0_00_INT_STATUS_BIT7 0x00800000
-
-#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
-#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
-#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_01 0x01
-#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
-#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
-#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
-#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
-#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
-#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
-#define DDR0_01_INT_MASK_MASK 0x000000FF
-#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
-#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
-#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
-
-#define DDR0_02 0x02
-#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
-#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
-#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
-#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
-#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
-#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
-#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
-#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_02_START_MASK 0x00000001
-#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
-#define DDR0_02_START_OFF 0x00000000
-#define DDR0_02_START_ON 0x00000001
-
-#define DDR0_03 0x03
-#define DDR0_03_BSTLEN_MASK 0x07000000
-#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_03_CASLAT_MASK 0x00070000
-#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
-#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_03_INITAREF_MASK 0x0000000F
-#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
-#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
-
-#define DDR0_04 0x04
-#define DDR0_04_TRC_MASK 0x1F000000
-#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_04_TRRD_MASK 0x00070000
-#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_04_TRTP_MASK 0x00000700
-#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
-
-#define DDR0_05 0x05
-#define DDR0_05_TMRD_MASK 0x1F000000
-#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_05_TEMRS_MASK 0x00070000
-#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_05_TRP_MASK 0x00000F00
-#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_05_TRAS_MIN_MASK 0x000000FF
-#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
-
-#define DDR0_06 0x06
-#define DDR0_06_WRITEINTERP_MASK 0x01000000
-#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_06_TWTR_MASK 0x00070000
-#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_06_TDLL_MASK 0x0000FF00
-#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
-#define DDR0_06_TRFC_MASK 0x0000007F
-#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_07 0x07
-#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
-#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_07_TFAW_MASK 0x001F0000
-#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
-#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
-#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
-#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
-#define DDR0_07_AREFRESH_MASK 0x00000001
-#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_08 0x08
-#define DDR0_08_WRLAT_MASK 0x07000000
-#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_08_TCPD_MASK 0x00FF0000
-#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_08_DQS_N_EN_MASK 0x00000100
-#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
-#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
-#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_09 0x09
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_09_RTT_0_MASK 0x00030000
-#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
-#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
-#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_10 0x0A
-#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
-#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_10_CS_MAP_MASK 0x00000300
-#define DDR0_10_CS_MAP_NO_MEM 0x00000000
-#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
-#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
-#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
-#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
-
-#define DDR0_11 0x0B
-#define DDR0_11_SREFRESH_MASK 0x01000000
-#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_11_TXSNR_MASK 0x00FF0000
-#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_11_TXSR_MASK 0x0000FF00
-#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
-
-#define DDR0_12 0x0C
-#define DDR0_12_TCKE_MASK 0x0000007
-#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
-#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
-
-#define DDR0_14 0x0E
-#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
-#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_14_REDUC_MASK 0x00010000
-#define DDR0_14_REDUC_64BITS 0x00000000
-#define DDR0_14_REDUC_32BITS 0x00010000
-#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
-#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
-
-#define DDR0_17 0x11
-#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
-#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
-#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
-#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
-#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
-#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
-
-#define DDR0_18 0x12
-#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
-#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
-#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
-#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
-#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
-#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_19 0x13
-#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
-#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
-#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
-#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
-#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
-#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_20 0x14
-#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
-#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
-#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
-#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
-#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_21 0x15
-#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
-#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
-#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
-#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
-#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_22 0x16
-#define DDR0_22_CTRL_RAW_MASK 0x03000000
-#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
-#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct */
-#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
-#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
-#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
-#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
-#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_23 0x17
-#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
-#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
-#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
-#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
-#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
-#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
-#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_24 0x18
-#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
-#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
-#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
-#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
-#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
-#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
-#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
-#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
-#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
-#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
-#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
-
-#define DDR0_25 0x19
-#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
-#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
-#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
-#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
-#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
-#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
-
-#define DDR0_26 0x1A
-#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
-#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
-#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
-#define DDR0_26_TREF_MASK 0x00003FFF
-#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
-#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
-
-#define DDR0_27 0x1B
-#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
-#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
-#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
-#define DDR0_27_TINIT_MASK 0x0000FFFF
-#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
-#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
-
-#define DDR0_28 0x1C
-#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
-#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
-#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
-#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
-#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
-#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
-
-#define DDR0_31 0x1F
-#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
-#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
-#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
-
-#define DDR0_32 0x20
-#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
-#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_33 0x21
-#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
-#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_34 0x22
-#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
-#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_35 0x23
-#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
-#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_36 0x24
-#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
-#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_37 0x25
-#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
-#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_38 0x26
-#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
-#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_39 0x27
-#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
-#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_40 0x28
-#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
-#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_41 0x29
-#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
-#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_42 0x2A
-#define DDR0_42_ADDR_PINS_MASK 0x07000000
-#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
-#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
-#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
-
-#define DDR0_43 0x2B
-#define DDR0_43_TWR_MASK 0x07000000
-#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_43_APREBIT_MASK 0x000F0000
-#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
-#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
-#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
-#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
-#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
-#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
-#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
-#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_44 0x2C
-#define DDR0_44_TRCD_MASK 0x000000FF
-#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
-
-#endif /* CONFIG_440EPX */
-
/*-----------------------------------------------------------------------------
| External Bus Controller
+----------------------------------------------------------------------------*/
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 76fe872..0a8479f 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -22,12 +22,52 @@
#ifndef __PPC4XX_H__
#define __PPC4XX_H__
+/*
+ * Configure which SDRAM/DDR/DDR2 controller is equipped
+ */
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
+ defined(CONFIG_AP1000) || defined(CONFIG_ML2)
+#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
+#endif
+
+#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
+#endif
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
+#endif
+
+#if defined(CONFIG_405EX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
+#endif
+
#if defined(CONFIG_440)
#include <ppc440.h>
#else
#include <ppc405.h>
#endif
+#include <asm/ppc4xx-sdram.h>
+
+/*
+ * Macro for generating register field mnemonics
+ */
+#define PPC_REG_BITS 32
+#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
+
+/*
+ * Elide casts when assembling register mnemonics
+ */
+#ifndef __ASSEMBLY__
+#define static_cast(type, val) (type)(val)
+#else
+#define static_cast(type, val) (val)
+#endif
+
/*
* Common stuff for 4xx (405 and 440)
*/