diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-ppc/config.h | 4 | ||||
-rw-r--r-- | include/asm-ppc/ppc4xx-sdram.h | 2 | ||||
-rw-r--r-- | include/configs/katmai.h | 1 | ||||
-rw-r--r-- | include/configs/kilauea.h | 7 |
4 files changed, 4 insertions, 10 deletions
diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index 6d27cb1..2a4ee15 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -22,10 +22,10 @@ #define _ASM_CONFIG_H_ #ifndef CONFIG_MAX_MEM_MAPPED -#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) && defined(CONFIG_SPD_EEPROM) +#if defined(CONFIG_4xx) #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #else -#define CONFIG_MAX_MEM_MAPPED (256 << 20) +#define CONFIG_MAX_MEM_MAPPED (256 << 20) #endif #endif diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 98faced..992a3d2 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -566,6 +566,8 @@ #define SDRAM_RDCC_RSAE_MASK 0x00000001 #define SDRAM_RDCC_RSAE_DISABLE 0x00000001 #define SDRAM_RDCC_RSAE_ENABLE 0x00000000 +#define SDRAM_RDCC_RDSS_ENCODE(n) ((((u32)(n))&0x03)<<30) +#define SDRAM_RDCC_RDSS_DECODE(n) ((((u32)(n))>>30)&0x03) /* * SDRAM Read Feedback Delay Control Register diff --git a/include/configs/katmai.h b/include/configs/katmai.h index ea6cf0d..0d89594 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -45,7 +45,6 @@ */ #define CONFIG_PHYS_64BIT #define CONFIG_VERY_BIG_RAM -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) /* * Include common defines/options for all AMCC eval boards diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 4d3ccf5..26cb854 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -234,16 +234,9 @@ * * DDR Autocalibration Method_B is the default. */ -#if 0 -/* - * Needs FIX!!! - * Disable autocalibration for now, because of the unresolved problem - * with kilauea board using 200MHz PLB/DDR2 frequency - */ #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ #undef CONFIG_PPC4xx_DDR_METHOD_A -#endif #define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE) |