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-rw-r--r--include/configs/MPC8610HPCD.h31
-rw-r--r--include/configs/MPC8641HPCN.h70
-rw-r--r--include/configs/sbc8641d.h7
3 files changed, 77 insertions, 31 deletions
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 67b2764..4486763 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -36,6 +36,12 @@
#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
+/*
+ * virtual address to be used for temporary mappings. There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA 0xc0000000
+
#define CONFIG_PCI 1 /* Enable PCI/PCIE*/
#define CONFIG_PCI1 1 /* PCI controler 1 */
#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
@@ -92,6 +98,7 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
#define MPC86xx_DDR_SDRAM_CLK_CNTL
@@ -370,27 +377,29 @@
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
/*
- * BAT3 32M Cache-inhibited, guarded
- * 0xe200_0000 1M PCI-Express 2 I/O
- * 0xe300_0000 1M PCI-Express 1 I/O
+ * BAT3 4M Cache-inhibited, guarded
+ * 0xe000_0000 4M CCSR
*/
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
/*
- * BAT4 4M Cache-inhibited, guarded
- * 0xe000_0000 4M CCSR
+ * BAT4 32M Cache-inhibited, guarded
+ * 0xe200_0000 1M PCI-Express 2 I/O
+ * 0xe300_0000 1M PCI-Express 1 I/O
*/
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
+
+#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
+
/*
* BAT5 128K Cacheable, non-guarded
* 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 542877b..1401e15 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -45,11 +45,24 @@
#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
+/*
+ * virtual address to be used for temporary mappings. There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA 0xe0000000
+
+/*
+ * set this to enable Rapid IO. PCI and RIO are mutually exclusive
+ */
+/*#define CONFIG_RIO 1*/
+
+#ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */
#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
+#endif
#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
@@ -102,6 +115,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
#define MPC86xx_DDR_SDRAM_CLK_CNTL
@@ -162,21 +176,26 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+/* Convert an address into the right format for the BR registers */
+#define BR_PHYS_ADDR(x) (x & 0xffff8000)
+
#define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/
#define CONFIG_SYS_BR1_PRELIM 0xfe001001 /* port size 16bit */
#define CONFIG_SYS_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/
-#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
+#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE) \
+ | 0x000001001) /* port size 16bit */
#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
-#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
+#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE) \
+ | 0x00000801) /* port size 8bit */
#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
+#define PIXIS_BASE (CONFIG_SYS_CCSRBAR + 0x00100000) /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
@@ -193,6 +212,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
+/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
+#define CF_BASE (PIXIS_BASE + 0x00100000)
+
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
@@ -298,11 +320,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
#define _IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
+#define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \
+ + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
+#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
+ + CONFIG_SYS_PCI1_IO_SIZE)
#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
@@ -331,12 +355,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
-#endif
-
/*PCIE video card used*/
#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_PHYS
@@ -418,26 +436,38 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
/*
- * BAT1 1G Cache-inhibited, guarded
+ * BAT1 unused
+ */
+#define CONFIG_SYS_DBAT1L 0
+#define CONFIG_SYS_DBAT1U 0
+#define CONFIG_SYS_IBAT1L 0
+#define CONFIG_SYS_IBAT1U 0
+
+/* if CONFIG_PCI:
+ * BAT2 1G Cache-inhibited, guarded
* 0x8000_0000 512M PCI-Express 1 Memory
* 0xa000_0000 512M PCI-Express 2 Memory
* Changed it for operating from 0xd0000000
- */
-#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
-
-/*
+ *
+ * if CONFIG_RIO
* BAT2 512M Cache-inhibited, guarded
* 0xc000_0000 512M RapidIO Memory
*/
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G \
+ | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
+ | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#else /* CONFIG_RIO */
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#endif
/*
* BAT3 4M Cache-inhibited, guarded
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 09a9901..e8216ea 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -49,6 +49,12 @@
#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
+/*
+ * virtual address to be used for temporary mappings. There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA 0xe8000000
+
#define CONFIG_PCI 1 /* Enable PCIE */
#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */
@@ -108,6 +114,7 @@
#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
#define MPC86xx_DDR_SDRAM_CLK_CNTL