diff options
Diffstat (limited to 'include')
32 files changed, 1336 insertions, 845 deletions
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 72459d8..33ee2c4 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -52,6 +52,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "fdtaddr=0x80F80000\0" \ + "fdt_high=0xffffffff\0" \ "rdaddr=0x81000000\0" \ "bootfile=/boot/uImage\0" \ "fdtfile=\0" \ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h new file mode 100644 index 0000000..1616b39 --- /dev/null +++ b/include/configs/cardhu.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/sizes.h> + +#include "tegra30-common.h" + +/* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra30-cardhu +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra30 (Cardhu) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_TEGRA_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C + +#define CONFIG_ENV_IS_NOWHERE + +/* SPI */ +#define CONFIG_TEGRA_SLINK +#define CONFIG_TEGRA_SLINK_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index d8aabd4..c7f36ff 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -37,7 +37,6 @@ #define CONFIG_SYS_COREBOOT #define CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_LAST_STAGE_INIT -#define CONFIG_X86_NO_RESET_VECTOR #define CONFIG_SYS_VSNPRINTF #define CONFIG_INTEL_CORE_ARCH /* Sandy bridge and ivy bridge chipsets. */ #define CONFIG_ZBOOT_32 diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h new file mode 100644 index 0000000..ce32c80 --- /dev/null +++ b/include/configs/dalmore.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/sizes.h> + +#include "tegra114-common.h" + +/* Must be off for Dalmore to boot !?!? FIXME */ +#define CONFIG_SYS_DCACHE_OFF + +/* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra114-dalmore +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra114 (Dalmore) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Dalmore" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_DALMORE + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ENV_IS_NOWHERE + +#define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */ + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/eNET.h b/include/configs/eNET.h deleted file mode 100644 index 28cf95b..0000000 --- a/include/configs/eNET.h +++ /dev/null @@ -1,619 +0,0 @@ -/* - * (C) Copyright 2008 - * Graeme Russ, graeme.russ@gmail.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <asm/ibmpc.h> -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SYS_SC520 -#define CONFIG_SYS_SC520_SSI -#define CONFIG_SHOW_BOOT_PROGRESS -#define CONFIG_LAST_STAGE_INIT - -/*----------------------------------------------------------------------- - * Watchdog Configuration - * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the - * bottom (processor) board MUST be removed! - */ -#undef CONFIG_WATCHDOG -#define CONFIG_HW_WATCHDOG - -/*----------------------------------------------------------------------- - * Real Time Clock Configuration - */ -#define CONFIG_RTC_MC146818 -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 - -/*----------------------------------------------------------------------- - * Serial Configuration - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 1843200 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \ - 9600, 19200, 38400, 115200} -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_NS16550_COM2 UART1_BASE -#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE) -#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE) -#define CONFIG_SYS_NS16550_PORT_MAPPED - -/*----------------------------------------------------------------------- - * Video Configuration - */ -#undef CONFIG_VIDEO -#undef CONFIG_CFB_CONSOLE - -/*----------------------------------------------------------------------- - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IMLS -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ITEST -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_SETGETDCR -#define CONFIG_CMD_SOURCE -#define CONFIG_CMD_XIMG -#define CONFIG_CMD_ZBOOT - -#define CONFIG_BOOTDELAY 15 -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 -#define CONFIG_KGDB_SER_INDEX 2 -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "boot > " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + \ - 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x01000000 -#define CONFIG_SYS_LOAD_ADDR 0x100000 -#define CONFIG_SYS_HZ 1000 - -/*----------------------------------------------------------------------- - * SDRAM Configuration - */ -#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18 -#define CONFIG_SYS_SDRAM_REFRESH_RATE 156 -#define CONFIG_NR_DRAM_BANKS 4 - -/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/ -#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY -#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T - -/*----------------------------------------------------------------------- - * CPU Features - */ -#define CONFIG_SYS_SC520_HIGH_SPEED 0 -#define CONFIG_SYS_SC520_RESET -#define CONFIG_SYS_SC520_TIMER -#undef CONFIG_SYS_GENERIC_TIMER -#define CONFIG_SYS_PCAT_INTERRUPTS -#define CONFIG_SYS_NUM_IRQS 16 -#define CONFIG_SYS_PC_BIOS -#define CONFIG_SYS_PCI_BIOS -#define CONFIG_SYS_X86_REALMODE -#define CONFIG_SYS_X86_ISR_TIMER - -/*----------------------------------------------------------------------- - * Memory organization: - * 32kB Stack - * 16kB Cache-As-RAM @ 0x19200000 - * 256kB Monitor - * (128kB + Environment Sector Size) malloc pool - */ -#define CONFIG_SYS_STACK_SIZE (32 * 1024) -#define CONFIG_SYS_CAR_ADDR 0x19200000 -#define CONFIG_SYS_CAR_SIZE (16 * 1024) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + \ - 128*1024) -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/*----------------------------------------------------------------------- - * FLASH configuration - * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000) - * 16MB StrataFlash #1 @ 0x10000000 - * 16MB StrataFlash #2 @ 0x11000000 - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_MAX_FLASH_BANKS 3 -#define CONFIG_SYS_FLASH_BASE 0x38000000 -#define CONFIG_SYS_FLASH_BASE_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE_2 0x11000000 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE_1, \ - CONFIG_SYS_FLASH_BASE_2} -#define CONFIG_SYS_FLASH_EMPTY_INFO -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_SYS_FLASH_LEGACY_512Kx8 -#define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */ - -/*----------------------------------------------------------------------- - * Environment configuration - * - Boot flash is 512kB with 64kB sectors - * - StrataFlash is 32MB with 128kB sectors - * - Redundant embedded environment is 25% of the Boot flash - * - Redundant StrataFlash environment is <1% of the StrataFlash - * - Environment is therefore located in StrataFlash - * - Primary copy is located in first sector of first flash - * - Redundant copy is located in second sector of first flash - * - Stack is only 32kB, so environment size is limited to 4kB - */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x01000 -#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/*----------------------------------------------------------------------- - * PCI configuration - */ -#define CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_SYS_FIRST_PCI_IRQ 10 -#define CONFIG_SYS_SECOND_PCI_IRQ 9 -#define CONFIG_SYS_THIRD_PCI_IRQ 11 -#define CONFIG_SYS_FORTH_PCI_IRQ 15 - -/*----------------------------------------------------------------------- - * Network device (TRL8100B) support - */ -#define CONFIG_RTL8139 - -/*----------------------------------------------------------------------- - * BOOTCS Control (for AM29LV040B-120JC) - * - * 000 0 00 0 000 11 0 011 }- 0x0033 - * \ / | \| | \ / \| | \ / - * | | | | | | | | - * | | | | | | | +---- 3 Wait States (First Access) - * | | | | | | +------- Reserved - * | | | | | +--------- 3 Wait States (Subsequent Access) - * | | | | +------------- Reserved - * | | | +---------------- Non-Paged Mode - * | | +------------------ 8 Bit Wide - * | +--------------------- GP Bus - * +------------------------ Reserved - */ -#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033 - -/*----------------------------------------------------------------------- - * ROMCS Control (for E28F128J3A-150 StrataFlash) - * - * 000 0 01 1 000 01 0 101 }- 0x0615 - * \ / | \| | \ / \| | \ / - * | | | | | | | | - * | | | | | | | +---- 5 Wait States (First Access) - * | | | | | | +------- Reserved - * | | | | | +--------- 1 Wait State (Subsequent Access) - * | | | | +------------- Reserved - * | | | +---------------- Paged Mode - * | | +------------------ 16 Bit Wide - * | +--------------------- GP Bus - * +------------------------ Reserved - */ -#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615 -#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615 - -/*----------------------------------------------------------------------- - * SC520 General Purpose Bus configuration - * - * Chip Select Offset 1 Clock Cycle - * Chip Select Pulse Width 8 Clock Cycles - * Chip Select Read Offset 2 Clock Cycles - * Chip Select Read Width 6 Clock Cycles - * Chip Select Write Offset 2 Clock Cycles - * Chip Select Write Width 6 Clock Cycles - * Chip Select Recovery Time 2 Clock Cycles - * - * Timing Diagram (from SC520 Register Set Manual - Order #22005B) - * - * |<-------------General Purpose Bus Cycle---------------->| - * | | - * ----------------------\__________________/------------------ - * |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> | - * - * ------------------------\_______________/------------------- - * |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->| - * - * --------------------------\_______________/----------------- - * |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->| - * - * ________/-----------\_______________________________________ - * |<--->|<--------->| - * ^ ^ - * (GPALEOFF + 1) | - * | - * (GPALEW + 1) - */ -#define CONFIG_SYS_SC520_GPCSOFF 0x00 -#define CONFIG_SYS_SC520_GPCSPW 0x07 -#define CONFIG_SYS_SC520_GPRDOFF 0x01 -#define CONFIG_SYS_SC520_GPRDW 0x05 -#define CONFIG_SYS_SC520_GPWROFF 0x01 -#define CONFIG_SYS_SC520_GPWRW 0x05 -#define CONFIG_SYS_SC520_GPCSRT 0x01 - -/*----------------------------------------------------------------------- - * SC520 Programmable I/O configuration - * - * Pin Mode Dir. Description - * ---------------------------------------------------------------------- - * PIO0 PIO Output Unused - * PIO1 GPBHE# Output GP Bus Byte High Enable (active low) - * PIO2 PIO Output Auxiliary power output enable - * PIO3 GPAEN Output GP Bus Address Enable - * PIO4 PIO Output Top Board Enable (active low) - * PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode) - * PIO6 PIO Input Data output of Power Supply ADC - * PIO7 PIO Output Clock input to Power Supply ADC - * PIO8 PIO Output Chip Select input of Power Supply ADC - * PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low) - * PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low) - * PIO11 PIO Input StrataFlash 1 Status - * PIO12 PIO Input StrataFlash 2 Status - * PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low) - * PIO14 PIO Input Low Input Voltage Warning (active low) - * PIO15 PIO Output Watchdog (must toggle at least every 1.6s) - * PIO16 PIO Input Power Fail - * PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low) - * PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low) - * PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low) - * PIO20 GPIRQ3 Input UART D IRQ - * PIO21 GPIRQ2 Input UART C IRQ - * PIO22 GPIRQ1 Input UART B IRQ - * PIO23 GPIRQ0 Input UART A IRQ - * PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable - * PIO25 PIO Input Battery OK Indication - * PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access - * PIO27 GPCS0# Output SRAM 1 Chip Select - * PIO28 PIO Input Top Board UART CTS - * PIO29 PIO Output FPGA Program Mode (active low) - * PIO30 PIO Input FPGA Initialised (active low) - * PIO31 PIO Input FPGA Done (active low) - */ -#define CONFIG_SYS_SC520_PIOPFS15_0 0x200a -#define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe -#define CONFIG_SYS_SC520_PIODIR15_0 0x87bf -#define CONFIG_SYS_SC520_PIODIR31_16 0x2900 - -/*----------------------------------------------------------------------- - * PIO Pin defines - */ -#define CONFIG_SYS_ENET_AUX_PWR 0x0004 -#define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010 -#define CONFIG_SYS_ENET_SF_WIDTH 0x0020 -#define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040 -#define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080 -#define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100 -#define CONFIG_SYS_ENET_SF1_MODE 0x0200 -#define CONFIG_SYS_ENET_SF2_MODE 0x0400 -#define CONFIG_SYS_ENET_SF1_STATUS 0x0800 -#define CONFIG_SYS_ENET_SF2_STATUS 0x1000 -#define CONFIG_SYS_ENET_PWR_STATUS 0x4000 -#define CONFIG_SYS_ENET_WATCHDOG 0x8000 - -#define CONFIG_SYS_ENET_PWR_FAIL 0x0001 -#define CONFIG_SYS_ENET_BAT_OK 0x0200 -#define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000 -#define CONFIG_SYS_ENET_FPGA_PROG 0x2000 -#define CONFIG_SYS_ENET_FPGA_INIT 0x4000 -#define CONFIG_SYS_ENET_FPGA_DONE 0x8000 - -/*----------------------------------------------------------------------- - * Chip Select Pin Function Select - * - * 1 1 1 1 1 0 0 0 }- 0xf8 - * | | | | | | | | - * | | | | | | | +--- Reserved - * | | | | | | +----- GPCS1_SEL = ROMCS1# - * | | | | | +------- GPCS2_SEL = ROMCS2# - * | | | | +--------- GPCS3_SEL = GPCS3 - * | | | +----------- GPCS4_SEL = GPCS4 - * | | +------------- GPCS5_SEL = GPCS5 - * | +--------------- GPCS6_SEL = GPCS6 - * +----------------- GPCS7_SEL = GPCS7 - */ -#define CONFIG_SYS_SC520_CSPFS 0xf8 - -/*----------------------------------------------------------------------- - * Clock Select (CLKTIMER[CLKTEST] pin) - * - * 0 111 00 1 0 }- 0x72 - * | \ / \| | | - * | | | | +--- Pin Disabled - * | | | +----- Pin is an output - * | | +------- Reserved - * | +----------- Disabled (pin stays Low) - * +-------------- Reserved - */ -#define CONFIG_SYS_SC520_CLKSEL 0x72 - -/*----------------------------------------------------------------------- - * Address Decode Control - * - * 0 00 0 0 0 0 0 }- 0x00 - * | \| | | | | | - * | | | | | | +--- Integrated UART 1 is enabled - * | | | | | +----- Integrated UART 2 is enabled - * | | | | +------- Integrated RTC is enabled - * | | | +--------- Reserved - * | | +----------- I/O Hole accesses are forwarded to the external GP bus - * | +------------- Reserved - * +---------------- Write-protect violations do not generate an IRQ - */ -#define CONFIG_SYS_SC520_ADDDECCTL 0x00 - -/*----------------------------------------------------------------------- - * UART Control - * - * 00000 1 1 1 }- 0x07 - * \___/ | | | - * | | | +--- Transmit TC interrupt enable - * | | +----- Receive TC interrupt enable - * | +------- 1.8432 MHz - * +----------- Reserved - */ -#define CONFIG_SYS_SC520_UART1CTL 0x07 -#define CONFIG_SYS_SC520_UART2CTL 0x07 - -/*----------------------------------------------------------------------- - * System Arbiter Control - * - * 00000 1 1 0 }- 0x06 - * \___/ | | | - * | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt - * | | +----- The system arbiter operates in concurrent mode - * | +------- Park the PCI bus on the last master that acquired the bus - * +----------- Reserved - */ -#define CONFIG_SYS_SC520_SYSARBCTL 0x06 - -/*----------------------------------------------------------------------- - * System Arbiter Master Enable - * - * 00000000000 0 0 0 1 1 }- 0x06 - * \_________/ | | | | | - * | | | | | +--- PCI master REQ0 enabled (Ethernet 1) - * | | | | +----- PCI master REQ1 enabled (Ethernet 2) - * | | | +------- PCI master REQ2 disabled - * | | +--------- PCI master REQ3 disabled - * | +----------- PCI master REQ4 disabled - * +------------------ Reserved - */ -#define CONFIG_SYS_SC520_SYSARBMENB 0x0003 - -/*----------------------------------------------------------------------- - * System Arbiter Master Enable - * - * 0 0000 0 00 0000 1 000 }- 0x06 - * | \__/ | \| \__/ | \_/ - * | | | | | | +---- Reserved - * | | | | | +------- Enable CPU-to-PCI bus write posting - * | | | | +---------- Reserved - * | | | +-------------- PCI bus reads to SDRAM are not automatically - * | | | retried - * | | +----------------- Target read FIFOs are not snooped during write - * | | transactions - * | +-------------------- Reserved - * +------------------------ Deassert the PCI bus reset signal - */ -#define CONFIG_SYS_SC520_HBCTL 0x08 - -/*----------------------------------------------------------------------- - * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS - * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800 - * \ / | | | | \----+----/ \-----+------/ - * | | | | | | +---------- Start at 0x38000000 - * | | | | | +----------------------- 512kB Region Size - * | | | | | ((7 + 1) * 64kB) - * | | | | +------------------------------ 64kB Page Size - * | | | +-------------------------------- Writes Enabled (So it can be - * | | | reprogrammed!) - * | | +---------------------------------- Caching Disabled - * | +------------------------------------ Execution Enabled - * +--------------------------------------- BOOTCS - */ -#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800 - -/*----------------------------------------------------------------------- - * Cache-As-RAM (Targets Boot Flash) - * - * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200 - * \ / | | | | \--+--/ \-------+--------/ - * | | | | | | +------------ Start at 0x19200000 - * | | | | | +------------------------- 64k Region Size - * | | | | | ((15 + 1) * 4kB) - * | | | | +------------------------------ 4kB Page Size - * | | | +-------------------------------- Writes Enabled - * | | +---------------------------------- Caching Enabled - * | +------------------------------------ Execution Prevented - * +--------------------------------------- BOOTCS - */ -#define CONFIG_SYS_SC520_CAR_PAR 0x903d9200 - -/*----------------------------------------------------------------------- - * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6 - * - * 001 110 0 000100000 0001000000000000 }- 0x38201000 - * \ / \ / | \---+---/ \------+-------/ - * | | | | +----------- Start at 0x00001000 - * | | | +------------------------ 33 Bytes (0x20 + 1) - * | | +------------------------------ Ignored - * | +--------------------------------- GPCS6 - * +------------------------------------- GP Bus I/O - */ -#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000 - -/*----------------------------------------------------------------------- - * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5 - * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7 - * - * 010 101 0 0000000 100000000000000000 }- 0x54020000 - * 010 111 0 0000000 100000000000000001 }- 0x5c020001 - * \ / \ / | \--+--/ \-------+--------/ - * | | | | +------------ Start at 0x200000000 - * | | | | 0x200010000 - * | | | +------------------------- 4kB Region Size - * | | | ((0 + 1) * 4kB) - * | | +------------------------------ 4k Page Size - * | +--------------------------------- GPCS5 - * | GPCS7 - * +------------------------------------- GP Bus Memory - */ -#define CONFIG_SYS_SC520_CF1_PAR 0x54020000 -#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001 - -/*----------------------------------------------------------------------- - * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0 - * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3 - * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4 - * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5 - * - * 001 000 0 000000111 0001001111111000 }- 0x200713f8 - * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8 - * 001 011 0 000000111 0001001011111000 }- 0x300711f8 - * 001 011 0 000000111 0001001011111000 }- 0x340710f8 - * \ / \ / | \---+---/ \------+-------/ - * | | | | +----------- Start at 0x013f8 - * | | | | 0x012f8 - * | | | | 0x011f8 - * | | | | 0x010f8 - * | | | +------------------------ 33 Bytes (32 + 1) - * | | +------------------------------ Ignored - * | +--------------------------------- GPCS6 - * +------------------------------------- GP Bus I/O - */ -#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8 -#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8 -#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8 -#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8 - -/*----------------------------------------------------------------------- - * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1 - * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2 - * - * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000 - * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100 - * \ / | | | | \----+----/ \-----+------/ - * | | | | | | +---------- Start at 0x10000000 - * | | | | | | 0x11000000 - * | | | | | +----------------------- 16MB Region Size - * | | | | | ((255 + 1) * 64kB) - * | | | | +------------------------------ 64kB Page Size - * | | | +-------------------------------- Writes Enabled - * | | +---------------------------------- Caching Disabled - * | +------------------------------------ Execution Enabled - * +--------------------------------------- ROMCS1 - * ROMCS2 - */ -#define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000 -#define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100 - -/*----------------------------------------------------------------------- - * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0 - * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3 - * - * 010 000 1 00000001111 01100100000000 }- 0x4203d900 - * 010 011 1 00000001111 01100100010000 }- 0x4e03d910 - * \ / \ / | \----+----/ \-----+------/ - * | | | | +---------- Start at 0x19000000 - * | | | | 0x19100000 - * | | | +----------------------- 1MB Region Size - * | | | ((15 + 1) * 64kB) - * | | +------------------------------ 64kB Page Size - * | +--------------------------------- GPCS0 - * | GPCS3 - * +------------------------------------- GP Bus Memory - */ -#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900 -#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910 - -/*----------------------------------------------------------------------- - * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4 - * - * 010 100 0 00000000 11000000100000000 }- 0x50018100 - * \ / \ / | \---+--/ \-------+-------/ - * | | | | +----------- Start at 0x18100000 - * | | | +------------------------ 4kB Region Size - * | | | ((0 + 1) * 4kB) - * | | +------------------------------ 4kB Page Size - * | +--------------------------------- GPCS4 - * +------------------------------------- GP Bus Memory - */ -#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100 - -#endif /* __CONFIG_H */ diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index e59f41e..0e7f924 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -85,6 +85,9 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 +/* define to enable boot progress via leds */ +#define CONFIG_SHOW_BOOT_PROGRESS + /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 @@ -115,7 +118,9 @@ #ifdef CONFIG_BOOT_NAND #define CONFIG_CMD_NAND #endif +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#endif #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_NFS /* NFS support */ diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 6887171..1b51fe2 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -191,7 +191,6 @@ #ifdef CONFIG_CMD_NET #define CONFIG_ETHPRIME "FEC0" #define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_MULTI #define CONFIG_MII #define CONFIG_FEC_XCV_TYPE RMII #endif @@ -274,7 +273,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTARGS "console=ttyAM0,115200n8 " +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " #define CONFIG_BOOTCOMMAND "run bootcmd_net" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index e852e315..bae4ba0 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -42,6 +42,7 @@ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT #define CONFIG_ENV_IS_NOWHERE @@ -77,6 +78,13 @@ "ext2load mmc 0 0x17000000 /boot/uImage;" \ "bootm" +/* LCD support */ +#define CONFIG_LCD +#define CONFIG_PWM_TEGRA +#define CONFIG_VIDEO_TEGRA +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK + #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h new file mode 100644 index 0000000..7983c5d --- /dev/null +++ b/include/configs/mx23_olinuxino.h @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2013 Marek Vasut <marex@denx.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __MX23_OLINUXINO_CONFIG_H__ +#define __MX23_OLINUXINO_CONFIG_H__ + +/* + * SoC configurations + */ +#define CONFIG_MX23 /* i.MX23 SoC */ +#define CONFIG_MXS_GPIO /* GPIO control */ +#define CONFIG_SYS_HZ 1000 /* Ticks per second */ + +#define CONFIG_MACH_TYPE 4105 + +#include <asm/arch/regs-base.h> + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_MISC_INIT + +/* + * SPL + */ +#define CONFIG_SPL +#define CONFIG_SPL_NO_CPU_SUPPORT_CODE +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +/* + * U-Boot Commands + */ +#include <config_cmd_default.h> +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_MMC + +/* + * Memory configurations + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ +#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ +#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ +#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +/* Point initial SP in SRAM so SPL can use it too. */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 +#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +/* + * We need to sacrifice first 4 bytes of RAM here to avoid triggering some + * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot + * binary. In case there was more of this mess, 0x100 bytes are skipped. + */ +#define CONFIG_SYS_TEXT_BASE 0x40000100 + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER + +/* + * Serial Driver + */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ + +/* + * MMC Driver + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_GENERIC_MMC +#define CONFIG_MXS_MMC +#endif + +/* + * APBH DMA + */ +#define CONFIG_APBH_DMA + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_OF_LIBFDT + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OVERWRITE +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (256 * 1024) +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +/* + * Extra Environments + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "update_sd_firmware_filename=u-boot.sd\0" \ + "update_sd_firmware=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if tftp ${update_sd_firmware_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "setexpr fw_sz ${fw_sz} + 1 ; " \ + "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ + "fi ; " \ + "fi\0" \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console=ttyAMA0\0" \ + "fdt_file=imx23-olinuxino.dtb\0" \ + "fdt_addr=0x41000000\0" \ + "boot_fdt=try\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else " \ + "echo ERR: Fail to boot from MMC; " \ + "fi; " \ + "fi; " \ + "else exit; fi" + +#endif /* __MX23_OLINUXINO_CONFIG_H__ */ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h new file mode 100644 index 0000000..c44a8b8 --- /dev/null +++ b/include/configs/mx23evk.h @@ -0,0 +1,202 @@ +/* + * Freescale i.MX23 EVK board config + * + * Copyright (C) 2013 Otavio Salvador <otavio@ossystems.com.br> + * on behalf of O.S. Systems Software LTDA. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef __MX23EVK_CONFIG_H__ +#define __MX23EVK_CONFIG_H__ + +/* SoC configurations */ +#define CONFIG_MX23 /* i.MX23 SoC */ + +#include <asm/arch/regs-base.h> + +#define CONFIG_MXS_GPIO /* GPIO control */ +#define CONFIG_SYS_HZ 1000 /* Ticks per second */ + +#define CONFIG_MACH_TYPE MACH_TYPE_MX23EVK + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_MISC_INIT + +/* SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NO_CPU_SUPPORT_CODE +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +/* U-Boot Commands */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_MMC +#define CONFIG_CMD_BOOTZ + +/* Memory configurations */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ +#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */ +#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ +#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ +#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +/* Point initial SP in SRAM so SPL can use it too. */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 +#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* + * We need to sacrifice first 4 bytes of RAM here to avoid triggering some + * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot + * binary. In case there was more of this mess, 0x100 bytes are skipped. + */ +#define CONFIG_SYS_TEXT_BASE 0x40000100 + +#define CONFIG_ENV_OVERWRITE + +/* U-Boot general configurations */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Serial Driver */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* DMA */ +#define CONFIG_APBH_DMA + +/* MMC Driver */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_MXS_MMC +#endif + +/* Boot Linux */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_OF_LIBFDT + +/* Environment */ +#define CONFIG_ENV_IS_IN_MMC +#ifdef CONFIG_ENV_IS_IN_MMC + #define CONFIG_ENV_OFFSET (256 * 1024) + #define CONFIG_ENV_SIZE (16 * 1024) + #define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +/* Extra Environments */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "update_sd_firmware_filename=u-boot.sd\0" \ + "update_sd_firmware=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if tftp ${update_sd_firmware_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "setexpr fw_sz ${fw_sz} + 1 ; " \ + "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ + "fi ; " \ + "fi\0" \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console=ttyAMA0\0" \ + "fdt_file=imx23-evk.dtb\0" \ + "fdt_addr=0x41000000\0" \ + "boot_fdt=try\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else " \ + "echo ERR: Fail to boot from MMC; " \ + "fi; " \ + "fi; " \ + "else exit; fi" + +#endif /* __MX23EVK_CONFIG_H__ */ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index dd0ef21..71447d9 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -163,7 +163,6 @@ #define CONFIG_NET_MULTI #define CONFIG_ETHPRIME "FEC0" #define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_MULTI #define CONFIG_MII #define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_MX28_FEC_MAC_IN_OCOTP diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h index cda4512..d76357c 100644 --- a/include/configs/mx6qsabre_common.h +++ b/include/configs/mx6qsabre_common.h @@ -91,7 +91,7 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index f4a082a..1583c11 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -19,11 +19,23 @@ #define CONFIG_MMCROOT "/dev/mmcblk0p2" #define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + #include "mx6qsabre_common.h" #define CONFIG_SYS_FSL_USDHC_NUM 2 #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 1 /* Boot partition 1 */ #endif #endif /* __MX6QSABREAUTO_CONFIG_H */ diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index ca4e724..180cb24 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -157,6 +157,9 @@ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ "source ${loadaddr}\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc${mmcdev} ...; " \ "run mmcargs; " \ @@ -164,12 +167,20 @@ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "fi; " \ + "if run loadbootenv; then " \ + "run importbootenv; " \ + "fi;" \ + "if test -n ${uenvcmd}; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "fi;" \ + "if run loaduimage; then " \ + "run mmcboot; " \ "fi; " \ "fi" diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 38c79cf..2edb4aa 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -36,6 +36,7 @@ #define CONFIG_MACH_TYPE MACH_TYPE_PAZ00 #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT /* SD/MMC */ #define CONFIG_MMC @@ -71,6 +72,14 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP +/* LCD support */ +#define CONFIG_LCD +#define CONFIG_PWM_TEGRA +#define CONFIG_VIDEO_TEGRA +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h new file mode 100644 index 0000000..aa90ba9 --- /dev/null +++ b/include/configs/pcm051.h @@ -0,0 +1,301 @@ +/* + * pcm051.h + * + * Phytec phyCORE-AM335x (pcm051) boards information header + * + * Copyright (C) 2013 Lemonage Software GmbH + * Author Lars Poeschel <poeschel@lemonage.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_PCM051_H +#define __CONFIG_PCM051_H + +#define CONFIG_AM33XX + +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> + +#define CONFIG_DMA_COHERENT +#define CONFIG_DMA_COHERENT_SIZE (1 << 20) + +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_SYS_NO_FLASH +#define MACH_TYPE_PCM051 4144 /* Until the next sync */ +#define CONFIG_MACH_TYPE MACH_TYPE_PCM051 + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_VERSION_VARIABLE + +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80007fc0\0" \ + "fdtaddr=0x80000000\0" \ + "rdaddr=0x81000000\0" \ + "bootfile=uImage\0" \ + "fdtfile=pcm051.dtb\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ + "ramrootfstype=ext2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ + "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "ramboot=echo Booting from ramdisk ...; " \ + "run ramargs; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loaduimage; then " \ + "run mmcboot;" \ + "fi;" \ + "fi;" \ + +/* Clock Defines */ +#define V_OSCK 25000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_CMD_ECHO + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * memtest works on 8 MB in DRAM after skipping 32MB from + * start addr of ram disk + */ +#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024)) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ + + (8 * 1024 * 1024)) + +#define CONFIG_SYS_LOAD_ADDR 0x80007fc0 /* Default load address */ +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ + +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +#define CONFIG_SPI +#define CONFIG_OMAP3_SPI +#define CONFIG_MTD_DEVICE +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 24000000 + + /* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 19) /* 512MiB */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + /* Platform/Board specific defs */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CONS_INDEX 1 +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ + +/* I2C Configuration */ +#define CONFIG_I2C +#define CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_DRIVER_OMAP24XX_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + +#define CONFIG_OMAP_GPIO + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ +4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +#define CONFIG_ENV_IS_NOWHERE + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (101 * 1024) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "pcm051 U-Boot SPL" +#define CONFIG_SPL_ETH_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * USB configuration + */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_GADGET +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + +#ifdef CONFIG_MUSB_GADGET +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#endif /* CONFIG_MUSB_GADGET */ + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 0 +#define CONFIG_PHY_SMSC + +#endif /* ! __CONFIG_PCM051_H */ diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h index f807a61..decf8d9 100644 --- a/include/configs/sc_sps_1.h +++ b/include/configs/sc_sps_1.h @@ -158,7 +158,6 @@ #ifdef CONFIG_CMD_NET #define CONFIG_ETHPRIME "FEC0" #define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_MULTI #define CONFIG_MII #define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_PHYLIB diff --git a/include/configs/tec.h b/include/configs/tec.h index 200cf66..caeb9cd 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -36,13 +36,13 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (TEC) # " #define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" -#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011 /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT /* SD/MMC */ #define CONFIG_MMC @@ -85,6 +85,13 @@ "ext2load mmc 0 0x17000000 /boot/uImage;" \ "bootm" +/* LCD support */ +#define CONFIG_LCD +#define CONFIG_PWM_TEGRA +#define CONFIG_VIDEO_TEGRA +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK + #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index ee40cc2..f2a70b1 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -119,33 +119,6 @@ #endif -/* - * Memory layout for where various images get loaded by boot scripts: - * - * scriptaddr can be pretty much anywhere that doesn't conflict with something - * else. Put it above BOOTMAPSZ to eliminate conflicts. - * - * kernel_addr_r must be within the first 128M of RAM in order for the - * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will - * decompress itself to 0x8000 after the start of RAM, kernel_addr_r - * should not overlap that area, or the kernel will have to copy itself - * somewhere else before decompression. Similarly, the address of any other - * data passed to the kernel shouldn't overlap the start of RAM. Pushing - * this up to 16M allows for a sizable kernel to be decompressed below the - * compressed load address. - * - * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for - * the compressed kernel to be up to 16M too. - * - * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows - * for the FDT/DTB to be up to 1M, which is hopefully plenty. - */ -#define MEM_LAYOUT_ENV_SETTINGS \ - "scriptaddr=0x10000000\0" \ - "kernel_addr_r=0x01000000\0" \ - "fdt_addr_r=0x02000000\0" \ - "ramdisk_addr_r=0x02100000\0" \ - #ifdef CONFIG_TEGRA_KEYBOARD #define STDIN_KBD_KBC ",tegra-kbc" #else @@ -160,10 +133,17 @@ #define STDIN_KBD_USB "" #endif +#ifdef CONFIG_VIDEO_TEGRA +#define STDOUT_LCD ",lcd" +#else +#define STDOUT_LCD "" +#endif + #define TEGRA_DEVICE_SETTINGS \ "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB "\0" \ - "stdout=serial,lcd\0" \ - "stderr=serial,lcd\0" \ + "stdout=serial" STDOUT_LCD "\0" \ + "stderr=serial" STDOUT_LCD "\0" \ + "" #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h new file mode 100644 index 0000000..4a656bb --- /dev/null +++ b/include/configs/tegra-common.h @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __TEGRA_COMMON_H +#define __TEGRA_COMMON_H +#include <asm/sizes.h> +#include <linux/stringify.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ +#define CONFIG_TEGRA /* which is a Tegra generic machine */ +#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ + +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#include <asm/arch/tegra.h> /* get chip and board defs */ + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_OF_LIBFDT /* enable passing of devicetree */ + +/* Environment */ +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ + +/* + * PllX Configuration + */ +#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 + +/* include default commands */ +#include <config_cmd_default.h> + +/* remove unused commands */ +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration support */ +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_NFS /* NFS support */ +#undef CONFIG_CMD_NET /* network support */ + +/* turn on command-line edit/hist/auto */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_COMMAND_HISTORY +#define CONFIG_AUTO_COMPLETE + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT V_PROMPT +/* + * Increasing the size of the IO buffer as default nfsargs size is more + * than 256 and so it is not possible to edit it + */ +#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) + +#define CONFIG_SYS_HZ 1000 + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 NV_PA_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ + +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ + +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_TEGRA_GPIO +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_ENTERRCM +#define CONFIG_CMD_BOOTZ + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SPL_TEXT_BASE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +#endif /* _TEGRA_COMMON_H_ */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h new file mode 100644 index 0000000..0033530 --- /dev/null +++ b/include/configs/tegra114-common.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA114_COMMON_H_ +#define _TEGRA114_COMMON_H_ +#include "tegra-common.h" + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +/* + * High Level Configuration Options + */ +#define CONFIG_TEGRA114 /* in a NVidia Tegra114 core */ + +/* Environment information, boards can override if required */ +#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ +#define CONFIG_STACKBASE 0x82800000 /* 40MB */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_SYS_TEXT_BASE 0x8010E000 + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x82100000\0" + +/* Defines for SPL */ +#define CONFIG_SPL_TEXT_BASE 0x80108000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 +#define CONFIG_SPL_STACK 0x800ffffc + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra114/u-boot-spl.lds" + +#endif /* _TEGRA114_COMMON_H_ */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index fe07f72..33e5f52 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -21,80 +21,81 @@ * MA 02111-1307 USA */ -#ifndef __TEGRA20_COMMON_H -#define __TEGRA20_COMMON_H -#include <asm/sizes.h> -#include <linux/stringify.h> +#ifndef _TEGRA20_COMMON_H_ +#define _TEGRA20_COMMON_H_ +#include "tegra-common.h" + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ /* * High Level Configuration Options */ -#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ -#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */ -#define CONFIG_TEGRA /* which is a Tegra generic machine */ -#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ +#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */ -#define CONFIG_SYS_CACHELINE_SIZE 32 +/* Environment information, boards can override if required */ +#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */ -#include <asm/arch/tegra.h> /* get chip and board defs */ +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */ +#define CONFIG_STACKBASE 0x02800000 /* 40MB */ -/* Align LCD to 1MB boundary */ -#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_SYS_TEXT_BASE 0x0010E000 /* - * Display CPU and Board information + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x10000000\0" \ + "kernel_addr_r=0x01000000\0" \ + "fdt_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x02100000\0" -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_OF_LIBFDT /* enable passing of devicetree */ +/* Defines for SPL */ +#define CONFIG_SPL_TEXT_BASE 0x00108000 +#define CONFIG_SYS_SPL_MALLOC_START 0x00090000 +#define CONFIG_SPL_STACK 0x000ffffc + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds" + +/* Align LCD to 1MB boundary */ +#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE #ifdef CONFIG_TEGRA_LP0 #define TEGRA_LP0_ADDR 0x1C406000 #define TEGRA_LP0_SIZE 0x2000 #define TEGRA_LP0_VEC \ - "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ + "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ "@" __stringify(TEGRA_LP0_ADDR) " " #else #define TEGRA_LP0_VEC #endif -/* Environment */ -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ - -/* - * PllX Configuration - */ -#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 1 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - /* * This parameter affects a TXFILLTUNING field that controls how much data is * sent to the latency fifo before it is sent to the wire. Without this @@ -107,105 +108,13 @@ /* Total I2C ports on Tegra20 */ #define TEGRA_I2C_NUM_CONTROLLERS 4 -/* include default commands */ -#include <config_cmd_default.h> #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART -/* remove unused commands */ -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#undef CONFIG_CMD_FPGA /* FPGA configuration support */ -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_NFS /* NFS support */ -#undef CONFIG_CMD_NET /* network support */ - -/* turn on command-line edit/hist/auto */ -#define CONFIG_CMDLINE_EDITING -#define CONFIG_COMMAND_HISTORY -#define CONFIG_AUTO_COMPLETE - -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */ -#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT V_PROMPT -/* - * Increasing the size of the IO buffer as default nfsargs size is more - * than 256 and so it is not possible to edit it - */ -#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) - -#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_STACKBASE 0x2800000 /* 40MB */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 NV_PA_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ - -#define CONFIG_SYS_TEXT_BASE 0x0010c000 -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_TEGRA_GPIO -#define CONFIG_CMD_GPIO -#define CONFIG_CMD_ENTERRCM -#define CONFIG_CMD_BOOTZ - -/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_RAM_DEVICE -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_TEXT_BASE 0x00108000 -#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SYS_SPL_MALLOC_START 0x00090000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 -#define CONFIG_SPL_STACK 0x000ffffc - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds" - #define CONFIG_SYS_NAND_SELF_INIT #define CONFIG_SYS_NAND_ONFI_DETECTION /* Misc utility code */ #define CONFIG_BOUNCE_BUFFER -#endif /* __TEGRA20_COMMON_H */ +#endif /* _TEGRA20_COMMON_H_ */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h new file mode 100644 index 0000000..04517e1 --- /dev/null +++ b/include/configs/tegra30-common.h @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA30_COMMON_H_ +#define _TEGRA30_COMMON_H_ +#include "tegra-common.h" + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +/* + * High Level Configuration Options + */ +#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */ + +/* Environment information, boards can override if required */ +#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ +#define CONFIG_STACKBASE 0x82800000 /* 40MB */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_SYS_TEXT_BASE 0x8010E000 + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x82100000\0" + +/* Defines for SPL */ +#define CONFIG_SPL_TEXT_BASE 0x80108000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 +#define CONFIG_SPL_STACK 0x800ffffc + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra30/u-boot-spl.lds" + +/* Total I2C ports on Tegra30 */ +#define TEGRA_I2C_NUM_CONTROLLERS 5 + +#endif /* _TEGRA30_COMMON_H_ */ diff --git a/include/fdt.h b/include/fdt.h index c51212e..f9612ed 100644 --- a/include/fdt.h +++ b/include/fdt.h @@ -4,45 +4,45 @@ #ifndef __ASSEMBLY__ struct fdt_header { - uint32_t magic; /* magic word FDT_MAGIC */ - uint32_t totalsize; /* total size of DT block */ - uint32_t off_dt_struct; /* offset to structure */ - uint32_t off_dt_strings; /* offset to strings */ - uint32_t off_mem_rsvmap; /* offset to memory reserve map */ - uint32_t version; /* format version */ - uint32_t last_comp_version; /* last compatible version */ + fdt32_t magic; /* magic word FDT_MAGIC */ + fdt32_t totalsize; /* total size of DT block */ + fdt32_t off_dt_struct; /* offset to structure */ + fdt32_t off_dt_strings; /* offset to strings */ + fdt32_t off_mem_rsvmap; /* offset to memory reserve map */ + fdt32_t version; /* format version */ + fdt32_t last_comp_version; /* last compatible version */ /* version 2 fields below */ - uint32_t boot_cpuid_phys; /* Which physical CPU id we're + fdt32_t boot_cpuid_phys; /* Which physical CPU id we're booting on */ /* version 3 fields below */ - uint32_t size_dt_strings; /* size of the strings block */ + fdt32_t size_dt_strings; /* size of the strings block */ /* version 17 fields below */ - uint32_t size_dt_struct; /* size of the structure block */ + fdt32_t size_dt_struct; /* size of the structure block */ }; struct fdt_reserve_entry { - uint64_t address; - uint64_t size; + fdt64_t address; + fdt64_t size; }; struct fdt_node_header { - uint32_t tag; + fdt32_t tag; char name[0]; }; struct fdt_property { - uint32_t tag; - uint32_t len; - uint32_t nameoff; + fdt32_t tag; + fdt32_t len; + fdt32_t nameoff; char data[0]; }; #endif /* !__ASSEMBLY */ #define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ -#define FDT_TAGSIZE sizeof(uint32_t) +#define FDT_TAGSIZE sizeof(fdt32_t) #define FDT_BEGIN_NODE 0x1 /* Start node: full name */ #define FDT_END_NODE 0x2 /* End node */ @@ -51,11 +51,11 @@ struct fdt_property { #define FDT_NOP 0x4 /* nop */ #define FDT_END 0x9 -#define FDT_V1_SIZE (7*sizeof(uint32_t)) -#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(uint32_t)) -#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(uint32_t)) +#define FDT_V1_SIZE (7*sizeof(fdt32_t)) +#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t)) +#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t)) #define FDT_V16_SIZE FDT_V3_SIZE -#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(uint32_t)) +#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t)) /* adding a ramdisk needs 0x44 bytes in version 2008.10 */ #define FDT_RAMDISK_OVERHEAD 0x80 diff --git a/include/fdt_support.h b/include/fdt_support.h index 4b9f84a..2cccc35 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -26,7 +26,7 @@ #ifdef CONFIG_OF_LIBFDT -#include <fdt.h> +#include <libfdt.h> u32 fdt_getprop_u32_default(const void *fdt, const char *path, const char *prop, const u32 dflt); @@ -92,7 +92,7 @@ int fdt_fixup_nor_flash_size(void *blob); void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size); void fdt_del_node_and_alias(void *blob, const char *alias); -u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr); +u64 fdt_translate_address(void *blob, int node_offset, const __be32 *in_addr); int fdt_node_offset_by_compat_reg(void *blob, const char *compat, phys_addr_t compat_off); int fdt_alloc_phandle(void *blob); diff --git a/include/fdtdec.h b/include/fdtdec.h index f77d195..77f244f 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -70,6 +70,8 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ + COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */ + COMPAT_NVIDIA_TEGRA20_SLINK, /* Tegra 2 SPI SLINK controller */ COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */ COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */ COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */ diff --git a/include/image.h b/include/image.h index f5adc50..8e285f9 100644 --- a/include/image.h +++ b/include/image.h @@ -52,7 +52,6 @@ #endif /* USE_HOSTCC */ #if defined(CONFIG_FIT) -#include <fdt.h> #include <libfdt.h> #include <fdt_support.h> #define CONFIG_MD5 /* FIT images need MD5 support */ diff --git a/include/libfdt.h b/include/libfdt.h index c93ae28..fc7f75b 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -882,8 +882,8 @@ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, const char *name, uint32_t val) { - val = cpu_to_fdt32(val); - return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val)); + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); } /** @@ -917,8 +917,8 @@ static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, const char *name, uint64_t val) { - val = cpu_to_fdt64(val); - return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val)); + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); } /** @@ -993,13 +993,13 @@ int fdt_begin_node(void *fdt, const char *name); int fdt_property(void *fdt, const char *name, const void *val, int len); static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) { - val = cpu_to_fdt32(val); - return fdt_property(fdt, name, &val, sizeof(val)); + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); } static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) { - val = cpu_to_fdt64(val); - return fdt_property(fdt, name, &val, sizeof(val)); + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); } static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) { @@ -1154,8 +1154,8 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, uint32_t val) { - val = cpu_to_fdt32(val); - return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val)); + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); } /** @@ -1189,8 +1189,8 @@ static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, uint64_t val) { - val = cpu_to_fdt64(val); - return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val)); + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); } /** @@ -1296,8 +1296,8 @@ int fdt_appendprop(void *fdt, int nodeoffset, const char *name, static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, const char *name, uint32_t val) { - val = cpu_to_fdt32(val); - return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val)); + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); } /** @@ -1331,8 +1331,8 @@ static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, const char *name, uint64_t val) { - val = cpu_to_fdt64(val); - return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val)); + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); } /** diff --git a/include/libfdt_env.h b/include/libfdt_env.h index bf63583..3e3defc 100644 --- a/include/libfdt_env.h +++ b/include/libfdt_env.h @@ -22,9 +22,14 @@ #define _LIBFDT_ENV_H #include "compiler.h" +#include "linux/types.h" extern struct fdt_header *working_fdt; /* Pointer to the working fdt */ +typedef __be16 fdt16_t; +typedef __be32 fdt32_t; +typedef __be64 fdt64_t; + #define fdt32_to_cpu(x) be32_to_cpu(x) #define cpu_to_fdt32(x) cpu_to_be32(x) #define fdt64_to_cpu(x) be64_to_cpu(x) diff --git a/include/netdev.h b/include/netdev.h index 7f158d4..fd3e243 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -215,9 +215,16 @@ struct mv88e61xx_config { int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); #endif /* CONFIG_MV88E61XX_SWITCH */ +struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id); +#ifdef CONFIG_PHYLIB +struct phy_device; +int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, + struct mii_dev *bus, struct phy_device *phydev); +#else /* * Allow FEC to fine-tune MII configuration on boards which require this. */ int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)); +#endif #endif /* _NETDEV_H_ */ diff --git a/include/phy.h b/include/phy.h index 3c30f11..58ca273 100644 --- a/include/phy.h +++ b/include/phy.h @@ -199,6 +199,9 @@ static inline int is_10g_interface(phy_interface_t interface) int phy_init(void); int phy_reset(struct phy_device *phydev); +struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, + phy_interface_t interface); +void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); struct phy_device *phy_connect(struct mii_dev *bus, int addr, struct eth_device *dev, phy_interface_t interface); diff --git a/include/serial.h b/include/serial.h index 14f863e..f6bb2b9 100644 --- a/include/serial.h +++ b/include/serial.h @@ -32,7 +32,7 @@ extern struct serial_device *default_serial_console(void); defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \ defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \ - defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT) || \ + defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \ defined(CONFIG_MICROBLAZE) extern struct serial_device serial0_device; extern struct serial_device serial1_device; |