diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/ppc4xx-isram.h | 75 | ||||
| -rw-r--r-- | include/configs/PCI405.h | 57 | ||||
| -rw-r--r-- | include/configs/canyonlands.h | 2 | ||||
| -rw-r--r-- | include/configs/katmai.h | 8 | ||||
| -rw-r--r-- | include/ppc440.h | 54 |
5 files changed, 94 insertions, 102 deletions
diff --git a/include/asm-ppc/ppc4xx-isram.h b/include/asm-ppc/ppc4xx-isram.h new file mode 100644 index 0000000..d6d17ac --- /dev/null +++ b/include/asm-ppc/ppc4xx-isram.h @@ -0,0 +1,75 @@ + +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC4xx_ISRAM_H_ +#define _PPC4xx_ISRAM_H_ + +/* + * Internal SRAM + */ +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define ISRAM0_DCR_BASE 0x380 +#else +#define ISRAM0_DCR_BASE 0x020 +#endif +#define ISRAM0_SB0CR (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ +#define ISRAM0_SB1CR (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/ +#define ISRAM0_SB2CR (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/ +#define ISRAM0_SB3CR (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/ +#define ISRAM0_BEAR (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ +#define ISRAM0_BESR0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ +#define ISRAM0_BESR1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ +#define ISRAM0_PMEG (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ +#define ISRAM0_CID (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ +#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ +#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define ISRAM1_DCR_BASE 0x0B0 +#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ +#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ +#define ISRAM1_BESR0 (ISRAM1_DCR_BASE+0x05) /* SRAM1 bus error status reg 0 */ +#define ISRAM1_BESR1 (ISRAM1_DCR_BASE+0x06) /* SRAM1 bus error status reg 1 */ +#define ISRAM1_PMEG (ISRAM1_DCR_BASE+0x07) /* SRAM1 power management */ +#define ISRAM1_CID (ISRAM1_DCR_BASE+0x08) /* SRAM1 bus core id reg */ +#define ISRAM1_REVID (ISRAM1_DCR_BASE+0x09) /* SRAM1 bus revision id reg */ +#define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */ +#endif /* CONFIG_460EX || CONFIG_460GT */ + +/* + * L2 Cache + */ +#if defined (CONFIG_440GX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) +#define L2_CACHE_BASE 0x030 +#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ +#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ +#define L2_CACHE_ADDR (L2_CACHE_BASE+0x02) /* L2 Cache Address */ +#define L2_CACHE_DATA (L2_CACHE_BASE+0x03) /* L2 Cache Data */ +#define L2_CACHE_STAT (L2_CACHE_BASE+0x04) /* L2 Cache Status */ +#define L2_CACHE_CVER (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */ +#define L2_CACHE_SNP0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */ +#define L2_CACHE_SNP1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */ +#endif /* CONFIG_440GX */ + +#endif /* _PPC4xx_ISRAM_H_ */ diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 0393366..d0a37d7 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -60,39 +60,24 @@ #define CONFIG_PREBOOT /* enable preboot variable */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - /* * Command line configuration. */ #include <config_cmd_default.h> +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_ITEST +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + #define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ #define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE #define CONFIG_CMD_I2C #define CONFIG_CMD_BSP #define CONFIG_CMD_EEPROM - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -102,7 +87,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ @@ -166,15 +150,9 @@ #define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#if 0 /* test-only */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -#else #define CONFIG_SYS_PCI_PTM2LA 0xef600000 /* point to internal regs */ #define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ -#endif /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -215,22 +193,10 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#if 0 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */ - -#else /* Use EEPROM for environment variables */ - #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ #define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/ /* total size of a CAT24WC08 is 1024 bytes */ -#endif #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ @@ -327,14 +293,6 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */ -#if 0 /* test-only */ -#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#else /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ #define CONFIG_SYS_TEMP_STACK_OCM 1 /* On Chip Memory location */ @@ -346,7 +304,6 @@ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#endif /* * Internal Definitions diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index f8e8801..faf6304 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -102,7 +102,7 @@ #define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \ (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) -#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 16k */ +#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 58694cc..ea6cf0d 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -53,6 +53,13 @@ #define CONFIG_HOSTNAME katmai #include "amcc-common.h" +/* + * For booting 256K-paged Linux we should have 16MB of memory + * for Linux initial memory map + */ +#undef CONFIG_SYS_BOOTMAPSZ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #undef CONFIG_SHOW_BOOT_PROGRESS @@ -189,6 +196,7 @@ /* * Commands additional to the ones defined in amcc-common.h */ +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_DATE #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM diff --git a/include/ppc440.h b/include/ppc440.h index ea0ac86..01f6eaf 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -169,18 +169,9 @@ #define sdr_ecid1 0x0081 #define sdr_ecid2 0x0082 #define sdr_jtag 0x00c0 -#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) -#define sdr_ddrdl 0x00e0 -#else -#define sdr_cfg 0x00e0 -#define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/ -#define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */ -#define SDR_CFG_32BITS 0x00000000 /* 32 bits */ -#define SDR_CFG_64BITS 0x01000000 /* 64 bits */ -#define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */ -#define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */ -#define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */ -#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */ +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define SDR0_DDRCFG 0x00e0 +#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ #define sdr_ebc 0x0100 #define sdr_uart0 0x0120 /* UART0 Config */ #define sdr_uart1 0x0121 /* UART1 Config */ @@ -616,45 +607,6 @@ #endif /* 440EP || 440GR || 440EPX || 440GRX */ -/*----------------------------------------------------------------------------- - | L2 Cache - +----------------------------------------------------------------------------*/ -#if defined (CONFIG_440GX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) -#define L2_CACHE_BASE 0x030 -#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */ -#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */ -#define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */ -#define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */ -#define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */ -#define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */ -#define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */ -#define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */ - -#endif /* CONFIG_440GX */ - -/*----------------------------------------------------------------------------- - | Internal SRAM - +----------------------------------------------------------------------------*/ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define ISRAM0_DCR_BASE 0x380 -#else -#define ISRAM0_DCR_BASE 0x020 -#endif -#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ -#define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/ -#define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/ -#define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/ -#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ -#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ -#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ -#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ -#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ -#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ -#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ - #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) |