diff options
Diffstat (limited to 'include')
57 files changed, 1943 insertions, 309 deletions
diff --git a/include/asm-blackfin/bfin_logo_rgb565_230x230.h b/include/asm-blackfin/bfin_logo_rgb565_230x230.h new file mode 100644 index 0000000..c5b0be9 --- /dev/null +++ b/include/asm-blackfin/bfin_logo_rgb565_230x230.h @@ -0,0 +1,1242 @@ +/* + * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi + * + * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y) + * + * Where: 'screen' is the pointer to the frame buffer + * 'width' is the screen width + * 'x' is the horizontal position + * 'y' is the vertical position + */ + +#define EASYLOGO_ENABLE_GZIP 19303 + +static unsigned char EASYLOGO_DECOMP_BUFFER[105800]; + +#include <video_easylogo.h> + +#define DEF_BFIN_LOGO_WIDTH 230 +#define DEF_BFIN_LOGO_HEIGHT 230 +#define DEF_BFIN_LOGO_PIXELS 52900 +#define DEF_BFIN_LOGO_BPP 16 +#define DEF_BFIN_LOGO_PIXEL_SIZE 2 +#define DEF_BFIN_LOGO_SIZE 105800 + +unsigned char DEF_BFIN_LOGO_DATA[] = { + 0x1f, 0x8b, 0x08, 0x00, 0x9d, 0x56, 0x26, 0x4b, 0x00, 0x03, 0xec, 0x5d, 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0xc9, 0x08, + 0xf8, 0x86, 0xe8, 0x13, 0xb4, 0x47, 0x11, 0xa7, 0x77, 0xa8, 0x98, 0xd8, 0xb4, 0x64, 0xd3, 0xa2, + 0x61, 0xd3, 0x38, 0xb3, 0xf3, 0xdc, 0x41, 0x90, 0xde, 0x0b, 0x95, 0xcb, 0xf7, 0xce, 0x14, 0xf8, + 0x86, 0x4f, 0xff, 0x11, 0x26, 0xe5, 0xd8, 0xcd, 0x96, 0xff, 0x17, 0xd8, 0x7d, 0xcf, 0x6f, 0x5c, + 0xec, 0xa7, 0xa1, 0x48, 0x9d, 0x01, 0x00 +}; + +fastimage_t bfin_logo = { + DEF_BFIN_LOGO_DATA, + DEF_BFIN_LOGO_WIDTH, + DEF_BFIN_LOGO_HEIGHT, + DEF_BFIN_LOGO_BPP, + DEF_BFIN_LOGO_PIXEL_SIZE, + DEF_BFIN_LOGO_SIZE +}; diff --git a/include/asm-blackfin/blackfin_local.h b/include/asm-blackfin/blackfin_local.h index 8ec7928..3fd34b3 100644 --- a/include/asm-blackfin/blackfin_local.h +++ b/include/asm-blackfin/blackfin_local.h @@ -25,6 +25,8 @@ #ifndef __BLACKFIN_LOCAL_H__ #define __BLACKFIN_LOCAL_H__ +#include <asm/mem_map.h> + #define LO(con32) ((con32) & 0xFFFF) #define lo(con32) ((con32) & 0xFFFF) #define HI(con32) (((con32) >> 16) & 0xFFFF) @@ -59,7 +61,7 @@ extern u_long get_vco(void); extern u_long get_cclk(void); extern u_long get_sclk(void); -# define bfin_revid() (*pCHIPID >> 28) +# define bfin_revid() (bfin_read_CHIPID() >> 28) extern bool bfin_os_log_check(void); extern void bfin_os_log_dump(void); diff --git a/include/asm-blackfin/config-pre.h b/include/asm-blackfin/config-pre.h index b1d3a94..1170a2a 100644 --- a/include/asm-blackfin/config-pre.h +++ b/include/asm-blackfin/config-pre.h @@ -71,4 +71,7 @@ static inline const char *get_bfin_boot_mode(int bfin_boot) # define BFIN_BOOT_SPI_SSEL 1 #endif +/* We rarely use interrupts, so favor throughput over latency */ +#define CONFIG_BFIN_INS_LOWOVERHEAD + #endif diff --git a/include/asm-blackfin/config.h b/include/asm-blackfin/config.h index 327843d..0ae838a 100644 --- a/include/asm-blackfin/config.h +++ b/include/asm-blackfin/config.h @@ -79,6 +79,11 @@ # define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL #endif +/* We need envcrc to embed the env into LDRs */ +#ifdef CONFIG_ENV_IS_EMBEDDED_IN_LDR +# define CONFIG_BUILD_ENVCRC +#endif + /* Default/common Blackfin memory layout */ #ifndef CONFIG_SYS_SDRAM_BASE # define CONFIG_SYS_SDRAM_BASE 0 @@ -87,7 +92,11 @@ # define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024) #endif #ifndef CONFIG_SYS_MONITOR_BASE -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN) +# if CONFIG_SYS_MAX_RAM_SIZE +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN) +# else +# define CONFIG_SYS_MONITOR_BASE 0 +# endif #endif #ifndef CONFIG_SYS_MALLOC_BASE # define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) @@ -109,7 +118,8 @@ #endif /* Check to make sure everything fits in external RAM */ -#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE) +#if CONFIG_SYS_MAX_RAM_SIZE && \ + ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE) # error Memory Map does not fit into configuration #endif diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h index b78b04c..c7099e6 100644 --- a/include/asm-blackfin/global_data.h +++ b/include/asm-blackfin/global_data.h @@ -28,6 +28,8 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include <asm/u-boot.h> + /* * The following data structure is placed in some memory wich is * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index 6806494..75244a0 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -1,25 +1,9 @@ /* * U-boot - io.h IO routines * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright 2004-2009 Analog Devices Inc. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ #ifndef _BLACKFIN_IO_H @@ -29,17 +13,13 @@ #include <asm/blackfin.h> +#define __iomem + static inline void sync(void) { SSYNC(); } -/* function prototypes for CF support */ -extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words); -extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words); -extern unsigned char cf_inb(volatile unsigned char *addr); -extern void cf_outb(unsigned char val, volatile unsigned char *addr); - /* * Given a physical address and a length, return a virtual address * that can be used to access the memory range with the caching @@ -76,114 +56,172 @@ static inline phys_addr_t virt_to_phys(void * vaddr) * * readX/writeX() are used to access memory mapped devices. On some * architectures the memory mapped IO stuff needs to be accessed - * differently. On the m68k architecture, we just read/write the + * differently. On the bfin architecture, we just read/write the * memory location directly. */ - #ifndef __ASSEMBLY__ -static inline unsigned char readb(const volatile void *addr) +static inline unsigned char readb(const volatile void __iomem *addr) { unsigned int val; int tmp; - __asm__ __volatile__ ("cli %1;\n\t" - "NOP; NOP; SSYNC;\n\t" - "%0 = b [%2] (z);\n\t" - "sti %1;\n\t" - : "=d"(val), "=d"(tmp): "a"(addr)); + __asm__ __volatile__ ( + "cli %1;" + "NOP; NOP; SSYNC;" + "%0 = b [%2] (z);" + "sti %1;" + : "=d"(val), "=d"(tmp) + : "a"(addr) + ); return (unsigned char) val; } -static inline unsigned short readw(const volatile void *addr) +static inline unsigned short readw(const volatile void __iomem *addr) { unsigned int val; int tmp; - __asm__ __volatile__ ("cli %1;\n\t" - "NOP; NOP; SSYNC;\n\t" - "%0 = w [%2] (z);\n\t" - "sti %1;\n\t" - : "=d"(val), "=d"(tmp): "a"(addr)); + __asm__ __volatile__ ( + "cli %1;" + "NOP; NOP; SSYNC;" + "%0 = w [%2] (z);" + "sti %1;" + : "=d"(val), "=d"(tmp) + : "a"(addr) + ); return (unsigned short) val; } -static inline unsigned int readl(const volatile void *addr) +static inline unsigned int readl(const volatile void __iomem *addr) { unsigned int val; int tmp; - __asm__ __volatile__ ("cli %1;\n\t" - "NOP; NOP; SSYNC;\n\t" - "%0 = [%2];\n\t" - "sti %1;\n\t" - : "=d"(val), "=d"(tmp): "a"(addr)); + __asm__ __volatile__ ( + "cli %1;" + "NOP; NOP; SSYNC;" + "%0 = [%2];" + "sti %1;" + : "=d"(val), "=d"(tmp) + : "a"(addr) + ); + return val; } -#define __raw_readb readb -#define __raw_readw readw -#define __raw_readl readl - #endif /* __ASSEMBLY__ */ #define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) #define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b)) #define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) + +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel - #define memset_io(a, b, c) memset((void *)(a), (b), (c)) #define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) #define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) -#define inb(addr) cf_inb((volatile unsigned char *)(addr)) -#define outb(x, addr) cf_outb((unsigned char)(x), (volatile unsigned char *)(addr)) - -#define insw(port, addr, count) cf_insw((unsigned short *)addr, (unsigned short *)(port), (count)) +/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */ +#define __io(port) ((void *)(unsigned long)(port)) + +#define inb(port) readb(__io(port)) +#define inw(port) readw(__io(port)) +#define inl(port) readl(__io(port)) +#define outb(x, port) writeb(x, __io(port)) +#define outw(x, port) writew(x, __io(port)) +#define outl(x, port) writel(x, __io(port)) + +#define inb_p(port) inb(__io(port)) +#define inw_p(port) inw(__io(port)) +#define inl_p(port) inl(__io(port)) +#define outb_p(x, port) outb(x, __io(port)) +#define outw_p(x, port) outw(x, __io(port)) +#define outl_p(x, port) outl(x, __io(port)) + +#define ioread8_rep(a, d, c) readsb(a, d, c) +#define ioread16_rep(a, d, c) readsw(a, d, c) +#define ioread32_rep(a, d, c) readsl(a, d, c) +#define iowrite8_rep(a, s, c) writesb(a, s, c) +#define iowrite16_rep(a, s, c) writesw(a, s, c) +#define iowrite32_rep(a, s, c) writesl(a, s, c) + +#define ioread8(x) readb(x) +#define ioread16(x) readw(x) +#define ioread32(x) readl(x) +#define iowrite8(val, x) writeb(val, x) +#define iowrite16(val, x) writew(val, x) +#define iowrite32(val, x) writel(val, x) + +#define mmiowb() wmb() -#define outsw(port, addr, count) cf_outsw((unsigned short *)(port), (unsigned short *)addr, (count)) +#ifndef __ASSEMBLY__ -#define IO_SPACE_LIMIT 0xffff +extern void outsb(unsigned long port, const void *addr, unsigned long count); +extern void outsw(unsigned long port, const void *addr, unsigned long count); +extern void outsw_8(unsigned long port, const void *addr, unsigned long count); +extern void outsl(unsigned long port, const void *addr, unsigned long count); -/* Values for nocacheflag and cmode */ -#define IOMAP_FULL_CACHING 0 -#define IOMAP_NOCACHE_SER 1 -#define IOMAP_NOCACHE_NONSER 2 -#define IOMAP_WRITETHROUGH 3 +extern void insb(unsigned long port, void *addr, unsigned long count); +extern void insw(unsigned long port, void *addr, unsigned long count); +extern void insw_8(unsigned long port, void *addr, unsigned long count); +extern void insl(unsigned long port, void *addr, unsigned long count); +extern void insl_16(unsigned long port, void *addr, unsigned long count); -extern void *__ioremap(unsigned long physaddr, unsigned long size, - int cacheflag); -extern void __iounmap(void *addr, unsigned long size); +static inline void readsl(const void __iomem *addr, void *buf, int len) +{ + insl((unsigned long)addr, buf, len); +} -extern inline void *ioremap(unsigned long physaddr, unsigned long size) +static inline void readsw(const void __iomem *addr, void *buf, int len) { - return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); + insw((unsigned long)addr, buf, len); } -extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size) + +static inline void readsb(const void __iomem *addr, void *buf, int len) { - return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); + insb((unsigned long)addr, buf, len); } -extern inline void *ioremap_writethrough(unsigned long physaddr, - unsigned long size) + +static inline void writesl(const void __iomem *addr, const void *buf, int len) { - return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); + outsl((unsigned long)addr, buf, len); } -extern inline void *ioremap_fullcache(unsigned long physaddr, - unsigned long size) + +static inline void writesw(const void __iomem *addr, const void *buf, int len) { - return __ioremap(physaddr, size, IOMAP_FULL_CACHING); + outsw((unsigned long)addr, buf, len); } -extern void iounmap(void *addr); +static inline void writesb(const void __iomem *addr, const void *buf, int len) +{ + outsb((unsigned long)addr, buf, len); +} -extern void blkfin_inv_cache_all(void); -#define dma_cache_inv(_start, _size) do { blkfin_inv_cache_all(); } while (0) -#define dma_cache_wback(_start, _size) do { } while (0) -#define dma_cache_wback_inv(_start, _size) do { blkfin_inv_cache_all(); } while (0) +#if defined(CONFIG_STAMP_CF) || defined(CONFIG_BFIN_IDE) +/* This hack for CF/IDE needs to be addressed at some point */ +extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words); +extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words); +extern unsigned char cf_inb(volatile unsigned char *addr); +extern void cf_outb(unsigned char val, volatile unsigned char *addr); +#undef inb +#undef outb +#undef insw +#undef outsw +#define inb(addr) cf_inb((void *)(addr)) +#define outb(x, addr) cf_outb((unsigned char)(x), (void *)(addr)) +#define insw(port, addr, cnt) cf_insw((void *)(addr), (void *)(port), cnt) +#define outsw(port, addr, cnt) cf_outsw((void *)(port), (void *)(addr), cnt) +#endif #endif + +#endif /* __KERNEL__ */ + #endif diff --git a/include/asm-blackfin/mach-bf527/BF522_def.h b/include/asm-blackfin/mach-bf527/BF522_def.h index 44143ba..bc05029 100644 --- a/include/asm-blackfin/mach-bf527/BF522_def.h +++ b/include/asm-blackfin/mach-bf527/BF522_def.h @@ -119,20 +119,5 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF522_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF523_def.h b/include/asm-blackfin/mach-bf527/BF523_def.h index 02675a9..c27fd64 100644 --- a/include/asm-blackfin/mach-bf527/BF523_def.h +++ b/include/asm-blackfin/mach-bf527/BF523_def.h @@ -119,20 +119,5 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF523_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF524_def.h b/include/asm-blackfin/mach-bf527/BF524_def.h index 10793e8..bd6aa8f 100644 --- a/include/asm-blackfin/mach-bf527/BF524_def.h +++ b/include/asm-blackfin/mach-bf527/BF524_def.h @@ -288,20 +288,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF524_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF525_def.h b/include/asm-blackfin/mach-bf527/BF525_def.h index c4c2f2f..5e88b3b 100644 --- a/include/asm-blackfin/mach-bf527/BF525_def.h +++ b/include/asm-blackfin/mach-bf527/BF525_def.h @@ -288,20 +288,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF525_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF526_def.h b/include/asm-blackfin/mach-bf527/BF526_def.h index 04db6c7..2644abf 100644 --- a/include/asm-blackfin/mach-bf527/BF526_def.h +++ b/include/asm-blackfin/mach-bf527/BF526_def.h @@ -367,20 +367,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF526_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF527_def.h b/include/asm-blackfin/mach-bf527/BF527_def.h index c1e1aab..c46c2b0 100644 --- a/include/asm-blackfin/mach-bf527/BF527_def.h +++ b/include/asm-blackfin/mach-bf527/BF527_def.h @@ -367,20 +367,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF527_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/def_local.h b/include/asm-blackfin/mach-bf527/def_local.h index 14c111f..81eca83 100644 --- a/include/asm-blackfin/mach-bf527/def_local.h +++ b/include/asm-blackfin/mach-bf527/def_local.h @@ -1 +1,2 @@ +#include "mem_map.h" #include "ports.h" diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h new file mode 100644 index 0000000..8386b4b --- /dev/null +++ b/include/asm-blackfin/mach-bf527/mem_map.h @@ -0,0 +1,21 @@ +/* + * Common Blackfin memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __BF52X_MEM_MAP_H__ +#define __BF52X_MEM_MAP_H__ + +#define L1_DATA_A_SRAM (0xFF800000) +#define L1_DATA_A_SRAM_SIZE (0x4000) +#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) +#define L1_DATA_B_SRAM (0xFF900000) +#define L1_DATA_B_SRAM_SIZE (0x4000) +#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) +#define L1_INST_SRAM (0xFFA00000) +#define L1_INST_SRAM_SIZE (0xC000) +#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) + +#endif diff --git a/include/asm-blackfin/mach-bf548/BF542_def.h b/include/asm-blackfin/mach-bf548/BF542_def.h index 40fe555..1324a13 100644 --- a/include/asm-blackfin/mach-bf548/BF542_def.h +++ b/include/asm-blackfin/mach-bf548/BF542_def.h @@ -113,20 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF542_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF544_def.h b/include/asm-blackfin/mach-bf548/BF544_def.h index 042e2ac..aef6e48 100644 --- a/include/asm-blackfin/mach-bf548/BF544_def.h +++ b/include/asm-blackfin/mach-bf548/BF544_def.h @@ -113,20 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF544_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF547_def.h b/include/asm-blackfin/mach-bf548/BF547_def.h index 1cb3381..ce7c880 100644 --- a/include/asm-blackfin/mach-bf548/BF547_def.h +++ b/include/asm-blackfin/mach-bf548/BF547_def.h @@ -113,14 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF547_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF548_def.h b/include/asm-blackfin/mach-bf548/BF548_def.h index 950ce43..e02e843 100644 --- a/include/asm-blackfin/mach-bf548/BF548_def.h +++ b/include/asm-blackfin/mach-bf548/BF548_def.h @@ -113,20 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF548_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF549_def.h b/include/asm-blackfin/mach-bf548/BF549_def.h index 55b0a29..a16ff5a 100644 --- a/include/asm-blackfin/mach-bf548/BF549_def.h +++ b/include/asm-blackfin/mach-bf548/BF549_def.h @@ -113,20 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF549_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/def_local.h b/include/asm-blackfin/mach-bf548/def_local.h index 14c111f..81eca83 100644 --- a/include/asm-blackfin/mach-bf548/def_local.h +++ b/include/asm-blackfin/mach-bf548/def_local.h @@ -1 +1,2 @@ +#include "mem_map.h" #include "ports.h" diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h new file mode 100644 index 0000000..4f94397 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/mem_map.h @@ -0,0 +1,21 @@ +/* + * Common Blackfin memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __BF54X_MEM_MAP_H__ +#define __BF54X_MEM_MAP_H__ + +#define L1_DATA_A_SRAM (0xFF800000) +#define L1_DATA_A_SRAM_SIZE (0x4000) +#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) +#define L1_DATA_B_SRAM (0xFF900000) +#define L1_DATA_B_SRAM_SIZE (0x4000) +#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) +#define L1_INST_SRAM (0xFFA00000) +#define L1_INST_SRAM_SIZE (0xC000) +#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) + +#endif diff --git a/include/asm-blackfin/mem_map.h b/include/asm-blackfin/mem_map.h new file mode 100644 index 0000000..3e361d6 --- /dev/null +++ b/include/asm-blackfin/mem_map.h @@ -0,0 +1,26 @@ +/* + * Common Blackfin memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MEM_MAP_H__ +#define __BFIN_MEM_MAP_H__ + +/* Every Blackfin so far has MMRs like this */ +#ifndef COREMMR_BASE +# define COREMMR_BASE 0xFFE00000 +#endif +#ifndef SYSMMR_BASE +# define SYSMMR_BASE 0xFFC00000 +#endif + +/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */ +#ifndef L1_SRAM_SCRATCH +# define L1_SRAM_SCRATCH 0xFFB00000 +# define L1_SRAM_SCRATCH_SIZE 0x1000 +# define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) +#endif + +#endif diff --git a/include/asm-blackfin/mmc.h b/include/asm-blackfin/mmc.h deleted file mode 100644 index aa2ac95..0000000 --- a/include/asm-blackfin/mmc.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-avr32/arch-at32ap700x/mmc.h> diff --git a/include/asm-blackfin/sdh.h b/include/asm-blackfin/sdh.h new file mode 100644 index 0000000..2c2f63e --- /dev/null +++ b/include/asm-blackfin/sdh.h @@ -0,0 +1,17 @@ +/* + * sdh.h, export bfin_mmc_init + * + * Copyright (c) 2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_SDH_H__ +#define __ASM_SDH_H__ + +#include <mmc.h> +#include <asm/u-boot.h> + +int bfin_mmc_init(bd_t *bis); + +#endif diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h index 18306dd..117f44c 100644 --- a/include/asm-blackfin/string.h +++ b/include/asm-blackfin/string.h @@ -29,9 +29,6 @@ #ifdef __KERNEL__ /* only set these up for kernel code */ -#include <config.h> -#include <asm/blackfin.h> - #define __HAVE_ARCH_STRCPY #define __HAVE_ARCH_STRNCPY #define __HAVE_ARCH_STRCMP @@ -47,7 +44,7 @@ extern int strcmp(const char *cs, const char *ct); extern int strncmp(const char *cs, const char *ct, size_t count); extern void *memcpy(void *dest, const void *src, size_t count); extern void *memset(void *s, int c, size_t count); -extern int memcmp(const void *, const void *, __kernel_size_t); +extern int memcmp(const void *, const void *, size_t); extern void *memmove(void *dest, const void *src, size_t count); #else /* KERNEL */ diff --git a/include/common.h b/include/common.h index 07897f6..391790a 100644 --- a/include/common.h +++ b/include/common.h @@ -336,7 +336,9 @@ extern void pic_write (uchar reg, uchar val); #if defined(CONFIG_SPI) || !defined(CONFIG_SYS_I2C_EEPROM_ADDR) # define CONFIG_SYS_DEF_EEPROM_ADDR 0 #else +#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) # define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR +#endif #endif /* CONFIG_SPI || !defined(CONFIG_SYS_I2C_EEPROM_ADDR) */ #if defined(CONFIG_SPI) @@ -617,6 +619,13 @@ int gunzip(void *, int, unsigned char *, unsigned long *); int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, int stoponerr, int offset); +/* lib_generic/net_utils.c */ +#include <net.h> +static inline IPaddr_t getenv_IPaddr (char *var) +{ + return (string_to_ip(getenv(var))); +} + /* lib_generic/time.c */ void udelay (unsigned long); diff --git a/include/compiler.h b/include/compiler.h index e602cce..332618e 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -125,4 +125,7 @@ typedef unsigned int uintptr_t; /* compiler options */ #define uninitialized_var(x) x = x +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) + #endif diff --git a/include/config_defaults.h b/include/config_defaults.h new file mode 100644 index 0000000..08b6ede --- /dev/null +++ b/include/config_defaults.h @@ -0,0 +1,17 @@ +/* + * config_defaults.h - sane defaults for everyone + * + * Copyright (c) 2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _CONFIG_DEFAULTS_H_ +#define _CONFIG_DEFAULTS_H_ + +/* Support bootm-ing different OSes */ +#define CONFIG_BOOTM_LINUX 1 +#define CONFIG_BOOTM_NETBSD 1 +#define CONFIG_BOOTM_RTEMS 1 + +#endif diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index 3db8171..1e821d9 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -53,7 +53,7 @@ #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MALLOC_LEN (384 * 1024) @@ -109,7 +109,7 @@ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x2000 #endif -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR /* @@ -125,6 +125,7 @@ * SDH Settings */ #if !defined(__ADSPBF512__) +#define CONFIG_GENERIC_MMC #define CONFIG_MMC #define CONFIG_BFIN_SDH #endif diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index 97853af..711fa27 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -126,7 +126,7 @@ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x2000 #endif -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR /* diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index 0d02354..7800c32 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -61,7 +61,8 @@ * (can't be used same time as ethernet) */ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -#define CONFIG_BFIN_NFC +# define CONFIG_BFIN_NFC +# define CONFIG_BFIN_NFC_BOOTROM_ECC #endif #ifdef CONFIG_BFIN_NFC #define CONFIG_BFIN_NFC_CTL_VAL 0x0033 @@ -69,7 +70,6 @@ #define CONFIG_SYS_NAND_BASE 0 /* not actually used */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 -#define CONFIG_CMD_NAND #endif @@ -118,14 +118,19 @@ #define CONFIG_ENV_OFFSET 0x10000 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SIZE 0x20000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_OFFSET 0x4000 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x2000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif -#define ENV_IS_EMBEDDED_CUSTOM /* @@ -150,6 +155,15 @@ /* + * Video Settings + */ +#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1 +# define CONFIG_LQ035Q1_SPI_BUS 0 +# define CONFIG_LQ035Q1_SPI_CS 7 +#endif + + +/* * Misc Settings */ #define CONFIG_MISC_INIT_R diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 0006b02..083c030 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -117,7 +117,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h index 463b7d0..86aa1f6 100644 --- a/include/configs/bf537-minotaur.h +++ b/include/configs/bf537-minotaur.h @@ -115,7 +115,7 @@ #define CONFIG_ENV_OFFSET 0x10000 #define CONFIG_ENV_SIZE 0x10000 #define CONFIG_ENV_SECT_SIZE 0x10000 -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR /* diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index 0f908ef..6627a04 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -94,7 +94,7 @@ * Env Storage Settings */ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_OFFSET 0x4000 #else diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h index 7368629..7e9dd36 100644 --- a/include/configs/bf537-srv1.h +++ b/include/configs/bf537-srv1.h @@ -115,7 +115,7 @@ #define CONFIG_ENV_OFFSET 0x10000 #define CONFIG_ENV_SIZE 0x10000 #define CONFIG_ENV_SECT_SIZE 0x10000 -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR /* diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 74b9ecd..de2add7 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -113,7 +113,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -145,7 +145,7 @@ * SPI_MMC Settings */ #define CONFIG_MMC -#define CONFIG_BFIN_SPI_MMC +#define CONFIG_SPI_MMC /* diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index c4d899d..4ea2300 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -110,7 +110,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index 5b9de16..f9c9711 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -107,7 +107,7 @@ #define CONFIG_ENV_OFFSET 0x10000 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x10000 -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x40000 @@ -118,7 +118,7 @@ #define CONFIG_ENV_OFFSET 0x2000 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif @@ -133,7 +133,6 @@ #define CONFIG_SYS_NAND_BASE 0 /* not actually used */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 -#define CONFIG_CMD_NAND /* @@ -162,6 +161,7 @@ * SDH Settings */ #if !defined(__ADSPBF544__) +#define CONFIG_GENERIC_MMC #define CONFIG_MMC #define CONFIG_BFIN_SDH #endif diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h new file mode 100644 index 0000000..0be170c --- /dev/null +++ b/include/configs/bf561-acvilon.h @@ -0,0 +1,178 @@ +/* + * U-boot - Configuration file for BF561 Acvilon System On Module + * For more information please go to http://www.niistt.ru/ + */ + +#ifndef __CONFIG_BF561_ACVILON_H__ +#define __CONFIG_BF561_ACVILON_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf561-0.5 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 12000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 50 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 10 +#define CONFIG_MEM_SIZE 128 + +#define CONFIG_EBIU_SDRRC_VAL 0x300 +#define CONFIG_EBIU_SDGCTL_VAL 0x00B11189 + +#define CONFIG_EBIU_AMGCTL_VAL 0x4e +#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 +#define CONFIG_EBIU_AMBCTL1_VAL 0x99b35554 + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * RTC Settings + */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CONFIG_SYS_I2C_DTT_ADDR 0x49 +/*#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3*/ + + +/* + * Network Settings + */ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_NET_MULTI +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DTT + +#if defined(CONFIG_CMD_NET) + +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_32_BIT +/* #define CONFIG_SMC911X_16_BIT */ +#define CONFIG_SMC911X_BASE 0x28000000 + +#endif /* (CONFIG_CMD_NET) */ + +#define CONFIG_HOSTNAME bf561-acvilon + +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_SYS_NO_FLASH + + +/* + * I2C Settings + */ +#define CONFIG_HARD_I2C +/* Use 300kHz speed by default */ +#define CONFIG_SYS_I2C_SPEED 0x00 +#define CONFIG_PCA9564_I2C +#define CONFIG_PCA9564_BASE 0x2c000000 + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +/* #define CONFIG_CMD_SAVEENV */ +#define CONFIG_ENV_SECT_SIZE (1056 * 8) +#define CONFIG_ENV_OFFSET ((16 + 256) * 1056) +#define CONFIG_ENV_SIZE (8 * 1056) +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) + + +/* + * NAND Settings + * We're using NAND_PLAT driver to make things simplier + */ +#define CONFIG_NAND_PLAT +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BASE 0x24000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3)) +#define BFIN_NAND_READY PF10 +#define BFIN_NAND_WRITE(addr, cmd) \ + do { \ + bfin_write8(addr, cmd); \ + SSYNC(); \ + } while (0) + +#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) +#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) +#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO0_FLAG_D() & BFIN_NAND_READY) +#define NAND_PLAT_INIT() \ + do { \ + bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() & ~BFIN_NAND_READY); \ + bfin_write_FIO0_INEN(bfin_read_FIO0_INEN() | BFIN_NAND_READY); \ + } while (0) + + +/* + * Misc Settings + */ +#define CONFIG_UART_CONSOLE 0 +#define CONFIG_BAUDRATE 57600 +#define CONFIG_SYS_PROMPT "Acvilon> " + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif /* __CONFIG_BF561_ACVILON_H__ */ diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index a1fa80b..8ab38bb 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -87,7 +87,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 0fbd8f4..6a2f1c7 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -45,7 +45,7 @@ # define CONFIG_CMD_USB_STORAGE # define CONFIG_DOS_PARTITION # endif -# ifdef CONFIG_NAND_PLAT +# if defined(CONFIG_NAND_PLAT) || defined(CONFIG_DRIVER_NAND_BFIN) # define CONFIG_CMD_NAND # endif # ifdef CONFIG_POST @@ -75,6 +75,9 @@ # else # define CONFIG_CMD_JFFS2 # endif +# ifdef CONFIG_CMD_JFFS2 +# define CONFIG_JFFS2_SUMMARY +# endif # define CONFIG_CMD_BOOTLDR # define CONFIG_CMD_CACHE # define CONFIG_CMD_CPLBINFO @@ -96,6 +99,7 @@ #define CONFIG_AUTO_COMPLETE 1 #define CONFIG_LOADS_ECHO 1 #define CONFIG_JTAG_CONSOLE +#define CONFIG_SILENT_CONSOLE #ifndef CONFIG_BAUDRATE # define CONFIG_BAUDRATE 57600 #endif @@ -127,6 +131,9 @@ #ifndef CONFIG_BOOTARGS_ROOT # define CONFIG_BOOTARGS_ROOT "/dev/mtdblock0 rw" #endif +#ifndef FLASHBOOT_ENV_SETTINGS +# define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20100000\0" +#endif #define CONFIG_BOOTARGS \ "root=" CONFIG_BOOTARGS_ROOT " " \ "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \ @@ -174,7 +181,19 @@ "erase 0x20000000 +$(filesize);" \ "cp.b $(loadaddr) 0x20000000 $(filesize)" # endif +# ifdef CONFIG_NETCONSOLE +# define NETCONSOLE_ENV \ + "nc=" \ + "set ncip ${serverip};" \ + "set stdin nc;" \ + "set stdout nc" \ + "\0" +# else +# define NETCONSOLE_ENV +# endif # define NETWORK_ENV_SETTINGS \ + NETCONSOLE_ENV \ + \ "ubootfile=" UBOOT_ENV_FILE "\0" \ "update=" \ "tftp $(loadaddr) $(ubootfile);" \ @@ -211,7 +230,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ NAND_ENV_SETTINGS \ NETWORK_ENV_SETTINGS \ - "flashboot=bootm 0x20100000\0" + FLASHBOOT_ENV_SETTINGS /* * Network Settings diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h index 1592719..ad1dd12 100644 --- a/include/configs/cm-bf527.h +++ b/include/configs/cm-bf527.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 4 +/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_120 | CLKBUFOE | FREQ_1000) + /* * Memory Settings @@ -105,8 +108,8 @@ #define CONFIG_ENV_ADDR 0x20008000 #define CONFIG_ENV_OFFSET 0x8000 #define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR /* @@ -125,6 +128,10 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS \ + "flashboot=flread 20040000 1000000 300000;" \ + "bootm 0x1000000\0" /* diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h index 06eb288..7515296 100644 --- a/include/configs/cm-bf533.h +++ b/include/configs/cm-bf533.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 5 +/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000) + /* * Memory Settings @@ -93,6 +96,8 @@ */ #define CONFIG_BAUDRATE 115200 #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" /* diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index 34d4299..0d68eba 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 4 +/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000) + /* * Memory Settings @@ -92,7 +95,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -127,6 +130,10 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS \ + "flashboot=flread 20040000 1000000 300000;" \ + "bootm 0x1000000\0" /* diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index d1870a8..c1179b0 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -96,7 +96,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -131,6 +131,10 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS \ + "flashboot=flread 20040000 1000000 280000;" \ + "bootm 0x1000000\0" /* @@ -138,13 +142,4 @@ */ #include <configs/bfin_adi_common.h> -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "run flashboot" - -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - NAND_ENV_SETTINGS \ - NETWORK_ENV_SETTINGS \ - "flashboot=flread 20040000 1000000 280000; bootm 0x1000000\0" - #endif diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h index b5cfc21..93c4c8d 100644 --- a/include/configs/cm-bf548.h +++ b/include/configs/cm-bf548.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 4 +/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000) + /* * Memory Settings @@ -96,7 +99,7 @@ #define CONFIG_ENV_ADDR 0x20008000 #define CONFIG_ENV_OFFSET 0x8000 #define CONFIG_ENV_SIZE 0x8000 -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR /* @@ -115,6 +118,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 1 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" #ifndef __ADSPBF542__ /* Don't waste time transferring a logo over the UART */ diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h index 4a77435..1741ed4 100644 --- a/include/configs/cm-bf561.h +++ b/include/configs/cm-bf561.h @@ -30,7 +30,7 @@ #define CONFIG_PLL_BYPASS 0 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ /* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 22 +#define CONFIG_VCO_MULT 20 /* CCLK_DIV controls the core clock divider */ /* Values can be 1, 2, 4, or 8 ONLY */ #define CONFIG_CCLK_DIV 1 @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 5 +/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) + /* * Memory Settings @@ -98,6 +101,8 @@ */ #define CONFIG_BAUDRATE 115200 #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" /* diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h index 066859f..7c9f71e 100644 --- a/include/configs/ibf-dsp561.h +++ b/include/configs/ibf-dsp561.h @@ -75,7 +75,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index 2ef6a35..729d1c0 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -125,7 +125,7 @@ #define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* UBI Support for all Keymile boards */ #define CONFIG_CMD_UBI diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index b023326..71658d8 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -33,6 +33,11 @@ /* include common defines/options for all Keymile boards */ #include "keymile-common.h" +#define MTDIDS_DEFAULT "nor0=boot" +#define MTDPARTS_DEFAULT \ + "mtdparts=boot:768k(u-boot),128k(env),128k(envred)," \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")" + #define CONFIG_MISC_INIT_R 1 /* * System Clock Setup @@ -152,7 +157,6 @@ */ #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CONFIG_SYS_FLASH_BASE 0xF0000000 -#define CONFIG_SYS_FLASH_BASE_1 0xF2000000 #define CONFIG_SYS_PIGGY_BASE 0xE8000000 #define CONFIG_SYS_PIGGY_SIZE 128 #define CONFIG_SYS_PAXE_BASE 0xA0000000 @@ -213,9 +217,9 @@ OR_GPCM_SCY_5 | \ OR_GPCM_TRLX | OR_GPCM_EAD) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 } +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } #undef CONFIG_SYS_FLASH_CHECKSUM diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h new file mode 100644 index 0000000..9c04d8a --- /dev/null +++ b/include/configs/tcm-bf518.h @@ -0,0 +1,129 @@ +/* + * U-boot - Configuration file for Bluetechnix TCM-BF518 board + */ + +#ifndef __CONFIG_TCM_BF518_H__ +#define __CONFIG_TCM_BF518_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf518-0.0 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 16 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 4 + + +/* + * Memory Settings + */ +/* This board has a 32meg MT48H16M16 */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL 0x3f8 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (384 * 1024) + + +/* + * Network Settings + */ +#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__) +#define ADI_CMDS_NETWORK 1 +#define CONFIG_BFIN_MAC +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 +#endif +#define CONFIG_HOSTNAME tcm-bf518 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 19 + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 9794e1b..5a5fbdd 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 4 +/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000) + /* * Memory Settings @@ -93,7 +96,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -128,6 +131,10 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS \ + "flashboot=flread 20040000 1000000 280000;" \ + "bootm 0x1000000\0" /* diff --git a/include/jffs2/jffs2.h b/include/jffs2/jffs2.h index ed96bab..651f94c 100644 --- a/include/jffs2/jffs2.h +++ b/include/jffs2/jffs2.h @@ -68,10 +68,9 @@ #define JFFS2_COMPR_COPY 0x04 #define JFFS2_COMPR_DYNRUBIN 0x05 #define JFFS2_COMPR_ZLIB 0x06 -#if defined(CONFIG_JFFS2_LZO_LZARI) +#if defined(CONFIG_JFFS2_LZO) #define JFFS2_COMPR_LZO 0x07 -#define JFFS2_COMPR_LZARI 0x08 -#define JFFS2_NUM_COMPR 9 +#define JFFS2_NUM_COMPR 8 #else #define JFFS2_NUM_COMPR 7 #endif @@ -226,11 +225,9 @@ void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, unsigned long sourcelen, unsigned long dstlen); long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out, __u32 srclen, __u32 destlen); -#if defined(CONFIG_JFFS2_LZO_LZARI) +#if defined(CONFIG_JFFS2_LZO) int lzo_decompress(unsigned char *data_in, unsigned char *cpage_out, u32 srclen, u32 destlen); -int lzari_decompress(unsigned char *data_in, unsigned char *cpage_out, - u32 srclen, u32 destlen); #endif char *mkmodestr(unsigned long mode, char *str); diff --git a/include/linux/mtd/compat.h b/include/linux/mtd/compat.h index f0c8464..39c693f 100644 --- a/include/linux/mtd/compat.h +++ b/include/linux/mtd/compat.h @@ -48,8 +48,5 @@ #define BUG_ON(condition) do { if (condition) BUG(); } while(0) #endif /* BUG */ -#define likely(x) __builtin_expect(!!(x), 1) -#define unlikely(x) __builtin_expect(!!(x), 0) - #define PAGE_SIZE 4096 #endif diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index 476d149..4dcf90c 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -947,6 +947,23 @@ struct mpc5xxx_mscan { struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */ }; +struct mpc5xxx_xlb { + volatile u8 reserved[0x40]; /* XLB + 0x00 */ + volatile u32 config; /* XLB + 0x40 */ + volatile u32 version; /* XLB + 0x44 */ + volatile u32 status; /* XLB + 0x48 */ + volatile u32 int_enable; /* XLB + 0x4c */ + volatile u32 addr_capture; /* XLB + 0x50 */ + volatile u32 bus_sig_capture; /* XLB + 0x54 */ + volatile u32 addr_timeout; /* XLB + 0x58 */ + volatile u32 data_timeout; /* XLB + 0x5c */ + volatile u32 bus_act_timeout; /* XLB + 0x60 */ + volatile u32 master_pri_enable; /* XLB + 0x64 */ + volatile u32 master_priority; /* XLB + 0x68 */ + volatile u32 base_address; /* XLB + 0x6c */ + volatile u32 snoop_window; /* XLB + 0x70 */ +}; + /* function prototypes */ void loadtask(int basetask, int tasks); diff --git a/include/net.h b/include/net.h index 1c8ab12..3f6a5d1 100644 --- a/include/net.h +++ b/include/net.h @@ -508,9 +508,6 @@ extern void VLAN_to_string (ushort x, char *s); /* Convert a string to a vlan id */ extern ushort string_to_VLAN(char *s); -/* read an IP address from a environment variable */ -extern IPaddr_t getenv_IPaddr (char *); - /* read a VLAN id from an environment variable */ extern ushort getenv_VLAN(char *); diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index 3b99456..f48945a 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -112,7 +112,7 @@ struct usb_ehci { u32 perlistbase; /* 0x154 - Periodic List Base - USB Device Address */ u32 ep_list_addr; /* 0x158 - Next Asynchronous List - - End Point Address */ + - Endpoint Address */ u8 res5[0x4]; u32 burstsize; /* 0x160 - Programmable Burst Size */ u32 txfilltuning; /* 0x164 - Host TT Transmit @@ -124,17 +124,17 @@ struct usb_ehci { u32 portsc; /* 0x184 - Port status/control */ u8 res8[0x20]; u32 usbmode; /* 0x1a8 - USB Device Mode */ - u32 epsetupstat; /* 0x1ac - End Point Setup Status */ - u32 epprime; /* 0x1b0 - End Point Init Status */ - u32 epflush; /* 0x1b4 - End Point De-initlialize */ - u32 epstatus; /* 0x1b8 - End Point Status */ - u32 epcomplete; /* 0x1bc - End Point Complete */ - u32 epctrl0; /* 0x1c0 - End Point Control 0 */ - u32 epctrl1; /* 0x1c4 - End Point Control 1 */ - u32 epctrl2; /* 0x1c8 - End Point Control 2 */ - u32 epctrl3; /* 0x1cc - End Point Control 3 */ - u32 epctrl4; /* 0x1d0 - End Point Control 4 */ - u32 epctrl5; /* 0x1d4 - End Point Control 5 */ + u32 epsetupstat; /* 0x1ac - Endpoint Setup Status */ + u32 epprime; /* 0x1b0 - Endpoint Init Status */ + u32 epflush; /* 0x1b4 - Endpoint De-initlialize */ + u32 epstatus; /* 0x1b8 - Endpoint Status */ + u32 epcomplete; /* 0x1bc - Endpoint Complete */ + u32 epctrl0; /* 0x1c0 - Endpoint Control 0 */ + u32 epctrl1; /* 0x1c4 - Endpoint Control 1 */ + u32 epctrl2; /* 0x1c8 - Endpoint Control 2 */ + u32 epctrl3; /* 0x1cc - Endpoint Control 3 */ + u32 epctrl4; /* 0x1d0 - Endpoint Control 4 */ + u32 epctrl5; /* 0x1d4 - Endpoint Control 5 */ u8 res9[0x228]; u32 snoop1; /* 0x400 - Snoop 1 */ u32 snoop2; /* 0x404 - Snoop 2 */ |